Texas Instruments TPS3125L30DBVT, TPS3125J18DBVT, TPS3125L30DBVR, TPS3125J18DBVR, TPS3125J12DBVT Datasheet

...
TPS3123J12, TPS3123G15, TPS3123J18, TPS3124J12, TPS3124G15
TPS3124J18, TPS3125J12, TPS3125G15, TPS3125J18, TPS3125L30
ULTRA-LOW VOLTAGE PROCESSOR SUPERVISORY CIRCUITS
SLVS227 – AUGUST 1999
features
D
D
Supply Voltage Supervision Range: – 1.2 V, 1.5 V, 1.8 V (TPS3123, TPS3124,
TPS3125)
– 3 V (TPS3125 Devices only)
D
Power-On Reset Generator With Fixed Delay Time of 180 ms
D
Manual Reset Input (TPS3123 and TPS3125)
D
Watchdog Timer Retriggers the RESET Output at V
D
Supply Current of 14 µA (Typ)
D
SOT23–5 Package
D
T emperature Range ...–40°C to 85°C
2.5 V 1.2 V
V
DD
V
DD
MR
TPS3125J12
GND
IT
RESET
CV
TMS320UVC5402
DD
DV
DD
typical applications
D
Applications Using Low Voltage DSPs, Microcontrollers or Microprocessors
D
Wireless Communication Systems
D
Portable/Battery-Powered Equipment
D
Programmable Controls
D
Intelligent Instruments
D
Industrial Equipment
D
Notebook/Desktop Computers
D
Automotive Systems
DBV PACKAGE
(TOP VIEW)
1
TPS3123
2
3
1
TPS3124
2
3
5
4
5
4
RESET
GND
MR
RESET
GND
RESET
V
DD
WDI
V
DD
WDI
MR
V
RESET
DD
TPS3823-25
GND
WDI
XF RESET
GND
RESET
GND
RESET
1
TPS3125
2
3
V
5
4
DD
MR
Figure 1. Typical Dual-Voltage DSP Application
description
The TPS3123, TPS3124, TPS3125 family of ultra-low voltage processor supervisory circuits provides circuit initialization and timing supervision, primarily for DSP and processor-based systems.
During power-on, RESET the supply voltage supervisor monitors V threshold voltage VIT. An internal timer delays the return of the output to the inactive state (high) to ensure proper system reset. The delay time, t
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
is asserted when the supply voltage (VDD) becomes higher than 0.75 V . Thereafter,
and keeps RESET output active as long as VDD remains below the
DD
= 180 ms starts after VDD has risen above the threshold voltage VIT.
dtyp
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 1999, Texas Instruments Incorporated
1
TPS3123J12, TPS3123G15, TPS3123J18, TPS3124J12, TPS3124G15
40°C to 85_C
TPS3124J18, TPS3125J12, TPS3125G15, TPS3125J18, TPS3125L30 ULTRA-LOW VOLTAGE PROCESSOR SUPERVISORY CIRCUITS
SLVS227 – AUGUST 1999
description (continued)
When the supply voltage drops below the threshold voltage VIT, the output becomes active (low) again. No external components are required. All the devices of this family have a fixed-sense threshold voltage VIT set by an internal voltage divider.
The TPS3123-xx and TPS3125-xx devices incorporate a manual reset input, MR. A low level at MR causes RESET RESET same as the TPS3125-xx devices. In addition the TPS3123-xx and TPS3124-xx have a watchdog timer that need to be triggered periodically by a positive or negative transition at WDI. When the supervising system fails to retrigger the watchdog circuit within the time-out interval t the time period td. This event also reinitializes the watchdog timer.
The circuits are available in a 5-pin SOT23-5 package. The TPS3123, TPS3124, TPS3125 devices are characterized for operation over a temperature range of –40°C to 85°C.
to become active. The TPS3124-xx devices do not have the input MR, but include a high-level output
= 0.8 s, RESET output becomes active for
tout
PACKAGE INFORMATION STANDARD VERSIONS
T
A
TPS3123J12DBVR
TPS3123G15DBVR†TPS3123G15DBVT
TPS3123J18DBVR TPS3124J12DBVR
°
The DBVR passive indicates tape and reel of 3000 parts.
The DBVT passive indicates tape and reel of 250 parts.
TPS3124G15DBVR†TPS3124G15DBVT
_
TPS3124J18DBVR TPS3125J12DBVR
TPS3125G15DBVR†TPS3125G15DBVT
TPS3125J18DBVR
TPS3125L30DBVR
DEVICE NAME THRESHOLD VOLTAGE MARKING
TPS3123J12DBVT
TPS3123J18DBVT
TPS3124J12DBVT
TPS3124J18DBVT
TPS3125J12DBVT
TPS3125J18DBVT
TPS3125L30DBVT
‡ ‡ ‡
‡ ‡ ‡
‡ ‡ ‡
1.08 V PBNI
1.40 V PBOI
1.62 V PBPI
1.08 V PBQI
1.40 V PBRI
1.62 V PBSI
1.08 V PBTI
1.40 V PBUI
1.62 V PBVI
2.64 V PBXI
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TPS3123J12, TPS3123G15, TPS3123J18, TPS3124J12, TPS3124G15
TPS3124J18, TPS3125J12, TPS3125G15, TPS3125J18, TPS3125L30
ULTRA-LOW VOLTAGE PROCESSOR SUPERVISORY CIRCUITS
ordering information application specific versions
TPS312 3 J 12 DBV R
Nominal Supply Voltage
Typical Reset Threshold Voltage
Functionality
Family
SLVS227 – AUGUST 1999
Reel
Package
DEVICE NAME
TPS312xx12DBV 1.2 V TPS312xAxxDBV V TPS312xx15DBV 1.5 V TPS312xBxxDBV V TPS312xx18DBV 1.8 V TPS312xCxxDBV V TPS312xx30DBV 3.0 V TPS312xDxxDBV V
NOTE: Ten standard versions will be available at product introduction.
For the application specific versions contact the local TI sales office for availability and lead time.
NOMINAL SUPPLY
VOLTAGE, V
NOM
DEVICE NAME
TPS312xExxDBV V TPS312xFxxDBV V TPS312xGxxDBV V TPS312xHxxDBV V
TPS312xIxxDBV V
TPS312xJxxDBV V TPS312xKxxDBV V TPS312xLxxDBV V TPS312xMxxDBV V TPS312xNxxDBV V TPS312xOxxDBV V
Function Tables
TPS3123 TPS3124 TPS3125
VDD > VITRESET VDD > VITRESET RESET MR VDD > VITRESET RESET
MR
L 0 L 0 L H L 0 L H
L 1 L 1 H L L 1 L H H 0 L H 0 L H H 1 H H 1 H L
TYPICAL RESET
THRESHOLD
VOLTAGE–V
NOM NOM NOM NOM NOM NOM NOM NOM
NOM NOM NOM NOM NOM NOM NOM
IT–
1%2%3%4%5%6%7%8%
9%10%11%12%13%14%15%
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
3
TPS3123J12, TPS3123G15, TPS3123J18, TPS3124J12, TPS3124G15 TPS3124J18, TPS3125J12, TPS3125G15, TPS3125J18, TPS3125L30 ULTRA-LOW VOLTAGE PROCESSOR SUPERVISORY CIRCUITS
SLVS227 – AUGUST 1999
functional block diagram
V
DD
R1
MR
GND
Reference
Voltage
WDI
TPS3123 and TPS3125 Only
TPS3123 and TPS3124 Only
§
TPS3124 and TPS3125 Only
Transition
Detector
timing diagram TPS3123 and TPS3125
V
DD V
IT
AB C DE F
R2
R3
Device Power Supply
Reset Logic
+ Timer
Watch Dog
Logic +
Timer
RESET
RESET
G
§
<0,85 V
MR
RESET
t
d
Output Undefined Output Undefined
t
d
t
d
t
t
t
4
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