TPS2834, TPS2835
SYNCHRONOUS-BUCK MOSFET DRIVERS
WITH DEADTIME CONTROL
SLVS223 – NOVEMBER 1999
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Floating Bootstrap or Ground-Reference
High-Side Driver
D
Active Deadtime Control
D
50-ns Max Rise/Fall Times With 3.3-nF Load
D
2-A Min Peak Output Current
D
4.5-V to 15-V Supply Voltage Range
D
TTL-Compatible Inputs
D
Internal Schottky Bootstrap Diode
D
SYNC Control for Synchronous or
Nonsynchronous Operation
D
CROWBAR for OVP, Protects Against
Faulted High-Side Power FETs
D
Low Supply Current ...3 mA Typ
D
Ideal for High-Current Single- or Multiphase
Applications
D
–40°C to 125°C Junction-Temperature
Operating Range
description
The TPS2834 and TPS2835 are MOSFET drivers for synchronous-buck power stages. These devices are ideal
for designing a high-performance power supply using a switching controller that does not include suitable
on-chip MOSFET drivers. The drivers are designed to deliver minimum 2-A peak currents into large capacitive
loads. The high-side driver can be configured as ground-reference or as floating-bootstrap. An adaptive
dead-time control circuit eliminates shoot-through currents through the main power FETs during switching
transitions, and provides high efficiency for the buck regulator. The TPS2834 and TPS2835 have additional
control functions: ENABLE, SYNC, and CROWBAR. Both high-side and low-side drivers are off when ENABLE
is low. The low-side driver is configured as a nonsynchronous-buck driver when SYNC is low . The CROWBAR
function turns on the low-side power FET, overriding the IN signal, for overvoltage protection against faulted
high-side power FETs.
The TPS2834 has a noninverting input, while the TPS2835 has an inverting input. These drivers are available
in 14-terminal SOIC and TSSOP packages and operate over a junction temperature range of –40°C to 125°C.
AVAILABLE OPTIONS
PACKAGED DEVICES
T
J
SOIC
(D)
TSSOP
(PWP)
–40°C to 125°C
TPS2834D
TPS2835D
TPS2834PWP
TPS2835PWP
The D and PWP packages are available taped and reeled. Add R
suffix to device type (e.g., TPS2834DR)
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
14
13
12
11
10
9
8
ENABLE
IN
CROWBAR
NC
SYNC
DT
PGND
BOOT
NC
HIGHDR
BOOTLO
LOWDR
NC
V
CC
D OR PWP PACKAGE
(TOP VIEW)
NC – No internal connection
TPS2834, TPS2835
SYNCHRONOUS-BUCK MOSFET DRIVERS
WITH DEADTIME CONTROL
SLVS223 – NOVEMBER 1999
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
DT
6
IN
V
CC
LOWDR
BOOTLO
HIGHDR
BOOT
PGND
2
8
14
12
11
10
V
CC
7
ENABLE
1
SYNC
5
CROWBAR
3
(TPS2834 Only)
(TPS2835 Only)
200 kΩ
200 kΩ
200 kΩ
Terminal Functions
TERMINAL
NAME NO.
I/O
DESCRIPTION
BOOT 14 I Bootstrap terminal. A ceramic capacitor is connected between BOOT and BOOTLO to develop the floating
bootstrap voltage for the high-side MOSFET. The capacitor value is typically between 0.1 µF and 1 µF.
BOOTLO 11 O This terminal connects to the junction of the high-side and low-side MOSFETs.
CROWBAR 3 I CROWBAR can to be driven by an external OVP circuit to protect against a short across the high-side
MOSFET. If CROWBAR is driven low, the low-side driver will be turned on and the high-side driver will be
turned off, independent of the status of all other control terminals.
DT 6 I Deadtime control terminal. Connect DT to the junction of the high-side and low-side MOSFETs.
ENABLE 1 I If ENABLE is low, both drivers are off.
HIGHDR 12 O Output drive for the high-side power MOSFET
IN 2 I Input signal to the MOSFET drivers (noninverting input for the TPS2834; inverting input for the TPS2835).
LOWDR 10 O Output drive for the low-side power MOSFET
NC 4, 9, 13
PGND 7 Power ground. Connect to the FET power ground
SYNC 5 I Synchronous rectifier enable terminal. If SYNC is low, the low-side driver is always off; If SYNC is high, the
low-side driver provides gate drive to the low-side MOSFET.
V
CC
8 I Input supply. Recommended that a 1-µF capacitor be connected from VCC to PGND.
TPS2834, TPS2835
SYNCHRONOUS-BUCK MOSFET DRIVERS
WITH DEADTIME CONTROL
SLVS223 – NOVEMBER 1999
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
detailed description
low-side driver
The low-side driver is designed to drive low r
DS(on)
N-channel MOSFET s. The current rating of the driver is 2 A,
source and sink.
high-side driver
The high-side driver is designed to drive low r
DS(on)
N-channel MOSFET s. The current rating of the driver is 2 A,
source and sink. The high-side driver can be configured as a GND-reference driver or as a floating bootstrap
driver. The internal bootstrap diode is a Schottky, for improved drive ef ficiency . The maximum voltage that can
be applied from BOOT to ground is 30 V.
dead-time (DT) control
Dead-time control prevents shoot-through current from flowing through the main power FETs during switching
transitions by controlling the turnon times of the MOSFET drivers. The high-side driver is not allowed to turn
on until the gate drive voltage to the low-side FET is low, and the low-side driver is not allowed to turn on until
the voltage at the junction of the power FETs (Vdrn) is low; the TTL-compatible DT terminal connects to the
junction of the power FETs.
ENABLE
The ENABLE terminal enables the drivers. When enable is low, the output drivers are low. ENABLE is a
TTL-compatible digital terminal.
IN
The IN terminal is a TTL-compatible digital terminal that is the input control signal for the drivers. The TPS2834
has a noninverting input; the TPS2835 has an inverting input.
SYNC
The SYNC terminal controls whether the drivers operate in synchronous or nonsynchronous mode. In
synchronous mode, the low-side FET is operated as a synchronous rectifier. In nonsynchronous mode, the
low-side FET is always off. SYNC is a TTL-compatible digital terminal.
CROWBAR
The CROWBAR terminal overrides the normal operation of the driver. When CROWBAR is low, the low-side
FET turns on to act as a clamp, protecting the output voltage of the dc/dc converter against overvoltages due
to a short across the high-side FET. VIN should be fused to protect the low-side FET. CROWBAR is a
TTL-compatible digital terminal.
TPS2834, TPS2835
SYNCHRONOUS-BUCK MOSFET DRIVERS
WITH DEADTIME CONTROL
SLVS223 – NOVEMBER 1999
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
†
Supply voltage range, V
CC
(see Note 1) –0.3 V to 16 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range:BOOT to PGND (high-side driver ON) –0.3 V to 30 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BOOTLO to PGND –0.3 V to 16 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BOOT to BOOTLO –0.3 V to 16 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ENABLE, SYNC, and CROWBAR (see Note 2) –0.3 V to 16 V. . . . . . . . . . . . . . . . . . . . .
IN –0.3 V to 16 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DT –0.3 V to 30 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature range, T
J
–40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Unless otherwise specified, all voltages are with respect to PGND.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
D 760 mW 7.6 mW/°C 420 mW 305 mW
PWP 2400 mW 25 mW/°C 1275 mW 900 mW
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, V
CC
4.5 15 V
Input voltage BOOT to PGND 4.5 28 V
electrical characteristics over recommended operating virtual junction temperature range,
V
CC
= 6.5 V, ENABLE = High, CL = 3.3 nF (unless otherwise noted)
supply current
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
CC
Supply voltage range 4.5 15 V
V
(ENABLE)
= LOW, VCC =15 V 100
V
(ENABLE)
= HIGH, VCC =15 V 300 400
µ
A
V
CC
Quiescent current
V
(ENABLE)
= HIGH,
f
(SWX)
= 200 kHz,
C
(HIGHDR)
= 50 pF,
See Note 2
VCC =12 V ,
BOOTLO grounded,
C
(LOWDR)
= 50 pF,
3 mA
NOTE 2: Ensured by design, not production tested.
TPS2834, TPS2835
SYNCHRONOUS-BUCK MOSFET DRIVERS
WITH DEADTIME CONTROL
SLVS223 – NOVEMBER 1999
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating virtual junction temperature range,
V
CC
= 6.5 V, ENABLE = High, CL = 3.3 nF (unless otherwise noted) (continued)
output drivers
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
(BOOT)
– V
(BOOTLO)
= 4.5 V,
V
(HIGHDR)
= 4 V
0.7 1.1
High-side sink
(see Note 3)
Duty cycle < 2%,
tpw < 100 µs
V
(BOOT)
– V
(BOOTLO)
= 6.5 V,
V
(HIGHDR)
= 5 V
1.1 1.5
A
(see Note 2)
V
(BOOT)
– V
(BOOTLO)
= 12 V,
V
(HIGHDR)
= 10.5 V
2 2.4
V
(BOOT)
– V
(BOOTLO)
= 4.5 V,
V
(HIGHDR)
= 0.5V
1.2 1.4
Peak output current
High-side source
(see Note 3)
Duty cycle < 2%,
tpw < 100 µs
V
(BOOT)
– V
(BOOTLO)
= 6.5 V,
V
(HIGHDR)
= 1.5 V
1.3 1.6
A
(see Note 2)
V
(BOOT)
– V
(BOOTLO)
= 12 V,
V
(HIGHDR)
= 1.5 V
2.3 2.7
VCC = 4.5 V, V
(LOWDR)
= 4 V 1.3 1.8
Low-side sink
Duty cycle < 2%
,
tpw < 100 µs
VCC = 6.5 V, V
(LOWDR)
= 5 V 2 2.5
A
(see Note 3)
(see Note 2)
VCC = 12 V, V
(LOWDR)
= 10.5 V 3 3.5
VCC = 4.5 V, V
LOWDR))
= 0.5V 1.4 1.7
Low-side source
Duty cycle < 2%
,
tpw < 100 µs
VCC = 6.5 V, V
(LOWDR))
= 1.5 V 2 2.4
A
(see Note 3)
(see Note 2)
VCC = 12 V, V
(LOWDR0)
= 1.5 V 2.5 3
V
(BOOT)
– V
(BOOTLO)
= 4.5 V,
V
(HIGHDR)
= 0.5 V
5
High-side sink (see Note 3)
V
(BOOT)
– V
(BOOTLO)
= 6.5 V,
V
(HIGHDR)
= 0.5 V
5
Ω
V
(BOOT)
– V
(BOOTLO)
= 12 V,
V
(HIGHDR)
= 0.5 V
5
V
(BOOT)
– V
(BOOTLO)
= 4.5 V,
V
(HIGHDR)
= 4 V
75
Output resistance
High-side source (see Note 3)
V
(BOOT)
– V
(BOOTLO)
= 6.5 V,
V
(HIGHDR)
= 6 V
75
Ω
V
(BOOT)
– V
(BOOTLO)
= 12 V,
V
(HIGHDR)
=11.5 V
75
V
(DRV)
= 4.5 V, V
(LOWDR)
= 0.5 V 9
Low-side sink (see Note 3)
V
(DRV)
= 6.5 V, V
(LOWDR)
= 0.5 V 7.5
Ω
V
(DRV)
= 12 V, V
(LOWDR)
= 0.5 V 6
V
(DRV)
= 4.5 V, V
(LOWDR)
= 4 V 75
Low-side source (see Note 3)
V
(DRV)
= 6.5 V, V
(LOWDR
)= 6 V 75
Ω
V
(DRV)
= 12 V, V
(LOWDR)
= 11.5 V 75
NOTES: 2: Ensured by design, not production tested.
3. The pullup/pulldown circuits of the drivers are bipolar and MOSFET transistors in parallel. The peak output current rating is the
combined current from the bipolar and MOSFET transistors. The output resistance is the r
DS(on)
of the MOSFET transistor when
the voltage on the driver output is less than the saturation voltage of the bipolar transistor.
TPS2834, TPS2835
SYNCHRONOUS-BUCK MOSFET DRIVERS
WITH DEADTIME CONTROL
SLVS223 – NOVEMBER 1999
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating virtual junction temperature range,
V
CC
= 6.5 V, ENABLE = High, CL = 3.3 nF (unless otherwise noted) (continued)
deadtime control
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
High-level input voltage, V
IH
0.7V
CC
LOWDR
Low-level input voltage, V
IL
Over the V
CC
range (see Note 2)
1
V
High-level input voltage, V
IH
0.7V
CC
V
DT
Low-level input voltage, V
IL
Over the V
CC
range
1 V
NOTE 2: Ensured by design, not production tested.
digital control terminals (IN, CROWBAR, SYNC, ENABLE)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
High-level input voltage, V
IH
2 V
Low-level input voltage, V
IL
Over the V
CC
range
1 V
switching characteristics over recommended operating virtual junction temperature range,
ENABLE = High, C
L
= 3.3 nF (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
(BOOT)
= 4.5 V, V
(BOOTLO)
= 0 V 60
HIGHDR output (see Note 2)
V
(BOOT)
= 6.5 V, V
(BOOTLO)
= 0 V 50
ns
V
(BOOT)
= 12 V, V
(BOOTLO)
= 0 V 50
Rise time
VCC = 4.5 V 40
LOWDR output (see Note 2)
VCC = 6.5 V 30
ns
VCC = 12 V 30
V
(BOOT)
= 4.5 V, V
(BOOTLO)
= 0 V 50
HIGHDR output (see Note 2)
V
(BOOT)
= 6.5 V, V
(BOOTLO)
= 0 V 40
ns
V
(BOOT)
= 12 V, V
(BOOTLO)
= 0 V 40
Fall time
VCC = 4.5 V 40
LOWDR output (see Note 2)
VCC = 6.5 V 30
ns
VCC = 12 V 30
V
(BOOT)
= 4.5 V, V
(BOOTLO)
= 0 V 95
HIGHDR going low (excluding
V
(BOOT)
= 6.5 V, V
(BOOTLO)
= 0 V 80
ns
p
deadtime) (see Note 2)
V
(BOOT)
= 12 V, V
(BOOTLO)
= 0 V 70
Propagation delay time
V
(BOOT)
= 4.5 V, V
(BOOTLO)
= 0 V 80
LOWDR going high (excluding
V
(BOOT)
= 6.5 V, V
(BOOTLO)
= 0 V 70
ns
deadtime) (see Note 2)
V
(BOOT)
= 12 V, V
(BOOTLO)
= 0 V 60
VCC = 4.5 V 80
Propagation delay time
LOWDR going low (excluding
VCC = 6.5 V 70
ns
deadtime) (see Note 2)
VCC = 12 V 60
VCC = 4.5 V 40 170
Driver nonoverlap time
DT to LOWDR and LOWDR to
VCC = 6.5 V 25 135
ns
HIGHDR (see Note 2)
VCC = 12 V 15 85
NOTE 2: Ensured by design, not production tested.
TPS2834, TPS2835
SYNCHRONOUS-BUCK MOSFET DRIVERS
WITH DEADTIME CONTROL
SLVS223 – NOVEMBER 1999
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 1
10
46 810
15
RISE TIME
vs
SUPPLY VOLTAGE
50
13
VCC – Supply Voltage – V
35
40
45
20
25
30
t
r
– Rise Time – ns
5791112
Low Side
High Side
CL = 3.3 nF
TJ = 25 °C
1514
Figure 2
FALL TIME
vs
SUPPLY VOLTAGE
t
f
– Fall Time – ns
10
46 810
15
50
13
VCC – Supply Voltage – V
35
40
45
20
25
30
5791112
Low Side
High Side
CL = 3.3 nF
TJ = 25 °C
1514
Figure 3
RISE TIME
vs
JUNCTION TEMPERATURE
t
r
– Rise Time – ns
TJ – Junction Temperature – °C
10
0 50 100
15
50
125
35
40
45
20
25
30
25 75–50 –25
VCC = 6.5 V
CL = 3.3 nF
Low Side
High Side
Figure 4
FALL TIME
vs
JUNCTION TEMPERATURE
t
f
– Fall Time – ns
TJ – Junction Temperature – °C
10
0 50 100
15
50
125
35
40
45
20
25
30
25 75
Low Side
High Side
VCC = 6.5 V
CL = 3.3 nF
–50 –25
TPS2834, TPS2835
SYNCHRONOUS-BUCK MOSFET DRIVERS
WITH DEADTIME CONTROL
SLVS223 – NOVEMBER 1999
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 5
20
46 810
30
LOW-TO-HIGH PROPAGATION DELAY TIME
vs
SUPPLY VOLTAGE, LOW TO HIGH LEVEL
150
13
VCC – Supply Voltage – V
70
80
90
40
50
60
5791112
120
130
140
100
110
Low Side
t
PLH
– Low-to-High Propagation Delay Time – ns
CL = 3.3 nF
TJ = 25 °C
1514
Figure 6
HIGH-TO-LOW PROPAGATION DELAY TIME
vs
SUPPLY VOLTAGE, HIGH TO LOW LEVEL
VCC – Supply Voltage – V
20
46 810
30
150
13
70
80
90
40
50
60
5791112
120
130
140
100
110
Low Side
High Side
t
PHL
– High-to-Low Propagation Delay Time – ns
CL = 3.3 nF
TJ = 25 °C
1514
Figure 7
LOW-TO-HIGH PROPAGATION DELAY TIME
vs
JUNCTION TEMPERATURE
TJ – Junction Temperature – °C
20
0 50 100
30
150
125
70
80
90
40
50
60
25 75
120
130
140
100
110
t
PLH
– Low-to-High Propagation Delay Time – ns
–25–50
VCC = 6.5 V
CL = 3.3 nF
High Side
Low Side
Figure 8
HIGH-TO-LOW PROPAGATION DELAY TIME
vs
JUNCTION TEMPERATURE
TJ – Junction Temperature – °C
20
0 50 100
30
150
125
70
80
90
40
50
60
25 75
120
130
140
100
110
t
PHL
– High-to-Low Propagation Delay Time – ns
Low Side
High Side
VCC = 6.5 V
CL = 3.3 nF
–25–50
TPS2834, TPS2835
SYNCHRONOUS-BUCK MOSFET DRIVERS
WITH DEADTIME CONTROL
SLVS223 – NOVEMBER 1999
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 9
DRIVER-OUTPUT RISE TIME
vs
LOAD CAPACITANCE
CL – Load Capacitance – nF
t
r
– Rise Time – ns
100
10
1
1000
0.01 1 10 100
VCC = 6.5 V
TJ = 25 °C
Low Side
High Side
0.1
Figure 10
DRIVER-OUTPUT FALL TIME
vs
LOAD CAPACITANCE
CL – Load Capacitance – nF
t
f
– Fall Time – ns
100
10
1
1000
0.01 1 10 100
VCC = 6.5 V
TJ = 25 °C
Low Side
High Side
0.1
Figure 11
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
VCC – Supply Voltage – V
0
46 810
500
5000
14
3500
4000
4500
1000
1500
2500
12
CC
I Supply Current – –Aµ
2000
3000
300 kHz
200 kHz
100 kHz
50 kHz
25 kHz
16
6000
5500
500 kHz
TJ = 25 °C
CL = 50 pF
Figure 12
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
VCC – Supply Voltage – V
0
46 810 14
10
12
CC
I Supply Current – mA–
5
16
15
20
25
1 MHz
TJ = 25 °C
CL = 50 pF
2 MHz
TPS2834, TPS2835
SYNCHRONOUS-BUCK MOSFET DRIVERS
WITH DEADTIME CONTROL
SLVS223 – NOVEMBER 1999
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 13
PEAK SOURCE CURRENT
vs
DRIVE VOLTAGE
Peak Source Current – A
VCC – Supply Voltage – V
0
46 810
0.5
4
14
2.5
3
3.5
1
1.5
2
12
Low Side
High Side
TJ = 25 °C
16
Figure 14
PEAK SINK CURRENT
vs
DRIVE VOLTAGE
Peak Sink Current – A
VCC – Supply Voltage – V
0
46 810
0.5
4
14
2.5
3
3.5
1
1.5
2
12
Low Side
High Side
TJ = 25 °C
16
1.00
1.20
1.40
1.60
1.80
2.00
4.00 6.00 8.00 10.00 12.00 14.00 16.00
Figure 15
INPUT THRESHOLD VOLTAGE
vs
SUPPLY VOLTAGE
VCC – Supply Voltage – V
V
IT
– Input Threshold Voltage – V
TJ = 25 °C
Figure 16
1.00
1.20
1.40
1.60
1.80
2.00
–50.00 –25.00 0.00 25.00 50.00 75.00 100.00 125.00
INPUT THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
TJ – Junction Temperature – °C
V
IT
– Input Threshold Voltage – V
VCC = 6.5 V
TPS2834, TPS2835
SYNCHRONOUS-BUCK MOSFET DRIVERS
WITH DEADTIME CONTROL
SLVS223 – NOVEMBER 1999
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Figure 17 shows the circuit schematic of a 100-kHz synchronous-buck converter implemented with a TL5001A
pulse-width-modulation (PWM) controller and a TPS2835 driver. The converter operates over an input range from
4.5 V to 12 V and has a 3.3-V output. The circuit can supply 3 A continuous load. The converter achieves an efficiency
of 94% for V
IN
= 5 V, I
load
=1 A, and 93% for V
IN
= 5 V, I
load
= 3 A.
C14
1 µF
R9
90.9 kΩ
R8
121 kΩ
C9
0.22 µF
V
CC
RT
FB
COMP
GND
OUT
DTC
SCP
U2
TL5001A
1
2
6
5
8
3
4
7
C1
1 µF
R10
1.0 kΩ
R2
1.6 kΩ
C2
0.033 µF
C3
0.0022 µF
C8
0.1 µF
C4
0.022 µFR3180 Ω
R4
2.32 kΩ
GND
Q2
Si4410
R7
3.3 Ω
C6
1000 pF
V
IN
C5
100 µF
C10
100 µF
C11
0.47 µF
3.3 V
C13
10 µF
C7
100 µF
C12
100 µF
Q1
Si4410
L1
27 µH
IN
BOOTLO
HIGHDR
NC
BOOT
ENABLE
CROWBAR
NC
U1
TPS2835
1
2
3
4
14
13
12
11
SYNC
DT
PGND
5
6
7
V
CC
NC
LOWDR
10
9
8
R1
1 kΩ
C15
1.0 µF
R6
1 MΩ
R5
0 Ω
R11
4.7 Ω
RTN
+
+
+
+
Figure 17. 3.3-V 3-A Synchronous-Buck Converter Circuit
TPS2834, TPS2835
SYNCHRONOUS-BUCK MOSFET DRIVERS
WITH DEADTIME CONTROL
SLVS223 – NOVEMBER 1999
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Great care should be taken when laying out the pc board. The power-processing section is the most critical and
will generate large amounts of EMI if not properly configured. The junction of Q1, Q2, and L1 should be very
tight. The connection from Q1 drain to the positive sides of C5, C10, and C1 1 and the connection from Q2 source
to the negative sides of C5, C10, and C11 should be as short as possible. The negative terminals of C7 and
C12 should also be connected to Q2 source.
Next, the traces from the MOSFET driver to the power switches should be considered. The BOOTLO signal from
the junction of Q1 and Q2 carries the large gate drive current pulses and should be as heavy as the gate drive
traces. The bypass capacitor (C14) should be tied directly across V
CC
and PGND.
The next most sensitive node is the FB node on the controller (terminal 4 on the TL5001A). This node is very
sensitive to noise pick-up and should be isolated from the high-current power stage and be as short as possible.
The ground around the controller and low-level circuitry should be tied to the power ground as the output. If these
three areas are properly laid out, the rest of the circuit should not have other EMI problems and the power supply
will be relatively free of noise.
TPS2834, TPS2835
SYNCHRONOUS-BUCK MOSFET DRIVERS
WITH DEADTIME CONTROL
SLVS223 – NOVEMBER 1999
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
4040047/D 10/96
0.228 (5,80)
0.244 (6,20)
0.069 (1,75) MAX
0.010 (0,25)
0.004 (0,10)
1
14
0.014 (0,35)
0.020 (0,51)
A
0.157 (4,00)
0.150 (3,81)
7
8
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.010 (0,25)
PINS **
0.008 (0,20) NOM
A MIN
A MAX
DIM
Gage Plane
0.189
(4,80)
(5,00)
0.197
8
(8,55)
(8,75)
0.337
14
0.344
(9,80)
16
0.394
(10,00)
0.386
0.004 (0,10)
M
0.010 (0,25)
0.050 (1,27)
0°–8°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
TPS2834, TPS2835
SYNCHRONOUS-BUCK MOSFET DRIVERS
WITH DEADTIME CONTROL
SLVS223 – NOVEMBER 1999
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
PWP (R-PDSO-G**) PowerPAD PLASTIC SMALL-OUTLINE PACKAGE
4073225/E 03/97
0,50
0,75
0,25
0,15 NOM
Thermal Pad
(See Note D)
Gage Plane
2824
7,70
7,90
20
6,40
6,60
9,60
9,80
6,60
6,20
11
0,19
4,50
4,30
10
0,15
20
A
1
0,30
1,20 MAX
1614
5,10
4,90
PINS **
4,90
5,10
DIM
A MIN
A MAX
0,05
Seating Plane
0,65
0,10
M
0,10
0°–8°
20-PIN SHOWN
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusions.
D. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This pad is electrically
and thermally connected to the backside of the die and possibly selected leads.
E. Falls within JEDEC MO-153
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