Floating Bootstrap or Ground-Reference
High-Side Driver
D
Active Deadtime Control
D
50-ns Max Rise/Fall Times With 3.3-nF Load
D
2-A Min Peak Output Current
D
4.5-V to 15-V Supply Voltage Range
D
TTL-Compatible Inputs
D
Internal Schottky Bootstrap Diode
D
SYNC Control for Synchronous or
Nonsynchronous Operation
D
CROWBAR for OVP, Protects Against
ENABLE
CROWBAR
SYNC
PGND
NC – No internal connection
D OR PWP PACKAGE
1
IN
NC
DT
2
3
4
5
6
7
(TOP VIEW)
14
13
12
11
10
9
8
BOOT
NC
HIGHDR
BOOTLO
LOWDR
NC
V
CC
Faulted High-Side Power FETs
D
Low Supply Current ...3 mA Typ
D
Ideal for High-Current Single- or Multiphase
Applications
D
–40°C to 125°C Junction-Temperature
Operating Range
description
The TPS2834 and TPS2835 are MOSFET drivers for synchronous-buck power stages. These devices are ideal
for designing a high-performance power supply using a switching controller that does not include suitable
on-chip MOSFET drivers. The drivers are designed to deliver minimum 2-A peak currents into large capacitive
loads. The high-side driver can be configured as ground-reference or as floating-bootstrap. An adaptive
dead-time control circuit eliminates shoot-through currents through the main power FETs during switching
transitions, and provides high efficiency for the buck regulator. The TPS2834 and TPS2835 have additional
control functions: ENABLE, SYNC, and CROWBAR. Both high-side and low-side drivers are off when ENABLE
is low. The low-side driver is configured as a nonsynchronous-buck driver when SYNC is low . The CROWBAR
function turns on the low-side power FET, overriding the IN signal, for overvoltage protection against faulted
high-side power FETs.
The TPS2834 has a noninverting input, while the TPS2835 has an inverting input. These drivers are available
in 14-terminal SOIC and TSSOP packages and operate over a junction temperature range of –40°C to 125°C.
AVAILABLE OPTIONS
PACKAGED DEVICES
–40°C to 125°C
The D and PWP packages are available taped and reeled. Add R
suffix to device type (e.g., TPS2834DR)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
T
J
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SOIC
(D)
TPS2834D
TPS2835D
TSSOP
(PWP)
TPS2834PWP
TPS2835PWP
Copyright 1999, Texas Instruments Incorporated
1
TPS2834, TPS2835
I/O
DESCRIPTION
SYNCHRONOUS-BUCK MOSFET DRIVERS
WITH DEADTIME CONTROL
SLVS223 – NOVEMBER 1999
functional block diagram
(TPS2834 Only)
2
IN
(TPS2835 Only)
6
DT
200 kΩ
200 kΩ
8
14
12
11
V
CC
BOOT
HIGHDR
BOOTLO
V
CC
10
200 kΩ
7
LOWDR
PGND
ENABLE
1
SYNC
CROWBAR
5
3
Terminal Functions
TERMINAL
NAMENO.
BOOT14IBootstrap terminal. A ceramic capacitor is connected between BOOT and BOOTLO to develop the floating
BOOTLO11OThis terminal connects to the junction of the high-side and low-side MOSFETs.
CROWBAR3ICROWBAR can to be driven by an external OVP circuit to protect against a short across the high-side
DT6IDeadtime control terminal. Connect DT to the junction of the high-side and low-side MOSFETs.
ENABLE1IIf ENABLE is low, both drivers are off.
HIGHDR12OOutput drive for the high-side power MOSFET
IN2IInput signal to the MOSFET drivers (noninverting input for the TPS2834; inverting input for the TPS2835).
LOWDR10OOutput drive for the low-side power MOSFET
NC4, 9, 13
PGND7Power ground. Connect to the FET power ground
SYNC5ISynchronous rectifier enable terminal. If SYNC is low, the low-side driver is always off; If SYNC is high, the
V
CC
8IInput supply. Recommended that a 1-µF capacitor be connected from VCC to PGND.
bootstrap voltage for the high-side MOSFET. The capacitor value is typically between 0.1 µF and 1 µF.
MOSFET. If CROWBAR is driven low, the low-side driver will be turned on and the high-side driver will be
turned off, independent of the status of all other control terminals.
low-side driver provides gate drive to the low-side MOSFET.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
detailed description
low-side driver
TPS2834, TPS2835
SYNCHRONOUS-BUCK MOSFET DRIVERS
WITH DEADTIME CONTROL
SLVS223 – NOVEMBER 1999
The low-side driver is designed to drive low r
source and sink.
high-side driver
The high-side driver is designed to drive low r
source and sink. The high-side driver can be configured as a GND-reference driver or as a floating bootstrap
driver. The internal bootstrap diode is a Schottky, for improved drive ef ficiency. The maximum voltage that can
be applied from BOOT to ground is 30 V.
dead-time (DT) control
Dead-time control prevents shoot-through current from flowing through the main power FETs during switching
transitions by controlling the turnon times of the MOSFET drivers. The high-side driver is not allowed to turn
on until the gate drive voltage to the low-side FET is low, and the low-side driver is not allowed to turn on until
the voltage at the junction of the power FETs (Vdrn) is low; the TTL-compatible DT terminal connects to the
junction of the power FETs.
ENABLE
The ENABLE terminal enables the drivers. When enable is low, the output drivers are low. ENABLE is a
TTL-compatible digital terminal.
IN
The IN terminal is a TTL-compatible digital terminal that is the input control signal for the drivers. The TPS2834
has a noninverting input; the TPS2835 has an inverting input.
SYNC
N-channel MOSFET s. The current rating of the driver is 2 A,
DS(on)
N-channel MOSFET s. The current rating of the driver is 2 A,
DS(on)
The SYNC terminal controls whether the drivers operate in synchronous or nonsynchronous mode. In
synchronous mode, the low-side FET is operated as a synchronous rectifier. In nonsynchronous mode, the
low-side FET is always off. SYNC is a TTL-compatible digital terminal.
CROWBAR
The CROWBAR terminal overrides the normal operation of the driver. When CROWBAR is low, the low-side
FET turns on to act as a clamp, protecting the output voltage of the dc/dc converter against overvoltages due
to a short across the high-side FET. VIN should be fused to protect the low-side FET. CROWBAR is a
TTL-compatible digital terminal.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
TPS2834, TPS2835
A
SYNCHRONOUS-BUCK MOSFET DRIVERS
WITH DEADTIME CONTROL
SLVS223 – NOVEMBER 1999
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Unless otherwise specified, all voltages are with respect to PGND.
DISSIPATION RATING TABLE
PACKAGE
D760 mW7.6 mW/°C420 mW305 mW
PWP2400 mW25 mW/°C1275 mW900 mW
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
recommended operating conditions
MINNOMMAXUNIT
Supply voltage, V
Input voltageBOOT to PGND4.528V
CC
4.515V
electrical characteristics over recommended operating virtual junction temperature range,
NOTES: 2: Ensured by design, not production tested.
3. The pullup/pulldown circuits of the drivers are bipolar and MOSFET transistors in parallel. The peak output current rating is the
combined current from the bipolar and MOSFET transistors. The output resistance is the r
the voltage on the driver output is less than the saturation voltage of the bipolar transistor.
High-side source
(see Note 3)
Low-side sink
Low-side source
High-side sink (see Note 3)
High-side source (see Note 3)
Low-side sink (see Note 3)
Low-side source (see Note 3)
Duty cycle < 2%,
tpw < 100 µs
Duty cycle < 2%,
tpw < 100 µs
tpw < 100 µs
(see Note 2)
tpw < 100 µs
(see Note 2)
V
V
V
V
V
V
V
V
V
V
V
V
VCC = 4.5 V, V
,
VCC = 6.5 V, V
VCC = 12 V, V
VCC = 4.5 V, V
,
VCC = 6.5 V, V
VCC = 12 V, V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
– V
(BOOT)
(HIGHDR)
– V
(BOOT)
(HIGHDR)
– V
(BOOT)
(HIGHDR)
– V
(BOOT)
(HIGHDR)
– V
(BOOT)
(HIGHDR)
– V
(BOOT)
(HIGHDR)
– V
(BOOT)
(HIGHDR)
– V
(BOOT)
(HIGHDR)
– V
(BOOT)
(HIGHDR)
– V
(BOOT)
(HIGHDR)
– V
(BOOT)
(HIGHDR)
– V
(BOOT)
(HIGHDR)
= 4.5 V, V
(DRV)
= 6.5 V, V
(DRV)
= 12 V, V
(DRV)
= 4.5 V, V
(DRV)
= 6.5 V, V
(DRV)
= 12 V, V
(DRV)
(BOOTLO)
= 4 V
(BOOTLO)
= 5 V
(BOOTLO)
= 10.5 V
(BOOTLO)
= 0.5V
(BOOTLO)
= 1.5 V
(BOOTLO)
= 1.5 V
(LOWDR)
(LOWDR)
(LOWDR)
LOWDR))
(LOWDR))
(LOWDR0)
(BOOTLO)
= 0.5 V
(BOOTLO)
= 0.5 V
(BOOTLO)
= 0.5 V
(BOOTLO)
= 4 V
(BOOTLO)
= 6 V
(BOOTLO)
=11.5 V
(LOWDR)
(LOWDR)
(LOWDR)
(LOWDR)
(LOWDR
(LOWDR)
= 4.5 V,
= 6.5 V,
= 12 V,
= 4.5 V,
= 6.5 V,
= 12 V,
= 4 V1.31.8
= 5 V22.5
= 10.5 V33.5
= 0.5V1.41.7
= 1.5 V22.4
= 1.5 V2.53
= 4.5 V,
= 6.5 V,
= 12 V,
= 4.5 V,
= 6.5 V,
= 12 V,
= 0.5 V9
= 0.5 V7.5
= 0.5 V6
= 4 V75
)= 6 V75
= 11.5 V75
0.71.1
1.11.5
22.4
1.21.4
1.31.6
2.32.7
of the MOSFET transistor when
DS(on)
5
5
5
75
75
75
A
A
A
A
Ω
Ω
Ω
Ω
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
TPS2834, TPS2835
LOWDR
Over the V
range (see Note 2)
V
DT
Over the V
range
Over the V
range
Rise time
Fall time
deadtime) (see Note 2)
Propagation delay time
deadtime) (see Note 2)
deadtime) (see Note 2)
HIGHDR (see Note 2)
SYNCHRONOUS-BUCK MOSFET DRIVERS
WITH DEADTIME CONTROL
SLVS223 – NOVEMBER 1999
electrical characteristics over recommended operating virtual junction temperature range,
High-level input voltage, V
Low-level input voltage, V
High-level input voltage, V
Low-level input voltage, V
NOTE 2: Ensured by design, not production tested.
IH
IL
IH
IL
CC
CC
digital control terminals (IN, CROWBAR, SYNC, ENABLE)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
High-level input voltage, V
Low-level input voltage, V
IH
IL
CC
switching characteristics over recommended operating virtual junction temperature range,
ENABLE = High, C
p
Propagation delay time
Driver nonoverlap time
NOTE 2: Ensured by design, not production tested.
= 3.3 nF (unless otherwise noted)
L
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
HIGHDR output (see Note 2)
LOWDR output (see Note 2)
HIGHDR output (see Note 2)
LOWDR output (see Note 2)
HIGHDR going low (excluding
LOWDR going high (excluding
LOWDR going low (excluding
DT to LOWDR and LOWDR to
V
V
V
VCC = 4.5 V40
VCC = 6.5 V30
VCC = 12 V30
V
V
V
VCC = 4.5 V40
VCC = 6.5 V30
VCC = 12 V30
V
V
V
V
V
V
VCC = 4.5 V80
VCC = 6.5 V70
VCC = 12 V60
VCC = 4.5 V40170
VCC = 6.5 V25135
VCC = 12 V1585
(BOOT)
(BOOT)
(BOOT)
(BOOT)
(BOOT)
(BOOT)
(BOOT)
(BOOT)
(BOOT)
(BOOT)
(BOOT)
(BOOT)
= 4.5 V, V
= 6.5 V, V
= 12 V,V
= 4.5 V, V
= 6.5 V, V
= 12 V,V
= 4.5 V, V
= 6.5 V, V
= 12 V,V
= 4.5 V, V
= 6.5 V, V
= 12 V,V
Figure 17 shows the circuit schematic of a 100-kHz synchronous-buck converter implemented with a TL5001A
pulse-width-modulation (PWM) controller and a TPS2835 driver. The converter operates over an input range from
4.5 V to 12 V and has a 3.3-V output. The circuit can supply 3 A continuous load. The converter achieves an efficiency
of 94% for V
V
IN
IN
= 5 V, I
=1 A, and 93% for V
load
= 5 V, I
IN
load
= 3 A.
+
C10
100 µF
C5
100 µF
+
R1
1 kΩ
GND
C9
0.22 µF
1
ENABLE
2
IN
3
CROWBAR
4
NC
5
SYNC
6
DT
7
PGND
R8
121 kΩ
U1
TPS2835
BOOTLO
C14
1 µF
C1
1 µF
BOOT
NC
HIGHDR
LOWDR
NC
V
CC
C8
0.1 µF
1
OUT
6
DTC
5
SCP
V
CC
GND
14
13
12
11
10
9
8
2
COMP
8
U2
TL5001A
3
4
FB
7
RT
R9
90.9 kΩ
C15
1.0 µF
C2
0.033 µF
R6
1 MΩ
C3
0.0022 µF
R2
1.6 kΩ
R10
1.0 kΩ
R5
0 Ω
Q1
Si4410
R11
4.7 Ω
Q2
Si4410
C4
0.022 µFR3180 Ω
R4
2.32 kΩ
C11
0.47 µF
R7
3.3 Ω
C6
1000 pF
L1
27 µH
100 µF
C12
C7
100 µF
+
C13
10 µF
+
3.3 V
RTN
Figure 17. 3.3-V 3-A Synchronous-Buck Converter Circuit
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
11
TPS2834, TPS2835
SYNCHRONOUS-BUCK MOSFET DRIVERS
WITH DEADTIME CONTROL
SLVS223 – NOVEMBER 1999
APPLICATION INFORMATION
Great care should be taken when laying out the pc board. The power-processing section is the most critical and
will generate large amounts of EMI if not properly configured. The junction of Q1, Q2, and L1 should be very
tight. The connection from Q1 drain to the positive sides of C5, C10, and C1 1 and the connection from Q2 source
to the negative sides of C5, C10, and C11 should be as short as possible. The negative terminals of C7 and
C12 should also be connected to Q2 source.
Next, the traces from the MOSFET driver to the power switches should be considered. The BOOTLO signal from
the junction of Q1 and Q2 carries the large gate drive current pulses and should be as heavy as the gate drive
traces. The bypass capacitor (C14) should be tied directly across V
The next most sensitive node is the FB node on the controller (terminal 4 on the TL5001A). This node is very
sensitive to noise pick-up and should be isolated from the high-current power stage and be as short as possible.
The ground around the controller and low-level circuitry should be tied to the power ground as the output. If these
three areas are properly laid out, the rest of the circuit should not have other EMI problems and the power supply
will be relatively free of noise.
and PGND.
CC
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2834, TPS2835
SYNCHRONOUS-BUCK MOSFET DRIVERS
WITH DEADTIME CONTROL
SLVS223 – NOVEMBER 1999
MECHANICAL DATA
D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0.050 (1,27)
14
1
0.069 (1,75) MAX
A
0.020 (0,51)
0.014 (0,35)
0.010 (0,25)
0.004 (0,10)
DIM
8
7
PINS **
0.010 (0,25)
0.157 (4,00)
0.150 (3,81)
M
0.244 (6,20)
0.228 (5,80)
Seating Plane
0.004 (0,10)
8
14
0.008 (0,20) NOM
0°–8°
16
Gage Plane
0.010 (0,25)
0.044 (1,12)
0.016 (0,40)
A MAX
A MIN
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
0.197
(5,00)
0.189
(4,80)
0.344
(8,75)
0.337
(8,55)
0.394
(10,00)
0.386
(9,80)
4040047/D 10/96
13
TPS2834, TPS2835
SYNCHRONOUS-BUCK MOSFET DRIVERS
WITH DEADTIME CONTROL
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusions.
D. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This pad is electrically
and thermally connected to the backside of the die and possibly selected leads.
E. Falls within JEDEC MO-153
PowerPAD is a trademark of Texas Instruments Incorporated.
5,10
4,90
5,10
4,90
6,60
6,40
7,90
7,70
9,80
9,60
4073225/E 03/97
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
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