TPS2832, TPS2833
FAST SYNCHRONOUS-BUCK MOSFET DRIVER
WITH DEADTIME CONTROL
SLVS195B – JANUARY 1999 – REVISED SEPTEMBER 1999
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Floating Bootstrap or Ground-Reference
High-Side Driver
D
Active Deadtime Control
D
50-ns Max Rise/Fall Times and 100-ns Max
Propagation Delay — 3-nF Load
D
Ideal for High-Current Single or Mutiphase
Applications
D
2.4-A Typ Peak Output Current
D
4.5-V to 15-V Supply Voltage Range
D
Internal Schottky Bootstrap Diode
D
Low Supply Current . . . 3–mA T yp
D
–40°C to 125°C Junction-Temperature
Operating Range
description
The TPS2832 and TPS2833 are MOSFET drivers for synchronous-buck power stages. These devices are ideal
for designing a high-performance power supply using a switching controller that does not include suitable
MOSFET drivers on the chip. The drivers are designed to deliver 2.4-A peak currents into large capacitive loads.
Higher currents can be controlled by using multiple drivers in a multiphase configuration. The high-side driver
can be configured as a ground-reference driver or as a floating bootstrap driver. An adaptive dead-time control
circuit eliminates shoot-through currents through the main power FET s during switching transitions and provides
high efficiency for the buck regulator.
The TPS2832 has a noninverting input. The TPS2833 has an inverting input. The TPS2832/33 drivers, available
in 8-terminal SOIC packages, operate over a junction temperature range of –40°C to 125°C.
AVAILABLE OPTIONS
PACKAGED DEVICES
T
J
SOIC
(D)
–40°C to 125°C
TPS2832D
TPS2833D
The D package is available taped and reeled. Add R
suffix to device type (e.g., TPS2830DR)
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
D PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
IN
PGND
DT
V
CC
BOOT
HIGHDR
BOOTLO
LOWDR
TPS2832, TPS2833
FAST SYNCHRONOUS-BUCK MOSFET DRIVER
WITH DEADTIME CONTROL
SLVS195B – JANUARY 1999 – REVISED SEPTEMBER 1999
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
DT
3
IN
V
CC
LOWDR
BOOTLO
HIGHDR
BOOT
PGND
1
4
8
7
6
5
V
CC
2
(TPS2832 Only)
(TPS2833 Only)
Terminal Functions
TERMINAL
NAME NO.
I/O
DESCRIPTION
BOOT 8 I Bootstrap terminal. A ceramic capacitor is connected between BOOT and BOOTLO terminals to develop
the floating bootstrap voltage for the high-side MOSFET. The capacitor value is typically between 0.1 µF
and 1 µF . A 1-MΩ resistor should be connected across the bootstrap capacitor to provide a discharge path
when the driver has been powered down.
BOOTLO 6 O This terminal connects to the junction of the high-side and low-side MOSFETs.
DT 3 I Deadtime control terminal. Connect DT to the junction of the high-side and low-side MOSFETs
HIGHDR 7 O Output drive for the high-side power MOSFET
IN 1 I Input signal to the MOSFET drivers (noninverting input for the TPS2832; inverting input for the TPS2833).
LOWDR 5 O Output drive for the low-side power MOSFET
PGND 2 Power ground. Connect to the FET power ground.
V
CC
4 I Input supply. Recommended that a 1 µF capacitor be connected from VCC to PGND.
TPS2832, TPS2833
FAST SYNCHRONOUS-BUCK MOSFET DRIVER
WITH DEADTIME CONTROL
SLVS195B – JANUARY 1999 – REVISED SEPTEMBER 1999
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
detailed description
low-side driver
The low-side driver is designed to drive low Rds(on) N-channel MOSFETs. The current rating of the driver is
2 A, source and sink.
high-side driver
The high-side driver is designed to drive low Rds(on) N-channel MOSFETs. The current rating of the driver is
2 A, source and sink. The high-side driver can be configured as a ground-reference driver or a floating bootstrap
driver. The internal bootstrap diode, is a Schottky for improved drive ef ficiency . The maximum voltage that can
be applied between the BOOT terminal and ground is 30 V.
deadtime (DT) control
†
Deadtime control prevents shoot through current from flowing through the main power FETs during switching
transitions by controlling the turn-on times of the MOSFET drivers. The high-side driver is not allowed to turn
on until the gate drive voltage to the low-side FET is low, and the low-side driver is not allowed to turn on until
the voltage at the junction of the power FET s (Vdrn) is low; the DT terminal connects to the junction of the power
FET s.
IN
†
The IN terminal is a digital terminal that is the input control signal for the drivers. The TPS2832 has a noninverting
input; the TPS2833 has an inverting input.
†
High-level input voltages on IN and DT must be greater than or equal to VCC.
TPS2832, TPS2833
FAST SYNCHRONOUS-BUCK MOSFET DRIVER
WITH DEADTIME CONTROL
SLVS195B – JANUARY 1999 – REVISED SEPTEMBER 1999
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
†
Supply voltage range, V
CC
(see Note 1) –0.3 V to 16 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range:BOOT to PGND (high-side driver ON) –0.3 V to 30 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BOOTLO to PGND –0.3 V to 16 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BOOT to BOOTLO –0.3 V to 16 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IN (see Note 2) –0.3 V to 16 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DT (see Note 2) –0.3 V to 30 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature range, T
J
–40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Unless otherwise specified, all voltages are with respect to PGND.
2. High-level input voltages on the IN and DT terminals must be greater than or equal to VCC.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
D 580 mW 5.8 mW/°C 320 mW 232 mW
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, V
CC
4.5 15 V
Input voltage BOOT to PGND 4.5 28 V
electrical characteristics over recommended operating virtual junction temperature range,
V
CC
= 6.5 V, CL = 3.3 nF (unless otherwise noted)
supply current
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
CC
Supply voltage range 4.5 15 V
VCC =15 V 100 µA
V
CC
Quiescent current
VCC =12 V ,
f
SWX
= 200 kHz,
C
HIGHDR
= 50 pF,
BOOTLO grounded,
C
LOWDR
= 50 pF,
See Note 3
3 mA
NOTE 3: Ensured by design, not production tested.
TPS2832, TPS2833
FAST SYNCHRONOUS-BUCK MOSFET DRIVER
WITH DEADTIME CONTROL
SLVS195B – JANUARY 1999 – REVISED SEPTEMBER 1999
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating virtual junction temperature range,
V
CC
= 6.5 V, CL = 3.3 nF (unless otherwise noted) (continued)
output drivers
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
BOOT
– V
BOOTLO
= 4.5 V, V
HIGHDR
= 4 V 0.7 1.1
High-side sink
Duty cycle < 2%
,
tpw < 100 µs
V
BOOT
– V
BOOTLO
= 6.5 V, V
HIGHDR
= 5 V 1.1 1.5
A
(see Note 4)
(see Note 3)
V
BOOT
– V
BOOTLO
= 12 V, V
HIGHDR
= 10.5 V 2 2.4
-
V
BOOT
– V
BOOTLO
= 4.5 V, V
HIGHDR
= 0.5V 1.2 1.4
High side
source
Duty cycle < 2%
,
tpw < 100 µs
V
BOOT
– V
BOOTLO
= 6.5 V, V
HIGHDR
= 1.5 V 1.3 1.6
A
Peak output-
(see Note 4) (see Note 3)
V
BOOT
– V
BOOTLO
= 12 V, V
HIGHDR
= 1.5 V 2.3 2.7
current
VCC = 4.5 V, V
LOWDR
= 4 V 1.3 1.8
Low-side sink
Duty cycle < 2%
,
tpw < 100 µs
VCC = 6.5 V, V
LOWDR
= 5 V 2 2.5
A
(see Note 4)
(see Note 3)
VCC = 12 V, V
LOWDR
= 10.5 V 3 3.5
-
VCC = 4.5 V, V
LOWDR
= 0.5V 1.4 1.7
Low side
source
Duty cycle < 2%
,
tpw < 100 µs
VCC = 6.5 V, V
LOWDR
= 1.5 V 2 2.4
A
(see Note 4) (see Note 3)
VCC = 12 V, V
LOWDR
= 1.5 V 2.5 3
V
BOOT
– V
BOOTLO
= 4.5 V, V
HIGHDR
= 0.5 V 5
High-side sink (see Note 4)
V
BOOT
– V
BOOTLO
= 6.5 V, V
HIGHDR
= 0.5 V 5
Ω
V
BOOT
– V
BOOTLO
= 12 V, V
HIGHDR
= 0.5 V 5
V
BOOT
– V
BOOTLO
= 4.5 V, V
HIGHDR
= 4 V 45
High-side source (see Note 4)
V
BOOT
– V
BOOTLO
= 6.5 V, V
HIGHDR
= 6 V 45
Ω
Output
V
BOOT
– V
BOOTLO
= 12 V, V
HIGHDR
=11.5 V 45
resistance
V
DRV
= 4.5 V, V
LOWDR
= 0.5 V 9
Low-side sink (see Note 4)
V
DRV
= 6.5 V V
LOWDR
= 0.5 V 7.5
Ω
V
DRV
= 12 V, V
LOWDR
= 0.5 V 6
V
DRV
= 4.5 V, V
LOWDR
= 4 V 45
Low-side source (see Note 4)
V
DRV
= 6.5 V, V
LOWDR
= 6 V 45
Ω
V
DRV
= 12 V, V
LOWDR
= 11.5 V 45
NOTES: 3. Ensured by design, not production tested.
4. The pull-up/pull-down circuits of the drivers are bipolar and MOSFET transistors in parallel. The peak output current rating is the
combined current from the bipolar and MOSFET transistors. The output resistance is the Rds(on) of the MOSFET transistor when
the voltage on the driver output is less than the saturation voltage of the bipolar transistor.
deadtime
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
High-level input voltage
2 V
LOWDR
Low-level input voltage
Over the V
CC
range (see Note 3)
1 V
High-level input voltage
2 V
DT
Low-level input voltage
Over the V
CC
range
1 V
NOTE 3: Ensured by design, not production tested.
digital control terminals
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
High-level input voltage
2 V
Low-level input voltage
Over the V
CC
range
1 V
TPS2832, TPS2833
FAST SYNCHRONOUS-BUCK MOSFET DRIVER
WITH DEADTIME CONTROL
SLVS195B – JANUARY 1999 – REVISED SEPTEMBER 1999
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating virtual junction temperature range,
C
L
= 3.3 nF (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
BOOT
= 4.5 V, V
BOOTLO
= 0 V 60
HIGHDR output
V
BOOT
= 6.5 V, V
BOOTLO
= 0 V 50
ns
(see Note 3)
V
BOOT
= 12 V, V
BOOTLO
= 0 V 50
Rise time
VCC = 4.5 V 40
LOWDR output
VCC = 6.5 V 30
ns
(see Note 3)
VCC = 12 V 30
V
BOOT
= 4.5 V, V
BOOTLO
= 0 V 60
HIGHDR output
V
BOOT
= 6.5 V, V
BOOTLO
= 0 V 50
ns
(see Note 3)
V
BOOT
= 12 V, V
BOOTLO
= 0 V 50
Fall time
VCC = 4.5 V 40
LOWDR output
VCC = 6.5 V 30
ns
(see Note 3)
VCC = 12 V 30
V
BOOT
= 4.5 V, V
BOOTLO
= 0 V 130
HIGHDR going low
(excluding deadtime)
V
BOOT
= 6.5 V, V
BOOTLO
= 0 V 100
ns
p
(see Note 3)
V
BOOT
= 12 V, V
BOOTLO
= 0 V 75
Propagation delay time
V
BOOT
= 4.5 V, V
BOOTLO
= 0 V 80
LOWDR going high
(excluding deadtime)
V
BOOT
= 6.5 V, V
BOOTLO
= 0 V 70
ns
(see Note 3)
V
BOOT
= 12 V, V
BOOTLO
= 0 V 60
VCC = 4.5 V 80
Propagation delay time
LOWDR going low
(excluding deadtime)
VCC = 6.5 V 70
ns
(see Note 3)
VCC = 12 V 60
DT to LOWDR and
VCC = 4.5 V 40 170
Driver nonoverlap time
DT to LOWDR and
LOWDR to HIGHDR
VCC = 6.5 V 25 135
ns
(see Note 3)
VCC = 12 V 15 85
NOTE 3: Ensured by design, not production tested.
TPS2832, TPS2833
FAST SYNCHRONOUS-BUCK MOSFET DRIVER
WITH DEADTIME CONTROL
SLVS195B – JANUARY 1999 – REVISED SEPTEMBER 1999
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 1
10
46 810
15
RISE TIME
vs
SUPPLY VOLTAGE
50
13
VCC – Supply Voltage – V
35
40
45
20
25
30
t
r
– Rise Time – ns
5791112
Low Side
High Side
CL = 3.3 nF
TJ = 25 °C
1514
Figure 2
FALL TIME
vs
SUPPLY VOLTAGE
t
f
– Fall Time – ns
10
46 810
15
50
13
VCC – Supply Voltage – V
35
40
45
20
25
30
5791112
Low Side
High Side
CL = 3.3 nF
TJ = 25 °C
1514
Figure 3
RISE TIME
vs
JUNCTION TEMPERATURE
t
r
– Rise Time – ns
TJ – Junction Temperature – °C
10
0 50 100
15
50
125
35
40
45
20
25
30
25 75–50 –25
VCC = 6.5 V
CL = 3.3 nF
Low Side
High Side
Figure 4
FALL TIME
vs
JUNCTION TEMPERATURE
t
f
– Fall Time – ns
TJ – Junction Temperature – °C
10
0 50 100
15
50
125
35
40
45
20
25
30
25 75
Low Side
High Side
VCC = 6.5 V
CL = 3.3 nF
–50 –25
TPS2832, TPS2833
FAST SYNCHRONOUS-BUCK MOSFET DRIVER
WITH DEADTIME CONTROL
SLVS195B – JANUARY 1999 – REVISED SEPTEMBER 1999
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 5
20
46 810
30
LOW-TO-HIGH PROPAGATION DELAY TIME
vs
SUPPLY VOLTAGE, LOW TO HIGH LEVEL
150
13
VCC – Supply Voltage – V
70
80
90
40
50
60
5791112
120
130
140
100
110
Low Side
High Side
t
PLH
– Low-to-High Propagation Delay Time – ns
CL = 3.3 nF
TJ = 25 °C
1514
Figure 6
HIGH-TO-LOW PROPAGATION DELAY TIME
vs
SUPPLY VOLTAGE, HIGH TO LOW LEVEL
VCC – Supply Voltage – V
20
46 810
30
150
13
70
80
90
40
50
60
5791112
120
130
140
100
110
Low Side
High Side
t
PHL
– High-to-Low Propagation Delay Time – ns
CL = 3.3 nF
TJ = 25 °C
1514
Figure 7
LOW-TO-HIGH PROPAGATION DELAY TIME
vs
JUNCTION TEMPERATURE
TJ – Junction Temperature – °C
20
0 50 100
30
150
125
70
80
90
40
50
60
25 75
120
130
140
100
110
t
PLH
– Low-to-High Propagation Delay Time – ns
–25–50
VCC = 6.5 V
CL = 3.3 nF
High Side
Low Side
Figure 8
HIGH-TO-LOW PROPAGATION DELAY TIME
vs
JUNCTION TEMPERATURE
TJ – Junction Temperature – °C
20
0 50 100
30
150
125
70
80
90
40
50
60
25 75
120
130
140
100
110
t
PHL
– High-to-Low Propagation Delay Time – ns
Low Side
High Side
VCC = 6.5 V
CL = 3.3 nF
–25–50
TPS2832, TPS2833
FAST SYNCHRONOUS-BUCK MOSFET DRIVER
WITH DEADTIME CONTROL
SLVS195B – JANUARY 1999 – REVISED SEPTEMBER 1999
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 9
RISE TIME
vs
LOAD CAPACITANCE
CL – Load Capacitance – nF
t
r
– Rise Time – ns
100
10
1
1000
0.1 1 10 100
VCC = 6.5 V
TJ = 25 °C
Low Side
High Side
Figure 10
FALL TIME
vs
LOAD CAPACITANCE
CL – Load Capacitance – nF
100
10
1
1000
0.1 1 10 100
VCC = 6.5 V
TJ = 25 °C
Low Side
High Side
t
f
– Fall Time – ns
Figure 11
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
VCC – Supply Voltage – V
0
46 810
500
5000
14
3500
4000
4500
1000
1500
2500
12
CC
I Supply Current – –Aµ
2000
3000
200 kHz
100 kHz
50 kHz
25 kHz
16
6000
5500
500 kHz
TJ = 25 °C
CL = 50 pF
300 kHz
Figure 12
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
VCC – Supply Voltage – V
0
46 810 14
10
12
CC
I Supply Current – mA–
5
16
15
20
25
1 MHz
TJ = 25 °C
CL = 50 pF
2 MHz
TPS2832, TPS2833
FAST SYNCHRONOUS-BUCK MOSFET DRIVER
WITH DEADTIME CONTROL
SLVS195B – JANUARY 1999 – REVISED SEPTEMBER 1999
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 13
PEAK SOURCE CURRENT
vs
DRIVE VOLTAGE
Peak Source Current – A
VCC – Supply Voltage – V
0
46 810
0.5
4
14
2.5
3
3.5
1
1.5
2
12
Low Side
High Side
TJ = 25 °C
16
Figure 14
PEAK SINK CURRENT
vs
DRIVE VOLTAGE
Peak Sink Current – A
VCC – Supply Voltage – V
0
46 810
0.5
4
14
2.5
3
3.5
1
1.5
2
12
Low Side
High Side
TJ = 25 °C
16
INPUT THRESHOLD VOLTAGE
vs
SUPPLY VOLTAGE
VCC – Supply Voltage – V
0
46 810
1
8
14
5
6
7
2
3
4
12
V
IT
– Input Threshold Voltage – V
16
TJ = 25 °C
9
Figure 15
TPS2832, TPS2833
FAST SYNCHRONOUS-BUCK MOSFET DRIVER
WITH DEADTIME CONTROL
SLVS195B – JANUARY 1999 – REVISED SEPTEMBER 1999
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Figure 15 shows the circuit schematic of a 100-kHz synchronous-buck converter implemented with a TL5001A
pulse-width-modulation (PWM) controller and a TPS2833 driver. The converter operates over an input range from
4.5 V to 12 V and has a 3.3 V output. The circuit can supply 3 A continuous load and the transient load is 5 A. The
converter achieves an efficiency of 94% for V
IN
= 5 V, I
load
=1 A, and 93% for V
in
= 5 V, I
load
= 3 A.
C14
1 µF
R9
90.9 kΩ
R8
121 kΩ
C9
0.22 µF
V
CC
RT
FB
COMP
GND
OUT
DTC
SCP
U2
TL5001A
1
2
6
5
8
3
4
7
C1
1 µF
R10
1.0 kΩ
R2
1.6 kΩ
C2
0.033 µF
C3
0.0022 µF
C8
0.1 µF
C4
0.022 µFR3180 Ω
R4
2.32 kΩ
GND
Q2
Si4410
R7
3.3 Ω
C6
1000 pF
V
IN
C5
100 µF
C10
100 µF
C11
0.47 µF
3.3 V
C13
10 µF
C7
100 µF
C12
100 µF
Q1
Si4410
L1
27 µH
U1
TPS2833
R1
1 kΩ
C15
1.0 µF
R6
1 MΩ
R5
0 Ω
R11
4.7 Ω
RTN
PGND
LOWDR
BOOTLO
HIGHDR
BOOT
IN
DT
V
CC
1
2
3
4
8
7
6
5
+
+
+
+
Figure 16. 3.3 V 3 A Synchronous-Buck Converter Circuit
TPS2832, TPS2833
FAST SYNCHRONOUS-BUCK MOSFET DRIVER
WITH DEADTIME CONTROL
SLVS195B – JANUARY 1999 – REVISED SEPTEMBER 1999
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Great care should be taken when laying out the pc board. The power-processing section is the most critical and
will generate large amounts of EMI if not properly configured. The junction of Q1, Q2, and L1 should be very
tight. The connection from Q1 drain to the positive sides of C5, C10, and C1 1 and the connection from Q2 source
to the negative sides of C5, C10, and C11 should be as short as possible. The negative terminals of C7 and
C12 should also be connected to Q2 source.
Next, the traces from the MOSFET driver to the power switches should be considered. The BOOTLO signal from
the junction of Q1 and Q2 carries the large gate drive current pulses and should be as heavy as the gate drive
traces. The bypass capacitor (C14) should be tied directly across V
CC
and PGND.
The next most sensitive node is the FB node on the controller (terminal 4 on the TL5001A) This node is very
sensitive to noise pick up and should be isolated from the high-current power stage and be as short as possible.
The ground around the controller and low-level circuitry should be tied to the power ground as the output. If these
three areas are properly laid out, the rest of the circuit should not have any other EMI problems and the power
supply will be relatively free of noise.
TPS2832, TPS2833
FAST SYNCHRONOUS-BUCK MOSFET DRIVER
WITH DEADTIME CONTROL
SLVS195B – JANUARY 1999 – REVISED SEPTEMBER 1999
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
4040047/D 10/96
0.228 (5,80)
0.244 (6,20)
0.069 (1,75) MAX
0.010 (0,25)
0.004 (0,10)
1
14
0.014 (0,35)
0.020 (0,51)
A
0.157 (4,00)
0.150 (3,81)
7
8
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.010 (0,25)
PINS **
0.008 (0,20) NOM
A MIN
A MAX
DIM
Gage Plane
0.189
(4,80)
(5,00)
0.197
8
(8,55)
(8,75)
0.337
14
0.344
(9,80)
16
0.394
(10,00)
0.386
0.004 (0,10)
M
0.010 (0,25)
0.050 (1,27)
0°–8°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
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Copyright 1999, Texas Instruments Incorporated
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