Texas Instruments TPS2068IDGNRQ1 Schematic [ru]

DGNPACKAGE
(TOP VIEW)
GND
1 2 3 4
8 7 6 5
IN
IN
EN
OUT OUT OUT
TPS2068-Q1
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................................................................................................................................................................................................ SLVS999 –AUGUST 2009
CURRENT-LIMITED POWER-DISTRIBUTION SWITCH
Check for Samples: TPS2068-Q1
1

FEATURES

2
Qualified for Automotive Applications
70-mHigh-Side MOSFET
1.5-A Continuous Current
Thermal and Short-Circuit Protection
Accurate Current Limit (1.6 A Min, 2.6 A Max)
Operating Range: 2.7 V to 5.5 V
0.6-ms Typical Rise Time
Undervoltage Lockout
Deglitched Fault Report (OC)
No OC Glitch During Power Up
1-μA Maximum Standby Supply Current
Reverse Current Blocking
UL Listed – File No. E169910
CB Certified

DESCRIPTION

The TPS2068 power-distribution switches are intended for applications where heavy capacitive loads and short-circuits are likely to be encountered. This device incorporates 70-mN-channel MOSFET power switches for power-distribution systems that require single or dual power switches in a single package. Each switch is controlled by a logic enable input. Gate drive is provided by an internal charge pump designed to control the power-switch rise times and fall times to minimize current surges during switching. The charge pump requires no external components and allows operation from supplies as low as 2.7 V.
When the output load exceeds the current-limit threshold or a short is present, the device limits the output current to a safe level by switching into a constant-current mode, pulling the overcurrent (OC) logic output low. When continuous heavy overloads and short-circuits increase the power dissipation in the switch, causing the junction temperature to rise, a thermal protection circuit shuts off the switch to prevent damage. Recovery from a thermal shutdown is automatic once the device has cooled sufficiently. Internal circuitry ensures that the switch remains off until valid input voltage is present. Current limit is typically 2.1 A.

APPLICATIONS

Heavy Capacitive Loads
Short-Circuit Protections
1
2PowerPad is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2009, Texas Instruments Incorporated
TPS2068-Q1
SLVS999 –AUGUST 2009 ................................................................................................................................................................................................
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
T
A
PACKAGE
(2)
ORDERABLE PART NUMBER TOP-SIDE MARKING
(1)
–40°C to 85°C MSOP – DGN Reel of 2500 TPS2068IDGNRQ1 PSQQ
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted
Input voltage range, V
V
Input voltage range, V
I
Voltage range, V
V
Output voltage range, V
O
I
Continuous output current , I
O
Continuous total power dissipation See Dissipation Rating Table
T
Operating virtual-junction temperature range –40°C to 105°C
J
T
Storage temperature range –65°C to150°C
stg
ESD Electrostatic discharge protection Machine model (MM) 50 V
(1) Stresses beyond those listed under absolute maximum ratingsmay cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
I(IN) I(EN)
I(OC)
O(OUT)
O(OUT)
Human-body model (HBM) 1500 V
Charged-device model (CDM) 1000 V
(1)
–0.3 V to 6 V –0.3 V to 6 V –0.3 V to 6 V –0.3 V to 6 V
Internally limited

DISSIPATING RATING TABLE

PACKAGE
(2)
DGN-8
TA< 25°C DERATING FACTOR TA= 70°C TA= 85°C
POWER RATING ABOVE TA= 25°C POWER RATING POWER RATING
1370 mW 17 mW/°C 600 mW 342 mW
(1)
(1) Heatsink the PowerPad™per the recommendations of SLMA002. PCB used for recommendations per appendix A4. (2) See Recommended Operating Conditions Table for PowerPad connection guidelines to meet qualifying conditions for CB Certificate.

RECOMMENDED OPERATING CONDITIONS

(1)
MIN MAX UNIT
V
I T
Input voltage, V
I
Input voltage, V Continuous output current, I
O
Operating virtual-junction temperature –40 105 °C
J
I(IN) I(EN)
O(OUT)
2.7 5.5 V 0 5.5 V 0 1.5 A
(1) The thermal pad must be connected externally to GND pin to meet qualifying conditions for CB Certificate (DGN package only).
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................................................................................................................................................................................................ SLVS999 –AUGUST 2009

ELECTRICAL CHARACTERISTICS

–40°C TJ≤ 105° V
PARAMETER TEST CONDITIONS
POWER SWITCH
Static drain-source on-state resistance,
r
DS(on)
t
r
t
f
ENABLE INPUT EN
V
IH
V
IL
I
I
t
on
t
off
CURRENT LIMIT
I
OS
I
OC_TRIP
I
OS
I
OL
I
OH
I
lkg
UNDERVOLTAGE LOCKOUT
OVERCURRENT OC
V
OL(OC)
THERMAL SHUTDOWN
(1) Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account (2) Specified by design
(3) This configuration has not been tested for UL certification. (4) The thermal shutdown only reacts under overcurrent conditions.
5-V operation and 3.3-V operation Static drain-source on-state resistance,
2.7-V operation
Rise time, output
Fall time, output
High-level input voltage 2.7 V < V Low-level input voltage 2.7 V < V Input current V Turn-on time Turn-off time
Short-circuit output current 1.6 2.1 2.6 A Overcurrent trip threshold
(3)
Short-circuit output current
Supply current, low-level output No load on OUT, V
Supply current, high-level output No load on OUT, V
Leakage current OUT connected to ground, V Reverse leakage current V
Low-level input voltage, IN 2 2.5 V Hysteresis, IN TJ= 25°C 75 mV
Output low voltage I Off-state current V OC deglitch
Thermal shutdown threshold Recovery from thermal shutdown Hysteresis 10 °C
separately.
= 5.5 V, IO= 1 A, V
I(IN)
(2)
(2)
(2) (2)
(2)
(2)
(2)
(4)
(2)
= 0 V (unless otherwise noted)
I(EN)
(1)
V
= 5 V or 3.3 V, IO= 1.5 A 70 150 m
I(IN)
V
= 2.7 V, IO= 1.5 A 75 150 m
I(IN)
V
= 5.5 V 0.6 1.5
I(IN)
V
= 2.7 V 0.4 1
I(IN)
V
= 5.5 V 0.05 0.5
I(IN)
V
= 2.7 V 0.05 0.5
I(IN)
< 5.5 V 2
I(IN)
< 5.5 V 0.8
I(IN)
= 0 V or 5.5 V -0.5 0.5 μA
I(EN)
CL= 1 μF, RL= 5
TJ=25°C ms
MIN TYP MAX UNIT
CL= 100 μF, RL= 5 3 CL= 100 μF, RL= 5 10
V
= 5 V, OUT connected to GND,
I(IN)
Device enabled into short-circuit V
= 5 V, Current ramp (100 A/s) on OUT 2.3 2.85 3.4 A
I(IN)
V
= 5 V, OUT connected to GND, Device enabled into
I(IN)
short-circuit, current measured at V
= 5.5 V μA
I(EN)
= 0 V μA
I(EN)
= 5.5 V, IN = ground TJ= 25°C 0.2 μA
I(OUT)
= 5 mA 0.4 V
O(OC)
= 5 V or 3.3 V 1 μA
O(OC)
I(IN)
TJ= 25°C 0.5 1 Over TJrange 0.5 5 TJ= 25°C 43 60 Over TJrange 43 70
= 5.5 V 1 μA
I(EN)
3.2 4.2 5.2 A
OC assertion or deassertion 4 8 15 ms
135 °C
(2)
125 °C
V
ms
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OUT
OC
IN
EN
GND
Current
Limit
Driver
UVLO
Charge
Pump
CS
Thermal
Sense
Deglitch
(SeeNote A)
TPS2068-Q1
SLVS999 –AUGUST 2009 ................................................................................................................................................................................................
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DEVICE INFORMATION

Terminal Functions
NAME NO. I/O DESCRIPTION
EN 4 I Enable input, logic low turns on power switch GND 1 Ground IN 2,3 I Input voltage OC 5 O Overcurrent, open-drain output, active-low OUT 6, 7,8 O Power-switch output Thermal pad Connect to GND
(1) See the Recommended Operating Conditions Table for PowerPad connection guidelines to meet qualifying conditions for CB Certificate
(DGN package only).
(1)
Functional Block Diagram
A. Current sense.
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R
L
C
L
OUT
t
r
t
f
90%
90%
10%
10%
50%
50%
90%
10%
V
O(OUT)
V
I(EN)
V
O(OUT)
VOLTAGE WAVEFORMS
TEST CIRCUIT
t
on
t
off
50%
50%
90%
10%
V
I(EN)
V
O(OUT)
t
on
t
off
V
I(EN)
5V/div
V
O(OUT)
2V/div
t-Time-400 sm
R =5
C =1 F,
L
L
W
m
,
=25 CT
A
°
V
I(EN)
5V/div
V
O(OUT)
2V/div
t-Time-400 sm
R =5
C =1 F,
L
L
W
m
,
=25 CT
A
°
TPS2068-Q1
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................................................................................................................................................................................................ SLVS999 –AUGUST 2009

PARAMETER MEASUREMENT INFORMATION

Figure 1. Test Circuit and Voltage Waveforms
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V
I(EN)
5V/div
V
O(OUT)
2V/div
t-Time-400 sm
R =5
C =100 F,
L
L
W
m
,
=25 CT
A
°
V
I(EN)
5V/div
V
O(OUT)
2V/div
t-Time-400 sm
R =5
C =100 F,
L
L
W
m
,
=25 CT
A
°
V
I(EN)
5 V/div
I
O(OUT)
500 mA/div
t − Time − 500 ms/div
220 mF
470 mF
100 mF
V
I(EN)
5 V/div
I
O(OUT)
500 mA/div
t − Time − 500 ms/div
VIN = 5 V , RL = 3 W, TA = 255C
TPS2068-Q1
SLVS999 –AUGUST 2009 ................................................................................................................................................................................................
PARAMETER MEASUREMENT INFORMATION (continued)
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V
O( )OCx
2V/div
I
O(OUT)
1 A/div
t-Time-2ms/div
TPS2068-Q1
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................................................................................................................................................................................................ SLVS999 –AUGUST 2009
PARAMETER MEASUREMENT INFORMATION (continued)
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0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
2 3 4 5 6
Turnon Time − ms
VI − Input Voltage − V
CL = 100 mF, RL = 5 W, TA = 255C
1.5
1.6
1.7
1.8
1.9
2
2 3 4 5 6
CL = 100 mF, RL = 5 W, TA = 255C
Turnoff Time − mS
VI − Input Voltage − V
0
0.1
0.2
0.3
0.4
0.5
0.6
2 3 4 5 6
Rise Time − ms
VI − Input Voltage − V
CL = 1 mF, RL = 5 W, TA = 255C
0
0.05
0.1
0.15
0.2
0.25
2 3 4 5 6
CL = 1 mF, RL = 5 W, TA = 255C
Fall Time − ms
VI − Input Voltage − V
TPS2068-Q1
SLVS999 –AUGUST 2009 ................................................................................................................................................................................................

TYPICAL CHARACTERISTICS

TURNON TIME TURNOFF TIME
vs vs
INPUT VOLTAGE INPUT VOLTAGE
Figure 9. Figure 10.
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RISE TIME FALL TIME
vs vs
INPUT VOLTAGE INPUT VOLTAGE
Figure 11. Figure 12.
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0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
−50 0 50 100 150
VI = 5.5 V
VI = 5 V
VI = 3.3 V
VI = 2.7 V
TJ − Junction Temperature − 5C
− Supply Current, Output Disabled −
I
I (IN)
Aµ
0
10
20
40
50
60
-50
0 50 100 150
30
T -JunctionTemperature- CJ°
I -SupplyCurrent,OutputEnabled- A
I(IN)
m
V =5.5V
I
V =3.3V
I
V =2.7V
I
V =5V
I
0
20
40
60
80
100
120
−50 0 50 100 150
Out1 = 5 V
Out1 = 3.3 V
Out1 = 2.7 V
IO = 0.5 A
TJ − Junction Temperature − 5C
r
DS(on) − Static Drain-Source
On-State Resistance − m
1.6
1.7
1.8
1.9
2
2.2
2.3
2.4
2.5
2.6
-50
0 50 100 150
2.1
T -JunctionTemperature- CJ°
I -Short-CircuitCurrentLimit- A
OS
V =2.7V
I
V =3.3V
I
V =5V
I
V =5.5V
I
TPS2068-Q1
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................................................................................................................................................................................................ SLVS999 –AUGUST 2009
TYPICAL CHARACTERISTICS (continued)
SUPPLY CURRENT, OUTPUT ENABLED SUPPLY CURRENT, OUTPUT DISABLED
vs vs
JUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 13. Figure 14.
STATIC DRAIN-SOURCE ON-STATE RESISTANCE SHORT-CIRCUIT OUTPUT CURRENT
JUNCTION TEMPERATURE JUNCTION TEMPERATURE
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Figure 15. Figure 16.
vs vs
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2.1
2.14
2.18
2.22
2.26
2.3
−50 0 50 100 150
UVLO Rising
UVLO Falling
UVOL − Undervoltage Lockout − V
TJ − Junction Temperature − 5C
0
50
100
150
200
0 2.5
5 7.5
10
Current-LimitResponse- sm
PeakCurrent- A
VI=5V, T
A
°=25 C
TPS2068-Q1
SLVS999 –AUGUST 2009 ................................................................................................................................................................................................
TYPICAL CHARACTERISTICS (continued)
UNDERVOLTAGE LOCKOUT CURRENT-LIMIT RESPONSE
vs vs
JUNCTION TEMPERATURE PEAK CURRENT
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Figure 17. Figure 18.
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IN
OC1 EN1 OC2
2
8
5
7
0.1 µF 22 µF
0.1 µF 22 µF
Load
Load
OUT1
OUT2
Power Supply
2.7 V to 5.5 V
6
EN2
3
4
GND
0.1 µF
TPS2060
1
TPS2068-Q1
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................................................................................................................................................................................................ SLVS999 –AUGUST 2009

APPLICATION INFORMATION

Power-Supply Considerations

Figure 19. Typical Application
A 0.01-μF to 0.1-μF ceramic bypass capacitor between IN and GND, close to the device, is recommended. Placing a high-value electrolytic capacitor on the output pin(s) is recommended when the output load is heavy. This precaution reduces power-supply transients that may cause ringing on the input. Additionally, bypassing the output with a 0.01-μF to 0.1-μF ceramic capacitor improves the immunity of the device to short-circuit transients.

Overcurrent

A sense FET is employed to check for overcurrent conditions. Unlike current-sense resistors, sense FETs do not increase the series resistance of the current path. When an overcurrent condition is detected, the device maintains a constant output current and reduces the output voltage accordingly. Complete shutdown occurs only if the fault is present long enough to activate thermal limiting.
Three possible overload conditions can occur. In the first condition, the output has been shorted before the device is enabled or before V
has been applied (see Figure 6). The TPS2068 senses the short and
I(IN)
immediately switches into a constant-current output. In the second condition, a short or an overload occurs while the device is enabled. At the instant the overload
occurs, high currents may flow for a short period of time before the current-limit circuit can react (see
Figure 8).After the current-limit circuit has tripped (reached the overcurrent trip threshold), the device switches
into constant-current mode. In the third condition, the load has been gradually increased beyond the recommended operating current. The
current is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device is exceeded. The TPS2068 is capable of delivering current up to the current-limit threshold without damaging the device. Once the threshold has been reached, the device switches into its constant-current mode.

OC Response

The OC open-drain output is asserted (active low) when an overcurrent or overtemperature shutdown condition is encountered after a 10-ms deglitch timeout. The output remains asserted until the overcurrent or overtemperature condition is removed. Connecting a heavy capacitive load to an enabled device can cause a momentary overcurrent condition; however, no false reporting on OC occurs due to the 10-ms deglitch circuit. The TPS2068 is designed to eliminate false overcurrent reporting. The internal overcurrent deglitch eliminates the need for external components to remove unwanted pulses. OC is not deglitched when the switch is turned off due to an overtemperature shutdown.
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GND IN EN1
EN2
OC1
OC2
OUT1 OUT2
TPS2060
R
pullup
V+
TPS2068-Q1
SLVS999 –AUGUST 2009 ................................................................................................................................................................................................
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Figure 20. Typical Circuit for theOC Pin

Power Dissipation and Junction Temperature

The low on-resistance on the N-channel MOSFET allows the small surface-mount packages to pass large currents. The thermal resistance of these packages are high compared to those of power packages; it is good design practice to check power dissipation and junction temperature. Begin by determining the r N-channel MOSFET relative to the input voltage and operating temperature. As an initial estimate, use the highest operating ambient temperature of interest and read r
from Figure 15. Using this value, the power
DS(on)
dissipation per switch can be calculated by:
PD= r
DS(on)
× I
2
Multiply this number by the number of switches being used. This step renders the total power dissipation from the N-channel MOSFETs.
Finally, calculate the junction temperature:
TJ= PD× R
θJA
+ T
A
Where:
TA= Ambient temperature °C R
= Thermal resistance
θJA
PD= Total power dissipation based on number of switches being used.
Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees, repeat the calculation, using the calculated value as the new estimate. Two or three iterations are generally sufficient to get a reasonable answer.
DS(on)
of the

Thermal Protection

Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present for extended periods of time. The TPS2068 implements a thermal sensing to monitor the operating junction temperature of the power distribution switch. In an overcurrent or short-circuit condition, the junction temperature rises due to excessive power dissipation. Once the die temperature rises to approximately 140°C due to overcurrent conditions, the internal thermal sense circuitry turns the power switch off, thus preventing the power switch from damage. Hysteresis is built into the thermal sense circuit, and after the device has cooled approximately10°C, the switch turns back on. The switch continues to cycle in this manner until the load fault or input power is removed. The OC open-drain output is asserted (active low) when an overtemperature shutdown or overcurrent occurs.

Undervoltage Lockout (UVLO)

An undervoltage lockout ensures that the power switch is in the off state at power up. Whenever the input voltage falls below approximately 2 V, the power switch is quickly turned off. This facilitates the design of hot-insertion systems where it is not possible to turn off the power switch before input power is removed. The UVLO also keeps the switch from being turned on until the power supply has reached at least 2 V, even if the switch is enabled. On reinsertion, the power switch is turned on, with a controlled rise time to reduce EMI and voltage overshoots.
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................................................................................................................................................................................................ SLVS999 –AUGUST 2009

Universal Serial Bus (USB) Applications

The universal serial bus (USB) interface is a 12-Mb/s, or 1.5-Mb/s, multiplexed serial bus designed for low­to-medium bandwidth PC peripherals (e.g., keyboards, printers, scanners, and mice). The four-wire USB interface is conceived for dynamic attach-detach (hot plug-unplug) of peripherals. Two lines are provided for differential data, and two lines are provided for 5-V power distribution.
USB data is a 3.3-V level signal, but power is distributed at 5 V to allow for voltage drops in cases where power is distributed through more than one hub across long cables. Each function must provide its own regulated 3.3 V from the 5-V input or its own internal power supply.
The USB specification defines the following five classes of devices, each differentiated by power-consumption requirements:
Hosts/self-powered hubs (SPH)
Bus-powered hubs (BPH)
Low-power, bus-powered functions
High-power, bus-powered functions
Self-powered functions SPHs and BPHs distribute data and power to downstream functions. The TPS2068 has higher current capability
than required by one USB port; so, it can be used on the host side and supplies power to multiple downstream ports or functions.

Host/Self-Powered and Bus-Powered Hubs

Hosts and SPHs have a local power supply that powers the embedded functions and the downstream ports (see
Figure 21). This power supply must provide from 5.25 V to 4.75 V to the board side of the downstream
connection under full-load and no-load conditions. Hosts and SPHs are required to have current-limit protection and must report overcurrent conditions to the USB controller. Typical SPHs are desktop PCs, monitors, printers, and stand-alone hubs.
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IN
OC1 EN1 OC2 EN2
GND
0.1 µF
2
8 3
5 4
7
22 µF
22 µF
GND
1
OUT1
TPS2060
Power Supply
D+ D−
V
BUS
GND
D+ D−
V
BUS
Downstream
USB Ports
USB
Controller
3.3 V
5 V
2 µF
GND
OUT2
D+ D−
V
BUS
22 µF
GND
D+ D−
V
BUS
6
0.1 µF
0.1 µF
0.1 µF
0.1 µF
22 µF
GND
D+ D−
V
BUS
0.1 µF
22 µF
GND
D+ D−
V
BUS
0.1 µF
TPS2068-Q1
SLVS999 –AUGUST 2009 ................................................................................................................................................................................................
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BPHs obtain all power from upstream ports and often contain an embedded function. The hubs are required to power up with less than one unit load. The BPH usually has one embedded function, and power is always available to the controller of the hub. If the embedded function and hub require more than 100 mA on power up,
Figure 21. Typical Six-Port USB Host/Self-Powered Hub
the power to the embedded function may need to be kept off until enumeration is completed. This can be accomplished by removing power or by shutting off the clock to the embedded function. Power switching the embedded function is not necessary if the aggregate power draw for the function and controller is less than one unit load. The total current drawn by the bus-powered device is the sum of the current to the controller, the embedded function, and the downstream ports, and it is limited to 500 mA from an upstream port.
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IN
OC1
OC2
2
8 3
5 4
7
0.1 µF 10 µF
Internal
Function
OUT1
Power Supply
3.3 V
EN1
6
0.1 µF 10 µF
OUT2
Internal
Function
0.1 µF
10 µF
USB
Control
GND
V
BUS
D−
D+
TPS2060
EN2
GND 1
TPS2068-Q1
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................................................................................................................................................................................................ SLVS999 –AUGUST 2009

Low-Power Bus-Powered and High-Power Bus-Powered Functions

Both low-power and high-power bus-powered functions obtain all power from upstream ports; low-power functions always draw less than 100mA; high-power functions must draw less than 100 mA at power up and can draw up to 500 mA after enumeration. If the load of the function is more than the parallel combination of 44 and 10 μF at power up, the device must implement inrush current limiting (see Figure 22). With TPS2068, the internal functions could draw more than 500 mA, which fits the needs of some applications such as motor driving circuits.
Figure 22. High-Power Bus-Powered Function

USB Power-Distribution Requirements

USB can be implemented in several ways, and, regardless of the type of USB device being developed, several power-distribution features must be implemented.
Hosts/SPHs must: – Current-limit downstream ports – Report overcurrent conditions on USB V
BPHs must: – Enable/disable power to downstream ports – Power up at <100 mA – Limit inrush current (<44 and 10 μF)
Functions must: – Limit inrush currents – Power up at <100 mA
The feature set of the TPS2068 allows them to meet each of these requirements. The integrated current-limiting and overcurrent reporting is required by hosts and self-powered hubs. The logic-level enable and controlled rise times meet the need of both input and output ports on bus-powered hubs, as well as the input ports for bus-powered functions (see Figure 23).
BUS
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): TPS2068-Q1
DP1
DM1
DP2
DM2
DP3
DM3
DP4
PWRON1
OVRCUR1
PWRON2
OVRCUR2
DM4
DP0 DM0
V
CC
XTAL1
XTAL2
OCSOFF
SN75240
D + D −
5 V
GND
D + D −
5 V
D + D −
5 V
D + D −
5 V
48-MHz Crystal
Downstream
Ports
TUSB2040
Hub Controller
Tuning
Circuit
ABC
D
33 µF
SN75240
ABC
D
GND
GND
GND
33 µF
33 µF
33 µF
D + D −
Upstream Port
TPS2041B
SN75240
A
B
5 V
GND
C D
1 µF
IN
GND
Ferrite Beads
Ferrite Beads
Ferrite Beads
Ferrite Beads
BUSPWR GANGED
Tie to TPS2041 EN
Input
OC EN
OUT
5-V Power
Supply
IN
GND
3.3 V
4.7 µF
0.1 µF
4.7 µF
EN1
IN
OC1
OUT1
TPS2060
EN2 OC2
OUT2
0.1 µF
GND
USB rev 1.1 requires 120 µF per hub.
TPS76333
TPS2068-Q1
SLVS999 –AUGUST 2009 ................................................................................................................................................................................................
www.ti.com

Generic Hot-Plug Applications

Figure 23. Hybrid Self / Bus-Powered Hub Implementation
In many applications it may be necessary to remove modules or PC boards while the main unit is still operating. These are considered hot-plug applications. Such implementations require the control of current surges seen by the main power supply and the card being inserted. The most effective way to control these surges is to limit and slowly ramp the current and voltage being applied to the card, similar to the way in which a power supply normally turns on. Due to the controlled rise times and fall times of the TPS2068, these devices can be used to provide a softer start-up to devices being hot-plugged into a powered system. The UVLO feature of the TPS2068 also ensures that the switch is off after the card has been removed, and that the switch is off during the next insertion. The UVLO feature insures a soft start with a controlled rise time for every insertion of the card or module.
16 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TPS2068-Q1
Power
Supply
0.1 µF
1000 µF Optimum
2.7 V to 5.5 V
PC Board
Overcurrent Response
TPS2060
OC1
GND
EN1
IN
EN2
OUT1
OUT2
OC2
Block of Circuitry
Block of Circuitry
TPS2068-Q1
www.ti.com
................................................................................................................................................................................................ SLVS999 –AUGUST 2009
Figure 24. Typical Hot-Plug Implementation
By placing the TPS2068 between the VCCinput and the rest of the circuitry, the input power reaches these devices first after insertion. The typical rise time of the switch is approximately 1 ms, providing a slow voltage ramp at the output of the device. This implementation controls system surge currents and provides a hot-plugging mechanism for any device.

DETAILED DESCRIPTION

Power Switch

The power switch is an N-channel MOSFET with a low on-state resistance. Configured as a high-side switch, the power switch prevents current flow from OUT to IN and IN to OUT when disabled. The power switch supplies a minimum current of 1.5 A.

Charge Pump

An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate of the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requires little supply current.

Driver

The driver controls the gate voltage of the power switch. To limit large current surges and reduce the associated electromagnetic interference (EMI) produced, the driver incorporates circuitry that controls the rise times and fall times of the output voltage.

Enable (EN)

The logic enable disables the power switch and the bias for the charge pump, driver, and other circuitry to reduce the supply current. The supply current is reduced to less than 1 μA when a logic high is present on EN. A logic zero input on EN restores bias to the drive and control circuits and turns the switch on. The enable input is compatible with both TTL and CMOS logic levels.

Overcurrent (OC)

The OC open-drain output is asserted (active low) when an overcurrent or overtemperature condition is encountered. The output remains asserted until the overcurrent or overtemperature condition is removed. A 10-ms deglitch circuit prevents the OC signal from oscillation or false triggering. If an overtemperature shutdown occurs, the OC is asserted instantaneously.
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): TPS2068-Q1
TPS2068-Q1
SLVS999 –AUGUST 2009 ................................................................................................................................................................................................
www.ti.com

Current Sense

A sense FET monitors the current supplied to the load. The sense FET measures current more efficiently than conventional resistance methods. When an overload or short circuit is encountered, the current-sense circuitry sends a control signal to the driver. The driver in turn reduces the gate voltage and drives the power FET into its saturation region, which switches the output into a constant-current mode and holds the current constant while varying the voltage on the load.

Thermal Sense

The TPS2068 implements a thermal sensing to monitor the operating temperature of the power distribution switch. In an overcurrent or short-circuit condition the junction temperature rises. When the die temperature rises to approximately 140°C due to overcurrent conditions, the internal thermal sense circuitry turns off the switch, thus preventing the device from damage. Hysteresis is built into the thermal sense, and after the device has cooled approximately 10 degrees, the switch turns back on. The switch continues to cycle off and on until the fault is removed. The open-drain false reporting output (OC) is asserted (active low) when an overtemperature shutdown or overcurrent occurs.

Undervoltage Lockout

A voltage sense circuit monitors the input voltage. When the input voltage is below approximately 2 V, a control signal turns off the power switch.
18 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TPS2068-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device Status
TPS2068IDGNRQ1 ACTIVE MSOP-
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
Package Type Package
(1)
PowerPAD
Drawing
DGN 8 2500 Green (RoHS
Pins Package
Qty
Eco Plan
(2)
& no Sb/Br)
Lead/Ball Finish MSL Peak Temp
(3)
CU NIPDAU Level-2-260C-1 YEAR -40 to 85 PSQQ
Op Temp (°C) Top-Side Markings
(4)
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS2068-Q1 :
Catalog: TPS2068
Samples
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
11-Apr-2013
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
TPS2068IDGNRQ1 MSOP-
Type
Power
PAD
Package Drawing
DGN 8 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1
Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm)B0(mm)K0(mm)P1(mm)W(mm)
Quadrant
Pin1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Jan-2013
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS2068IDGNRQ1 MSOP-PowerPAD DGN 8 2500 370.0 355.0 55.0
Pack Materials-Page 2
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