Texas Instruments TPS2060DGN, TPS2060DRBR, TPS2064DGN, TPS2064DRBR, TPS2068D Schematic [ru]

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D−8 DRB−8DGN−8

TPS2060/TPS2064

DGNPACKAGE

(TOP VIEW)

GND

1 2 3 4

8 7 6 5

EN1 EN2

OC1 OUT1 OUT2

OC2

TPS2068

DGNPACKAGE

(TOP VIEW)

GND

1 2 3 4

8 7 6 5

OUT OUT OUT

TPS2069

DGNPACKAGE

(TOP VIEW)

GND

1 2 3 4

8 7 6 5

IN IN

OUT OUT OUT

TPS2068

DPACKAGE

(TOP VIEW)

GND

OUT

GND

EN1

†

EN2

OC1

OUT1

OUT2

OC2

TPS2060/TPS2064

DRBPACKAGES

(TOP VIEW)

† Allenableinputsareactivehighforthe TPS2064devices.

†

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SLVS553K –MARCH 2005– REVISED MAY 2011

CURRENT-LIMITED, POWER-DISTRIBUTION SWITCHES

Check for Samples: TPS2060, TPS2064, TPS2068, TPS2069

FEATURES

• 70-mΩ High-Side MOSFET

• 1.5-A Continuous Current • Short-Circuit Protections

• Thermal and Short-Circuit Protection

• Accurate Current Limit (1.6 A min, 2.6 A max)

• Operating Range: 2.7 V to 5.5 V

• 0.6-ms Typical Rise Time

• Undervoltage Lockout

• Deglitched Fault Report (OC)

• No OC Glitch During Power Up

• 1-μA Maximum Standby Supply Current

• Reverse Current Blocking

• TPS2060/64 Temperature Range: 0°C to 70°C

• TPS2068/69 DGN Package Temperature Range: –40°C to 85°C

• TPS2068 D Package Temperature Range: 0°C to 70°C

• UL Listed – File No. E169910

• TPS2068/69: CB Certified

APPLICATIONS

• Heavy Capacitive Loads

TPS2060, TPS2064 TPS2068, TPS2069

DESCRIPTION

The TPS206x power-distribution switches are intended for applications where heavy capacitive loads and short-circuits are likely to be encountered. This device incorporates 70-mΩ N-channel MOSFET power switches for power-distribution systems that require single or dual power switches in a single package. Each switch is controlled by a logic enable input. Gate drive is provided by an internal charge pump designed to control the power-switch rise times and fall times to minimize current surges during switching. The charge pump requires no external components and allows operation from supplies as low as 2.7 V.

When the output load exceeds the current-limit threshold or a short is present, the device limits the output current to a safe level by switching into a constant-current mode, pulling the overcurrent (OCx) logic output low. When continuous heavy overloads and short-circuits increase the power dissipation in the switch, causing the junction temperature to rise, a thermal protection circuit shuts off the switch to prevent damage. Recovery from a thermal shutdown is automatic once the device has cooled sufficiently. Internal circuitry ensures that the switch remains off until valid input voltage is present. Current limit is typically 2.1 A.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2PowerPad is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

TPS2060, TPS2064 TPS2068, TPS2069

SLVS553K –MARCH 2005– REVISED MAY 2011

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

AVAILABLE OPTION AND ORDERING INFORMATION

RECOMMENDED TYPICAL PACKAGED

0°C to 70°C Dual

–40°C to 85°C Single

ENABLE

Active low TPS2060DGN TPS2060DRB

Active high TPS2064DGN TPS2064DRB

Active low 1.5 A 2.1 A TPS2068DGN

Active high TPS2069DGN

MAXIMUM SHORT-CIRCUIT NUMBER OF DEVICES

CONTINUOUS CURRENT LIMIT SWITCHES

LOAD CURRENT AT 25°C

MSOP (DGN) SON (DRB)

0°C to 70°C Active low Single TPS2068D

(1) The package is available taped and reeled. Add an R suffix to device types (e.g., TPS2060DGN). (2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted

Input voltage range, V

VIInput voltage range, V

Voltage range, V VOOutput voltage range, V I

Continuous output current, I

Continuous total power dissipation See Dissipation Rating Table

Operating virtual junction temperature

range

Storage temperature range –65°C to 150°C

stg

ESD Electrostatic discharge protection

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

I(/OC)

I(IN) I(/ENx)

, V

I(/OCx)

O(OUT)

I(ENx)

, V

O(OUT)

O(OUTx)

, I

O(OUTx)

TPS2060/64 0°C to 105°C TPS2068/69 (DGN Package) –40°C to 105°C TPS2068 (D Package) 0°C to 105°C

Human body model MIL-STD-883C 2 kV Charge device model (CDM) 500 V

(1)

UNIT

–0.3 V to 6 V –0.3 V to 6 V –0.3 V to 6 V –0.3 V to 6 V

Internally limited

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(1) (2)

DISSIPATING RATING TABLE

(1)

THERMAL TA< 25°C DERATING TA= 70°C TA= 85°C

PACKAGE RESISTANCE POWER RATING FACTOR POWER RATING POWER RATING

DGN-8

(2)

1370 mW 17 mW/°C 600 mW 342 mW

ABOVE TA= 25°C

D-8 585.82 mW 5.8582 mW/°C 322.20 mW 234.32 mW

DRB-8 (Low-K)

DRB-8 (High-K)

(3)

(4)

270 °CW 370 mW 3.71 mW/°C 203 mW 148 mW

60 °CW 1600 mW 16.67 mW/°C 916 mW 866 mW

(1) Heatsink the PowerPad™per the recommendations of SLMA002. PCB used for recommendations per appendix A4. (2) See Recommended Operating Conditions Table for PowerPad connection guidelines to meet qualifying conditions for CB Certificate. (3) Soldered PowerPAD on a standard 2-layer PCB without vias for thermal pad. See TI application note SLMA002 for further details. (4) Soldered PowerPAD on a standard 4-layer PCB with vias for thermal pad. See TI application note SLMA002 for further details.

TPS2060, TPS2064 TPS2068, TPS2069

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RECOMMENDED OPERATING CONDITIONS

Input voltage, V

Input voltage, V Continuous output current, I

I(IN) I(ENx)

, V

I(/ENx)

O(OUTx)

(1)

TPS2060/64 0 105

Operating virtual junction temperature TPS2068/69 (DGN Package) –40 105 °C

TPS2068 (D Package) 0 105

(1) The PowerPad must be connected externally to GND pin to meet qualifying conditions for CB Certificate (DGN package only).

ELECTRICAL CHARACTERISTICS

0°C ≤ TJ≤ 105°C for the TPS2060/64 and TPS2068 (D package), plus –40°C ≤ TJ≤ 105° for the TPS2068/69 (DGN package), V

PARAMETER TEST CONDITIONS

POWER SWITCH

Static drain-source on-state resistance, 5-V operation and V

DS(on)

ENABLE INPUT EN OR EN

off

CURRENT LIMIT

OC_TRIP

lkg

UNDERVOLTAGE LOCKOUT

(1) Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account (2) This configuration has not been tested for UL certification.

3.3-V operation Static drain-source on-state resistance,

2.7-V operation

Rise time, output

Fall time, output

High-level input voltage 2.7 V < V Low-level input voltage 2.7 V < V Input current V Turnon time CL= 100 μF, RL= 5 Ω 3 Turnoff time CL= 100 μF, RL= 5 Ω 10

Short-circuit output current 1.6 2.1 2.6 A

Overcurrent trip threshold A

(2)

Short-circuit output current 3.2 4.2 5.2 A Overcurrent trip threshold V

(2)

TPS2060/64 together, current measured at V

Supply current, low-level output μA

Supply current, high-level output No load on OUT, V TPS2060/64 or V

Supply current, high-level output No load on OUT, V TPS2068/69 or V

Leakage current 1 μA Reverse leakage current V

Low-level input voltage, IN 2 2.5 V Hysteresis, IN TJ= 25°C 75 mV

separately.

= 5.5 V, IO= 1 A, V

I(IN)

I(/ENx)

I(IN)

short-circuit V

I(IN)

(≤ 100 A/s) on OUT V

I(IN)

into short-circuit, current measured at V

I(IN)

No load on OUT, V or V

OUT connected to ground, V or V

I(OUTx)

I(/ENx)

= 0 V, or V

= 5.5 V (unless otherwise noted).

I(ENx)

(1)

= 5 V or 3.3 V, IO= 1.5 A 70 115 mΩ

= 2.7 V, IO= 1.5 A 75 125 mΩ = 5.5 V 0.6 1.5

= 2.7 V 0.4 1 = 5.5 V 0.05 0.5

CL= 1 μF, RL= 5 Ω

= 2.7 V 0.05 0.5

< 5.5 V 2

I(IN)

< 5.5 V 0.8

I(IN)

= 0 V or 5.5 V, V

= 0 V or 5.5 V -0.5 0.5 μA

I(ENx)

= 5 V, OUT connected to GND, device enabled into

= 5 V, Current ramp

= 5 V, OUT1 and OUT2 connected to GND, Device enabled

I(IN)

= 5 V, Current ramp (≤ 100 A/s) on OUT1 and OUT2 tied

I(IN)

= 5.5 V,

I(ENx)

= 0 V

= 5.5 V

= 0 V

I(/ENx)

= 0 V,

I(/ENx)

= 5.5 V,

= 5.5 V, IN = ground TJ= 25°C 0.2 μA

SLVS553K –MARCH 2005– REVISED MAY 2011

MIN MAX UNIT

2.7 5.5 V 0 5.5 V 0 1.5 A

MIN TYP MAX UNIT

TJ= 25°C ms

TPS2060/64 3.2 3.9 TPS2068/69 2.3 2.85 3.4

6.4 7.8 A

TJ= 25°C 0.5 1 Over TJrange 0.5 5 TJ= 25°C 50 70 Over TJrange 50 90 TJ= 25°C 43 60 Over TJrange 43 70

μA

TPS2060, TPS2064 TPS2068, TPS2069

SLVS553K –MARCH 2005– REVISED MAY 2011

ELECTRICAL CHARACTERISTICS (continued)

0°C ≤ TJ≤ 105°C for the TPS2060/64 and TPS2068 (D package), plus –40°C ≤ TJ≤ 105° for the TPS2068/69 (DGN package), V

PARAMETER TEST CONDITIONS

OVERCURRENT OCx

OL(/OCx)

THERMAL SHUTDOWN

(3) The thermal shutdown only reacts under overcurrent conditions.

DGN and DRB PACKAGES

NAME TPS2060 TPS2064

EN1 3 — I Enable input, logic low turns on power switch IN-OUT1 EN2 4 — I Enable input, logic low turns on power switch IN-OUT2 EN1 — 3 I Enable input, logic high turns on power switch IN-OUT1 EN2 — 4 I Enable input, logic high turns on power switch IN-OUT2 GND 1 1 Ground IN 2 2 I Input voltage OC1 8 8 O Overcurrent, open-drain output, active low, IN-OUT1 OC2 5 5 O Overcurrent, open-drain output, active low, IN-OUT2 OUT1 7 7 O Power-switch output, IN-OUT1 OUT2 6 6 O Power-switch output, IN-OUT2

Output low voltage I Off-state current V OC deglitch OCx assertion or deassertion 4 8 15 ms

(3)

Thermal shutdown threshold 135 °C Recovery from thermal shutdown 125 °C Hysteresis 10 °C

PINS

PowerPad PowerPad Connect to GND

= 5.5 V, IO= 1 A, V

I(IN)

O(/OCx)

= 5 mA 0.4 V

= 5 V or 3.3 V 1 μA

I(/ENx)

= 0 V, or V

= 5.5 V (unless otherwise noted).

I(ENx)

(1)

DEVICE INFORMATION

Pin Functions

I/O DESCRIPTION

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MIN TYP MAX UNIT

Thermal

Sense

Driver

Current

Limit

Charge

Pump

UVLO

Driver

Current

Limit

Thermal

Sense

Charge

Pump

GND

EN1

EN2

OC1

OUT1

OUT2

OC2

Deglitch

(SeeNote A)

(SeeNoteB)

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TPS2060, TPS2064 TPS2068, TPS2069

SLVS553K –MARCH 2005– REVISED MAY 2011

Functional Block Diagram (TPS2060 and TPS2064)

A. Current sense. B. Active low (ENx) for TPS2060. Active high (ENx) for TPS2064.

OUT

GND

Current

Limit

Driver

UVLO

Charge

Pump

Thermal

Sense

Deglitch

(SeeNote A)

(SeeNoteB)

TPS2060, TPS2064 TPS2068, TPS2069

SLVS553K –MARCH 2005– REVISED MAY 2011

DEVICE INFORMATION

Pin Functions (TPS2068 and TPS2069)

PINS

NAME TPS2068 TPS2069

EN 4 — I Enable input, logic low turns on power switch EN — 4 I Enable input, logic high turns on power switch GND 1 1 Ground IN 2, 3 2, 3 I Input voltage OC 5 5 O Overcurrent, open-drain output, active-low OUT 6, 7, 8 6, 7, 8 O Power-switch output

PowerPad PowerPad Connect to GND (DGN Package Only)

(1) See the Recommended Operating Conditions Table for PowerPad connection guidelines to meet qualifying conditions for CB Certificate

(DGN package only).

Functional Block Diagram (TPS2068 and TPS2069)

I/O DESCRIPTION

(1)

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A. Current sense. B. Active low (EN) for TPS2068. Active high (EN) for TPS2069.

OUT

90%

10%

50%

90%

10%

O(OUT)

I(EN)

O(OUT)

VOLTAGE WAVEFORMS

TEST CIRCUIT

off

50%

90%

10%

I(EN)

O(OUT)

off

I(EN)

5V/div

O(OUT)

2V/div

t-Time-400 sm

R =5

C =1 F,

=25 CT

I(EN)

5V/div

O(OUT)

2V/div

t-Time-400 sm

R =5

C =1 F,

=25 CT

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TPS2060, TPS2064 TPS2068, TPS2069

SLVS553K –MARCH 2005– REVISED MAY 2011

PARAMETER MEASUREMENT INFORMATION

Figure 1. Test Circuit and Voltage Waveforms

Figure 2. Turnon Delay and Rise Time With 1-μF Figure 3. Turnoff Delay and Fall Time With 1-μF

Load Load

I(EN)

5V/div

O(OUT)

2V/div

t-Time-400 sm

R =5

C =100 F,

=25 CT

I(EN)

5V/div

O(OUT)

2V/div

t-Time-400 sm

R =5

C =100 F,

=25 CT

I(EN)

5 V/div

O(OUT)

1 A/div

t − Time − 500 ms/div

220 mF

470 mF

100 mF

I(EN)

5 V/div

O(OUT)

500 mA/div

t − Time − 500 ms/div

VIN = 5 V , RL = 3 W, TA = 255C

TPS2060, TPS2064 TPS2068, TPS2069

SLVS553K –MARCH 2005– REVISED MAY 2011

PARAMETER MEASUREMENT INFORMATION (continued)

Figure 4. Turnon Delay and Rise Time With 100-μF Figure 5. Turnoff Delay and Fall Time With 100-μF

Load Load

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Figure 6. Short-Circuit Current, Figure 7. Inrush Current With Different

Device Enabled Into Short Load Capacitance

O( )OCx

2V/div

O(OUT)

1 A/div

t-Time-2ms/div

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

2 3 4 5 6

Turnon Time − ms

VI − Input Voltage − V

CL = 100 mF, RL = 5 W, TA = 255C

1.5

1.6

1.7

1.8

1.9

2 3 4 5 6

CL = 100 mF, RL = 5 W, TA = 255C

Turnoff Time − mS

VI − Input Voltage − V

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TPS2060, TPS2064 TPS2068, TPS2069

SLVS553K –MARCH 2005– REVISED MAY 2011

PARAMETER MEASUREMENT INFORMATION (continued)

Figure 8. 0.6-Ω Load Connected to Enabled Device

TYPICAL CHARACTERISTICS

TURNON TIME TURNOFF TIME

vs vs

INPUT VOLTAGE INPUT VOLTAGE

Figure 9. Figure 10.

0.1

0.2

0.3

0.4

0.5

0.6

2 3 4 5 6

Rise Time − ms

VI − Input Voltage − V

CL = 1 mF, RL = 5 W, TA = 255C

0.05

0.1

0.15

0.2

0.25

2 3 4 5 6

CL = 1 mF, RL = 5 W, TA = 255C

Fall Time − ms

VI − Input Voltage − V

−50 0 50 100 150

VI = 5.5 V

VI = 5 V

VI = 3.3 V

VI = 2.7 V

TJ − Junction Temperature − 5C

− Supply Current, Output Enabled −

I (IN)

Aµ

-50

0 50 100 150

T -JunctionTemperature- CJ°

I -SupplyCurrent,OutputEnabled- A

I(IN)

V =5.5V

V =3.3V

V =2.7V

V =5V

TPS2060, TPS2064 TPS2068, TPS2069

SLVS553K –MARCH 2005– REVISED MAY 2011

TYPICAL CHARACTERISTICS (continued)

RISE TIME FALL TIME

vs vs

INPUT VOLTAGE INPUT VOLTAGE

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Figure 11. Figure 12.

TPS2060, TPS2064 TPS2068, TPS2069

SUPPLY CURRENT, OUTPUT ENABLED SUPPLY CURRENT, OUTPUT ENABLED

JUNCTION TEMPERATURE JUNCTION TEMPERATURE

Figure 13. Figure 14.

vs vs

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

−50 0 50 100 150

VI = 5.5 V

VI = 5 V

VI = 3.3 V

VI = 2.7 V

TJ − Junction Temperature − 5C

− Supply Current, Output Disabled −

I (IN)

Aµ

100

120

−50 0 50 100 150

Out1 = 5 V

Out1 = 3.3 V

Out1 = 2.7 V

IO = 0.5 A

TJ − Junction Temperature − 5C

DS(on) − Static Drain-Source

On-State Resistance − mΩ

2.1

2.14

2.18

2.22

2.26

2.3

−50 0 50 100 150

UVLO Rising

UVLO Falling

UVOL − Undervoltage Lockout − V

TJ − Junction Temperature − 5C

1.6

1.7

1.8

1.9

2.2

2.3

2.4

2.5

2.6

-50

0 50 100 150

2.1

T -JunctionTemperature- CJ°

I -Short-CircuitCurrentLimit- A

V =2.7V

V =3.3V

V =5V

V =5.5V

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TPS2060, TPS2064 TPS2068, TPS2069

SLVS553K –MARCH 2005– REVISED MAY 2011

TYPICAL CHARACTERISTICS (continued)

SUPPLY CURRENT, OUTPUT DISABLED STATIC DRAIN-SOURCE ON-STATE RESISTANCE

vs vs

JUNCTION TEMPERATURE JUNCTION TEMPERATURE

Figure 15. Figure 16.

SHORT-CIRCUIT OUTPUT CURRENT UNDERVOLTAGE LOCKOUT

JUNCTION TEMPERATURE JUNCTION TEMPERATURE

Figure 17. Figure 18.

vs vs

100

150

200

0 2.5

5 7.5

Current-LimitResponse- sm

PeakCurrent- A

VI=5V, T

°=25 C

TPS2060, TPS2064 TPS2068, TPS2069

SLVS553K –MARCH 2005– REVISED MAY 2011

TYPICAL CHARACTERISTICS (continued)

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CURRENT-LIMIT RESPONSE

PEAK CURRENT

Figure 19.

OC1 EN1 OC2

0.1 µF 22 µF

Load

OUT1

OUT2

Power Supply

2.7 V to 5.5 V

EN2

GND

0.1 µF

TPS2060

TPS2060, TPS2064 TPS2068, TPS2069

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APPLICATION INFORMATION

POWER-SUPPLY CONSIDERATIONS

Figure 20. Typical Application

A 0.01-μF to 0.1-μF ceramic bypass capacitor between IN and GND, close to the device, is recommended. Placing a high-value electrolytic capacitor on the output pin(s) is recommended when the output load is heavy. This precaution reduces power-supply transients that may cause ringing on the input. Additionally, bypassing the output with a 0.01-μF to 0.1-μF ceramic capacitor improves the immunity of the device to short-circuit transients.

SLVS553K –MARCH 2005– REVISED MAY 2011

OVERCURRENT

A sense FET is employed to check for overcurrent conditions. Unlike current-sense resistors, sense FETs do not increase the series resistance of the current path. When an overcurrent condition is detected, the device maintains a constant output current and reduces the output voltage accordingly. Complete shutdown occurs only if the fault is present long enough to activate thermal limiting.

Three possible overload conditions can occur. In the first condition, the output has been shorted before the device is enabled or before V

has been applied (see Figure 6). The TPS206x senses the short and

I(IN)

immediately switches into a constant-current output. In the second condition, a short or an overload occurs while the device is enabled. At the instant the overload

occurs, high currents may flow for a short period of time before the current-limit circuit can react (see Figure 8). After the current-limit circuit has tripped (reached the overcurrent trip threshold), the device switches into constant-current mode.

In the third condition, the load has been gradually increased beyond the recommended operating current. The current is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device is exceeded. The TPS206x is capable of delivering current up to the current-limit threshold without damaging the device. Once the threshold has been reached, the device switches into its constant-current mode.

OC RESPONSE

The OCx open-drain output is asserted (active low) when an overcurrent or overtemperature shutdown condition is encountered after a 10-ms deglitch timeout. The output remains asserted until the overcurrent or overtemperature condition is removed. Connecting a heavy capacitive load to an enabled device can cause a momentary overcurrent condition; however, no false reporting on OCx occurs due to the 10-ms deglitch circuit. The TPS206x is designed to eliminate false overcurrent reporting. The internal overcurrent deglitch eliminates the need for external components to remove unwanted pulses. OCx is not deglitched when the switch is turned off due to an overtemperature shutdown.

GND IN EN1

EN2

OC1

OC2

OUT1 OUT2

TPS2060

pullup

V+

TPS2060, TPS2064 TPS2068, TPS2069

SLVS553K –MARCH 2005– REVISED MAY 2011

Figure 21. Typical Circuit for the OC Pin

POWER DISSIPATION AND JUNCTION TEMPERATURE

The low on-resistance on the N-channel MOSFET allows the small surface-mount packages to pass large currents. The thermal resistance of these packages are high compared to those of power packages; it is good design practice to check power dissipation and junction temperature. Begin by determining the r N-channel MOSFET relative to the input voltage and operating temperature. As an initial estimate, use the highest operating ambient temperature of interest and read r dissipation per switch can be calculated by:

PD= r

DS(on)

× I

Multiply this number by the number of switches being used. This step renders the total power dissipation from the N-channel MOSFETs.

Finally, calculate the junction temperature:

TJ= PD× R

θJA

+ T

Where:

TA= Ambient temperature °C R

= Thermal resistance

θJA

PD= Total power dissipation based on number of switches being used.

Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees, repeat the calculation, using the calculated value as the new estimate. Two or three iterations are generally sufficient to get a reasonable answer.

from Figure 16. Using this value, the power

DS(on)

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DS(on)

of the

THERMAL PROTECTION

Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present for extended periods of time. The TPS206x implements a thermal sensing to monitor the operating junction temperature of the power distribution switch. In an overcurrent or short-circuit condition, the junction temperature rises due to excessive power dissipation. Once the die temperature rises to approximately 140°C due to overcurrent conditions, the internal thermal sense circuitry turns the power switch off, thus preventing the power switch from damage. Hysteresis is built into the thermal sense circuit, and after the device has cooled approximately 10°C, the switch turns back on. The switch continues to cycle in this manner until the load fault or input power is removed. The OCx open-drain output is asserted (active low) when an overtemperature shutdown or overcurrent occurs.

UNDERVOLTAGE LOCKOUT (UVLO)

An undervoltage lockout ensures that the power switch is in the off state at power up. Whenever the input voltage falls below approximately 2 V, the power switch is quickly turned off. This facilitates the design of hot-insertion systems where it is not possible to turn off the power switch before input power is removed. The UVLO also keeps the switch from being turned on until the power supply has reached at least 2 V, even if the switch is enabled. On reinsertion, the power switch is turned on, with a controlled rise time to reduce EMI and voltage overshoots.

TPS2060, TPS2064 TPS2068, TPS2069

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UNIVERSAL SERIAL BUS (USB) APPLICATIONS

The universal serial bus (USB) interface is a 12-Mb/s, or 1.5-Mb/s, multiplexed serial bus designed for lowto-medium bandwidth PC peripherals (e.g., keyboards, printers, scanners, and mice). The four-wire USB interface is conceived for dynamic attach-detach (hot plug-unplug) of peripherals. Two lines are provided for differential data, and two lines are provided for 5-V power distribution.

USB data is a 3.3-V level signal, but power is distributed at 5 V to allow for voltage drops in cases where power is distributed through more than one hub across long cables. Each function must provide its own regulated 3.3 V from the 5-V input or its own internal power supply.

The USB specification defines the following five classes of devices, each differentiated by power-consumption requirements:

• Hosts/self-powered hubs (SPH)

• Bus-powered hubs (BPH)

• Low-power, bus-powered functions

• High-power, bus-powered functions

• Self-powered functions

SPHs and BPHs distribute data and power to downstream functions. The TPS206x has higher current capability than required by one USB port; so, it can be used on the host side and supplies power to multiple downstream ports or functions.

SLVS553K –MARCH 2005– REVISED MAY 2011

HOST/SELF-POWERED AND BUS-POWERED HUBS

Hosts and SPHs have a local power supply that powers the embedded functions and the downstream ports (see

Figure 22). This power supply must provide from 5.25 V to 4.75 V to the board side of the downstream

connection under full-load and no-load conditions. Hosts and SPHs are required to have current-limit protection and must report overcurrent conditions to the USB controller. Typical SPHs are desktop PCs, monitors, printers, and stand-alone hubs.

OC1 EN1 OC2 EN2

GND

0.1 µF

8 3

5 4

22 µF

GND

OUT1

TPS2060

Power Supply

D+ D−

BUS

GND

D+ D−

BUS

Downstream

USB Ports

USB

Controller

3.3 V

5 V

2 µF

GND

OUT2

D+ D−

BUS

22 µF

GND

D+ D−

BUS

0.1 µF

22 µF

GND

D+ D−

BUS

0.1 µF

22 µF

GND

D+ D−

BUS

0.1 µF

TPS2060, TPS2064 TPS2068, TPS2069

SLVS553K –MARCH 2005– REVISED MAY 2011

www.ti.com

BPHs obtain all power from upstream ports and often contain an embedded function. The hubs are required to power up with less than one unit load. The BPH usually has one embedded function, and power is always available to the controller of the hub. If the embedded function and hub require more than 100 mA on power up,

Figure 22. Typical Six-Port USB Host/Self-Powered Hub

the power to the embedded function may need to be kept off until enumeration is completed. This can be accomplished by removing power or by shutting off the clock to the embedded function. Power switching the embedded function is not necessary if the aggregate power draw for the function and controller is less than one unit load. The total current drawn by the bus-powered device is the sum of the current to the controller, the embedded function, and the downstream ports, and it is limited to 500 mA from an upstream port.

OC1

OC2

8 3

5 4

0.1 µF 10 µF

Internal

Function

OUT1

Power Supply

3.3 V

EN1

0.1 µF 10 µF

OUT2

Internal

Function

0.1 µF

10 µF

USB

Control

GND

BUS

D−

D+

TPS2060

EN2

GND 1

TPS2060, TPS2064 TPS2068, TPS2069

www.ti.com

LOW-POWER BUS-POWERED AND HIGH-POWER BUS-POWERED FUNCTIONS

Both low-power and high-power bus-powered functions obtain all power from upstream ports; low-power functions always draw less than 100 mA; high-power functions must draw less than 100 mA at power up and can draw up to 500 mA after enumeration. If the load of the function is more than the parallel combination of 44 Ω and 10 μF at power up, the device must implement inrush current limiting (see Figure 23). With TPS206x, the internal functions could draw more than 500 mA, which fits the needs of some applications such as motor driving circuits.

SLVS553K –MARCH 2005– REVISED MAY 2011

Figure 23. High-Power Bus-Powered Function

USB POWER-DISTRIBUTION REQUIREMENTS

USB can be implemented in several ways, and, regardless of the type of USB device being developed, several power-distribution features must be implemented.

• Hosts/SPHs must: – Current-limit downstream ports – Report overcurrent conditions on USB V

• BPHs must: – Enable/disable power to downstream ports – Power up at <100 mA – Limit inrush current (<44 Ω and 10 μF)

• Functions must: – Limit inrush currents – Power up at <100 mA

The feature set of the TPS206x allows them to meet each of these requirements. The integrated current-limiting and overcurrent reporting is required by hosts and self-powered hubs. The logic-level enable and controlled rise times meet the need of both input and output ports on bus-powered hubs, as well as the input ports for bus-powered functions (see Figure 24).

BUS

DP1

DM1

DP2

DM2

DP3

DM3

DP4

PWRON1

OVRCUR1

PWRON2

OVRCUR2

DM4

DP0 DM0

XTAL1

XTAL2

OCSOFF

SN75240

D + D −

5 V

GND

D + D −

5 V

D + D −

5 V

D + D −

5 V

48-MHz Crystal

Downstream

Ports

TUSB2040

Hub Controller

Tuning Circuit

ABC

33 µF

†

SN75240

ABC

GND

33 µF

†

33 µF

†

33 µF

†

D +

D −

Upstream Port

TPS2041B

SN75240

5 V

GND

C D

1 µF

GND

Ferrite Beads

BUSPWR GANGED

Tie to TPS2041 EN

Input

OC EN

OUT

5-V Power

Supply

GND

3.3 V

4.7 µF

0.1 µF

4.7 µF

EN1

OC1

OUT1

TPS2060

EN2 OC2

OUT2

0.1 µF

GND

†

USB rev 1.1 requires 120 µF per hub.

TPS76333

TPS2060, TPS2064 TPS2068, TPS2069

SLVS553K –MARCH 2005– REVISED MAY 2011

www.ti.com

GENERIC HOT-PLUG APPLICATIONS

Figure 24. Hybrid Self / Bus-Powered Hub Implementation

In many applications it may be necessary to remove modules or pc boards while the main unit is still operating. These are considered hot-plug applications. Such implementations require the control of current surges seen by the main power supply and the card being inserted. The most effective way to control these surges is to limit and slowly ramp the current and voltage being applied to the card, similar to the way in which a power supply normally turns on. Due to the controlled rise times and fall times of the TPS206x, these devices can be used to provide a softer start-up to devices being hot-plugged into a powered system. The UVLO feature of the TPS206x also ensures that the switch is off after the card has been removed, and that the switch is off during the next insertion. The UVLO feature insures a soft start with a controlled rise time for every insertion of the card or module.

Power

Supply

0.1 µF

1000 µF Optimum

2.7 V to 5.5 V

PC Board

Overcurrent Response

TPS2060

OC1

GND

EN1

EN2

OUT1

OUT2

OC2

Block of Circuitry

TPS2060, TPS2064 TPS2068, TPS2069

www.ti.com

Figure 25. Typical Hot-Plug Implementation

By placing the TPS206x between the VCCinput and the rest of the circuitry, the input power reaches these devices first after insertion. The typical rise time of the switch is approximately 1 ms, providing a slow voltage ramp at the output of the device. This implementation controls system surge currents and provides a hot-plugging mechanism for any device.

DETAILED DESCRIPTION

SLVS553K –MARCH 2005– REVISED MAY 2011

Power Switch

The power switch is an N-channel MOSFET with a low on-state resistance. Configured as a high-side switch, the power switch prevents current flow from OUT to IN and IN to OUT when disabled. The power switch supplies a minimum current of 1.5 A.

Charge Pump

An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate of the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requires little supply current.

Driver

The driver controls the gate voltage of the power switch. To limit large current surges and reduce the associated electromagnetic interference (EMI) produced, the driver incorporates circuitry that controls the rise times and fall times of the output voltage.

Enable (ENx)

The logic enable disables the power switch and the bias for the charge pump, driver, and other circuitry to reduce the supply current. The supply current is reduced to less than 1 μA when a logic high is present on ENx, or when a logic low is present on ENx. A logic zero input on ENx, or a logic high input on ENx restores bias to the drive and control circuits and turns the switch on. The enable input is compatible with both TTL and CMOS logic levels.

Overcurrent (OCx)

The OCx open-drain output is asserted (active low) when an overcurrent or overtemperature condition is encountered. The output remains asserted until the overcurrent or overtemperature condition is removed. A 10-ms deglitch circuit prevents the OCx signal from oscillation or false triggering. If an overtemperature shutdown occurs, the OCx is asserted instantaneously.

TPS2060, TPS2064 TPS2068, TPS2069

SLVS553K –MARCH 2005– REVISED MAY 2011

Current Sense

A sense FET monitors the current supplied to the load. The sense FET measures current more efficiently than conventional resistance methods. When an overload or short circuit is encountered, the current-sense circuitry sends a control signal to the driver. The driver in turn reduces the gate voltage and drives the power FET into its saturation region, which switches the output into a constant-current mode and holds the current constant while varying the voltage on the load.

Thermal Sense

The TPS206x implements a thermal sensing to monitor the operating temperature of the power distribution switch. In an overcurrent or short-circuit condition the junction temperature rises. When the die temperature rises to approximately 140°C due to overcurrent conditions, the internal thermal sense circuitry turns off the switch, thus preventing the device from damage. Hysteresis is built into the thermal sense, and after the device has cooled approximately 10 degrees, the switch turns back on. The switch continues to cycle off and on until the fault is removed. The open-drain false reporting output (OCx) is asserted (active low) when an overtemperature shutdown or overcurrent occurs.

Undervoltage Lockout

A voltage sense circuit monitors the input voltage. When the input voltage is below approximately 2 V, a control signal turns off the power switch.

www.ti.com

PACKAGE OPTION ADDENDUM

www.ti.com

PACKAGING INFORMATION

Orderable Device Status

(1)

TPS2060DGN ACTIVE MSOP-

TPS2060DGNR ACTIVE MSOP-

TPS2060DRBR ACTIVE SON DRB 8 3000 Green (RoHS

TPS2060DRBT ACTIVE SON DRB 8 250 Green (RoHS

TPS2064DGN ACTIVE MSOP-

TPS2064DGNG4 ACTIVE MSOP-

TPS2064DGNR ACTIVE MSOP-

TPS2064DGNRG4 ACTIVE MSOP-

TPS2064DRBR ACTIVE SON DRB 8 3000 Green (RoHS

TPS2064DRBT ACTIVE SON DRB 8 250 Green (RoHS

TPS2068D ACTIVE SOIC D 8 75 Green (RoHS

TPS2068DG4 ACTIVE SOIC D 8 75 Green (RoHS

TPS2068DGN ACTIVE MSOP-

TPS2068DGNG4 ACTIVE MSOP-

TPS2068DGNR ACTIVE MSOP-

TPS2068DGNRG4 ACTIVE MSOP-

TPS2068DR ACTIVE SOIC D 8 2500 Green (RoHS

Package Type Package

Drawing

DGN 8 80 Green (RoHS

PowerPAD

DGN 8 2500 Green (RoHS

PowerPAD

DGN 8 80 Green (RoHS

PowerPAD

DGN 8 80 Green (RoHS

PowerPAD

DGN 8 2500 Green (RoHS

PowerPAD

DGN 8 2500 Green (RoHS

PowerPAD

DGN 8 80 Green (RoHS

PowerPAD

DGN 8 80 Green (RoHS

PowerPAD

DGN 8 2500 Green (RoHS

PowerPAD

DGN 8 2500 Green (RoHS

PowerPAD

Pins Package

Qty

Eco Plan

(2)

& no Sb/Br)

Lead/Ball Finish

(6)

CU NIPDAU |

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

Level-1-260C-UNLIM 0 to 70 2060

CU NIPDAUAG

CU NIPDAU |

Level-1-260C-UNLIM 0 to 70 2060

CU NIPDAUAG

CU NIPDAU Level-1-260C-UNLIM 0 to 70 2060

CU NIPDAU |

Level-1-260C-UNLIM 0 to 70 2064

CU NIPDAUAG

CU NIPDAU Level-1-260C-UNLIM 0 to 70 2064

CU NIPDAU |

Level-1-260C-UNLIM 0 to 70 2064

CU NIPDAUAG

CU NIPDAU Level-1-260C-UNLIM 0 to 70 2064

CU NIPDAU Level-2-260C-1 YEAR 0 to 70 2068

CU NIPDAU |

Level-1-260C-UNLIM -40 to 85 2068

CU NIPDAUAG

CU NIPDAU Level-1-260C-UNLIM -40 to 85 2068

CU NIPDAU |

Level-1-260C-UNLIM -40 to 85 2068

CU NIPDAUAG

CU NIPDAU Level-1-260C-UNLIM -40 to 85 2068

CU NIPDAU Level-2-260C-1 YEAR 0 to 70 2068

10-Jun-2014

Samples

(4/5)

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

Orderable Device Status

TPS2069DGN ACTIVE MSOP-

TPS2069DGNG4 ACTIVE MSOP-

TPS2069DGNR ACTIVE MSOP-

TPS2069DGNRG4 ACTIVE MSOP-

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

Package Type Package

(1)

PowerPAD

Drawing

DGN 8 80 Green (RoHS

DGN 8 2500 Green (RoHS

Pins Package

Qty

Eco Plan

(2)

& no Sb/Br)

Lead/Ball Finish

(6)

CU NIPDAU |

CU NIPDAUAG

CU NIPDAU Level-1-260C-UNLIM -40 to 85 2069

CU NIPDAU |

CU NIPDAUAG

CU NIPDAU Level-1-260C-UNLIM -40 to 85 2069

MSL Peak Temp

(3)

Level-1-260C-UNLIM -40 to 85 2069

Op Temp (°C) Device Marking

10-Jun-2014

(4/5)

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Samples

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

10-Jun-2014

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TPS2068 :

Automotive: TPS2068-Q1

•

NOTE: Qualified Version Definitions:

Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

•

Addendum-Page 3

PACKAGE MATERIALS INFORMATION

www.ti.com 16-Aug-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

TPS2060DGNR MSOP-

Power

TPS2060DRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2 TPS2060DRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2 TPS2064DGNR MSOP-

Power

TPS2064DGNR MSOP-

Power

TPS2064DRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2 TPS2064DRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2 TPS2068DGNR MSOP-

Power

TPS2068DGNR MSOP-

Power

TPS2068DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

TPS2069DGNR MSOP- DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

Type

PAD

Package

Drawing

DGN 8 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1

DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

DGN 8 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm)B0(mm)K0(mm)P1(mm)W(mm)

Pin1

Quadrant

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com 16-Aug-2013

Device Package

Type

Power

PAD

TPS2069DGNR MSOP-

Power

PAD

Package

Drawing

DGN 8 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm)B0(mm)K0(mm)P1(mm)W(mm)

Pin1

Quadrant

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TPS2060DGNR MSOP-PowerPAD DGN 8 2500 346.0 346.0 35.0 TPS2060DRBR SON DRB 8 3000 346.0 346.0 35.0

TPS2060DRBT SON DRB 8 250 203.0 203.0 35.0 TPS2064DGNR MSOP-PowerPAD DGN 8 2500 346.0 346.0 35.0 TPS2064DGNR MSOP-PowerPAD DGN 8 2500 364.0 364.0 27.0 TPS2064DRBR SON DRB 8 3000 346.0 346.0 35.0

TPS2064DRBT SON DRB 8 250 203.0 203.0 35.0 TPS2068DGNR MSOP-PowerPAD DGN 8 2500 364.0 364.0 27.0 TPS2068DGNR MSOP-PowerPAD DGN 8 2500 346.0 346.0 35.0

TPS2068DR SOIC D 8 2500 533.4 186.0 36.0 TPS2069DGNR MSOP-PowerPAD DGN 8 2500 364.0 364.0 27.0 TPS2069DGNR MSOP-PowerPAD DGN 8 2500 346.0 346.0 35.0

Pack Materials-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed.

TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards.

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

Texas Instruments TPS2060DGN, TPS2060DRBR, TPS2064DGN, TPS2064DRBR, TPS2068D Schematic [ru]

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

DESCRIPTION

ABSOLUTE MAXIMUM RATINGS

DISSIPATING RATING TABLE

RECOMMENDED OPERATING CONDITIONS

ELECTRICAL CHARACTERISTICS

DEVICE INFORMATION

DEVICE INFORMATION

PARAMETER MEASUREMENT INFORMATION

TYPICAL CHARACTERISTICS

APPLICATION INFORMATION

POWER-SUPPLY CONSIDERATIONS

OVERCURRENT

OC RESPONSE

POWER DISSIPATION AND JUNCTION TEMPERATURE

THERMAL PROTECTION

UNDERVOLTAGE LOCKOUT (UVLO)

UNIVERSAL SERIAL BUS (USB) APPLICATIONS

HOST/SELF-POWERED AND BUS-POWERED HUBS

LOW-POWER BUS-POWERED AND HIGH-POWER BUS-POWERED FUNCTIONS

USB POWER-DISTRIBUTION REQUIREMENTS

GENERIC HOT-PLUG APPLICATIONS

DETAILED DESCRIPTION

Power Switch

Charge Pump

Driver

Enable (ENx)

Overcurrent (OCx)

Current Sense

Thermal Sense

Undervoltage Lockout