TEXAS INSTRUMENTS TPS2043, TPS2053 Technical data

TPS2043, TPS2053

TRIPLE POWER-DISTRIBUTION SWITCHES

SLVS191 – JANUARY 1999

IN1
EN1
EN2

IN2
EN3

NC

IN1
EN1
EN2

IN2
EN3

NC

TPS2043

D PACKAGE

(TOP VIEW)

1

16

2

15

3

14

4

13

5

12

6

11

7

10

8

D PACKAGE

(TOP VIEW)

TPS2053

1
2
3
4
5
6
7
8

9

16
15
14
13
12
11
10

9

OC1
OUT1
OUT2
OC2
OC3
OUT3
NC
NC

OC1
OUT1
OUT2
OC2
OC3
OUT3
NC
NC

D

135-mΩ -Maximum (5-V Input) High-Side
MOSFET Switch

D

500 mA Continuous Current per Channel

D

Short-Circuit and Thermal Protection With
Overcurrent Logic Output

D

Operating Range...2.7 V to 5.5 V

D

Logic-Level Enable Input

D

2.5-ms Typical Rise Time

D

Undervoltage Lockout

D

20 µA Maximum Standby Supply Current

D

Bidirectional Switch

D

Available in 16-pin SOIC Package

D

Ambient Temperature Range, –40°C to 85°C

D

2-kV Human-Body-Model, 200-V
Machine-Model ESD Protection

D

UL Listed – File No. E169910

description

The TPS2043 and TPS2053 triple power
distribution switches are intended for applications

GND1

GND2

GND1

GND2

where heavy capacitive loads and short circuits
are likely to be encountered. The TPS2043 and

NC – No internal connection

the TPS2053 incorporate in single packages three 135-mΩ N-channel MOSFET high-side power switches for
power-distribution systems that require multiple power switches. Each switch is controlled by a logic enable that
is compatible with 5-V logic and 3-V logic. Gate drive is provided by an internal charge pump that controls the
power-switch rise times and fall times to minimize current surges during switching. The charge pump, requiring
no external components, allows operation from supplies as low as 2.7 V.

When the output load exceeds the current-limit threshold or a short is present, the TPS2043 and TPS2053 limit
the output current to a safe level by switching into a constant-current mode, pulling the overcurrent (OCx
output low. When continuous heavy overloads and short circuits increase the power dissipation in the switch
causing the junction temperature to rise, a thermal protection circuit shuts off the switch to prevent damage.
Recovery from a thermal shutdown is automatic once the device has cooled sufficiently. Internal circuitry
ensures the switch remains off until valid input voltage is present.

The TPS2043 and TPS2053 are designed to limit at 0.9-A load. These power distribution switches are available
in a 16-pin small-outline integrated circuit (SOIC) package and operate over an ambient temperature range of
–40°C to 85°C.

AVAILABLE OPTIONS

RECOMMENDED MAXIMUM TYPICAL SHORT-CIRCUIT

T

A

–40°C to 85°C Active low 0.5 0.9 TPS2043D
–40°C to 85°C Active high 0.5 0.9 TPS2053D

†

The D package is available taped and reeled. Add an R suffix to device type (e.g., TPS2043DR)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

ENABLE

CONTINUOUS LOAD CURRENT

(A)

CURRENT LIMIT AT 25°C

(A)

Copyright  1999, Texas Instruments Incorporated

PACKAGED DEVICES

SOIC

†

(D)

) logic

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1

TPS2043, TPS2053
TRIPLE POWER-DISTRIBUTION SWITCHES

SLVS191 – JANUARY 1999

TPS2043 functional block diagram

OC1

GND1

EN1

IN1

EN2

Charge

Pump

Charge

Pump

UVLO

Thermal

Sense

Driver

Driver

Thermal

Sense

Current

Limit

CS

Power Switch

CS

Current

Limit

†

OUT1

†

OUT2

OC2

OC3

GND2

EN3

IN2

†

Current sense

Charge

Pump

UVLO

Thermal

Sense

Driver

Current

Limit

CS

Power Switch

†

OUT3

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

NAME

TRIPLE POWER-DISTRIBUTION SWITCHES

Terminal Functions

TERMINAL

NO.

TPS2043 TPS2053

EN1 3 – I Enable input, logic low turns on power switch, IN1-OUT1.
EN2 4 – I Enable input, logic low turns on power switch, IN1-OUT2.
EN3 7 – I Enable input, logic low turns on power switch, IN2-OUT3.
EN1 – 3 I Enable input, logic high turns on power switch, IN1-OUT1.
EN2 – 4 I Enable input, logic high turns on power switch, IN1-OUT2.
EN3 – 7 I Enable input, logic high turns on power switch, IN2-OUT3.
GND1 1 1 Ground
GND2 5 5 Ground
IN1 2 2 I Input voltage
IN2 6 6 I Input voltage
NC 8, 9, 10 8, 9, 10 No connection
OC1 16 16 O Overcurrent, logic output active low, IN1-OUT1
OC2 13 13 O Overcurrent, logic output active low, IN1-OUT2
OC3 12 12 O Overcurrent, logic output active low, IN2-OUT3
OUT1 15 15 O Power-switch output, IN1-OUT1
OUT2 14 14 O Power-switch output, IN1-OUT2
OUT3 11 11 O Power-switch output, IN2-OUT3

I/O DESCRIPTION

TPS2043, TPS2053

SLVS191 – JANUARY 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

TPS2043, TPS2053
TRIPLE POWER-DISTRIBUTION SWITCHES

SLVS191 – JANUARY 1999

detailed description

power switch

The power switch is an N-channel MOSFET with a maximum on-state resistance of 135 mΩ (V
Configured as a high-side switch, the power switch prevents current flow from OUTx to INx and INx to OUTx
when disabled. The power switch supplies a minimum of 500 mA per switch.

charge pump

An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate
of the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requires
very little supply current.

driver

The driver controls the gate voltage of the power switch. T o limit large current surges and reduce the associated
electromagnetic interference (EMI) produced, the driver incorporates circuitry that controls the rise times and
fall times of the output voltage. The rise and fall times are typically in the 2-ms to 4-ms range.

enable (ENx

The logic enable disables the power switch and the bias for the charge pump, driver, and other circuitry to reduce
the supply current to less than 20 µA when a logic high is present on ENx
on ENx (TPS2053). A logic zero input on ENx
and turns the power on. The enable input is compatible with both TTL and CMOS logic levels.

overcurrent (OCx

The OCx
encountered. The output will remain asserted until the overcurrent or overtemperature condition is removed.

current sense

or ENx)

(TPS2043) or a logic low is present

or logic high on ENx restores bias to the drive and control circuits

)

open-drain output is asserted (active low) when an overcurrent or overtemperature condition is

I(INx)

= 5 V).

A sense FET monitors the current supplied to the load. The sense FET measures current more efficiently than
conventional resistance methods. When an overload or short circuit is encountered, the current-sense circuitry
sends a control signal to the driver. The driver in turn reduces the gate voltage and drives the power FET into
its saturation region, which switches the output into a constant current mode and holds the current constant
while varying the voltage on the load.

thermal sense

The TPS2043 and TPS2053 implement a dual-threshold thermal trip to allow fully independent operation of the
power distribution switches. In an overcurrent or short-circuit condition the junction temperature rises. When
the die temperature rises to approximately 140°C, the internal thermal sense circuitry checks to determine which
power switch is in an overcurrent condition and turns off that switch, thus isolating the fault without interrupting
operation of the adjacent power switch. Hysteresis is built into the thermal sense, and after the device has cooled
approximately 20 degrees, the switch turns back on. The switch continues to cycle off and on until the fault is
removed. The (OCx

undervoltage lockout

A voltage sense circuit monitors the input voltage. When the input voltage is below approximately 2 V , a control
signal turns off the power switch.

) open-drain output is asserted (active low) when overtemperature or overcurrent occurs.

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

UNIT

TPS2043, TPS2053

TRIPLE POWER-DISTRIBUTION SWITCHES

SLVS191 – JANUARY 1999

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Input voltage range, V
Output voltage range, V
Input voltage range, V
Continuous output current, I

Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating virtual junction temperature range, T
Storage temperature range, T

Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . .

Electrostatic discharge (ESD) protection: Human body model MIL-STD-883C 2 kV. . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltages are with respect to GND.

PACKAGE

D 725 mW 5.8 mW/°C 464 mW 377 mW

(see Note1) –0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I(INx)

O(OUTx)

I(ENx)

(see Note1) –0.3 V to V

or V

I(ENx)

O(OUTx)

J

stg

Machine model 0.2 kV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DISSIPATION RATING TABLE

TA ≤ 25°C

POWER RATING

DERATING FACTOR

ABOVE TA = 25°C

TA = 70°C

POWER RATING

TA = 85°C

POWER RATING

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I(INx)

–0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Internally limited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

recommended operating conditions

TPS2043 TPS2053

MIN MAX MIN MAX

Input voltage, V
Input voltage, V
Continuous output current, I
Operating virtual junction temperature, T

I(INx)
I(ENx)

or V

I(ENx)

O(OUTx)

J

2.7 5.5 2.7 5.5 V
0 5.5 0 5.5 V
0 500 0 500 mA

–40 125 –40 125 °C

†

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5

TPS2043, TPS2053

PARAMETER

TEST CONDITIONS

†

UNIT

r

trRise time, output

ms

tfFall time, output

ms

PARAMETER

TEST CONDITIONS

UNIT

VILLow-level input voltage

IIInput current

A

PARAMETER

TEST CONDITIONS

†

UNIT

TRIPLE POWER-DISTRIBUTION SWITCHES

SLVS191 – JANUARY 1999

electrical characteristics over recommended operating junction temperature range, V
I

= rated current, V

O

I(ENx)

= 0 V, V

= Hi (unless otherwise noted)

I(ENx)

I(IN)

= 5.5 V,

power switch

TPS2043 TPS2053

MIN TYP MAX MIN TYP MAX

V

= 5 V,

I(INx)

IO = 0.5 A

Static drain-source on-state
resistance, 5-V operation

DS(on)

Static drain-source on-state
resistance, 3.3-V operation

p

p

†

Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.

V

= 5 V,

I(INx)

IO = 0.5 A
V

= 5 V,

I(INx)

IO = 0.5 A
V

= 3.3 V,

I(INx)

IO = 0.5 A
V

= 3.3 V,

I(INx)

IO = 0.5 A
V

= 3.3 V,

I(INx)

IO = 0.5 A
V

= 5.5 V,

I(INx)

CL = 1 µF,
V

= 2.7 V,

I(INx)

CL = 1 µF,
V

= 5.5 V,

I(INx)

CL = 1 µF,
V

= 2.7 V,

I(INx)

CL = 1 µF,

TJ = 25°C,

TJ = 85°C,

TJ = 125°C,

TJ = 25°C,

TJ = 85°C,

TJ = 125°C,

TJ = 25°C,
RL = 10 Ω

TJ = 25°C,
RL = 10 Ω

TJ = 25°C,
RL = 10 Ω

TJ = 25°C,
RL = 10 Ω

80 95 80 95

90 120 90 120

100 135 100 135

85 105 85 105

100 135 100 135

115 150 115 150

2.5 2.5

3 3

4.4 4.4

2.5 2.5

mΩ

enable input ENx or ENx

TPS2043 TPS2053

MIN TYP MAX MIN TYP MAX

V

High-level input voltage 2.7 V ≤ V

IH

p

p

t

Turnon time CL = 100 µF, RL=10 Ω 20 20 ms

on

t

Turnoff time CL = 100 µF, RL=10 Ω 40 40

off

TPS2043 V
TPS2053 V

4.5 V ≤ V

2.7 V≤ V
I(ENx

I(ENx)

≤ 5.5 V 2 2 V

I(INx)

≤ 5.5 V 0.8 0.8 V

I(INx)

≤ 4.5 V 0.4 0.4

I(INx)

= 0 V or V

)

= V

I(INx)

I(ENx)

or V

= V

I(IN)

= 0 V –0.5 0.5

I(ENx)

–0.5 0.5

µ

current limit

TPS2043 TPS2053

MIN TYP MAX MIN TYP MAX

V

= 5 V, OUT connected to GND,

I

Short-circuit output current

OS

†

Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.

I(INx)

Device enable into short circuit

0.7 0.9 1.1 0.7 0.9 1.1 A

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER

TEST CONDITIONS

UNIT

Su ly

TPS2043

,

A

V

V

TPS2053

Su ly

V

V

TPS2043

,

A

V

V

TPS2053

g

d

A

leak

g

T

25°C

A

PARAMETER

TEST CONDITIONS

UNIT

PARAMETER

TEST CONDITIONS

UNIT

TPS2043, TPS2053

TRIPLE POWER-DISTRIBUTION SWITCHES

SLVS191 – JANUARY 1999

electrical characteristics over recommended operating junction temperature range, V
I

= rated current, V

O

I(ENx)

= 0 V, V

= Hi (unless otherwise noted) (continued)

I(ENx)

I(IN)

= 5.5 V,

supply current

TPS2043 TPS2053

MIN TYP MAX MIN TYP MAX

pp
current,
low-level
output

pp
current,
high-level
output

Leakage
current

Reverse

age

current

No Load
on OUTx

No Load
on OUTx

OUTx
connecte
to ground

IN = high
impedance

V

= V

I(ENx)

= 0

I(ENx)

= 0

I(ENx)

=

I(ENx)

V

= V

I(ENx)

V

= 0 V –40°C ≤ TJ ≤ 125°C TPS2053 200

I(ENx)

V

= 0 V

I(ENx

)

V

= Hi

I(ENx)

TJ = 25°C

I(INx)

–40°C ≤ TJ ≤ 125°C
TJ = 25°C
–40°C ≤ TJ ≤ 125°C
TJ = 25°C
–40°C ≤ TJ ≤ 125°C
TJ = 25°C

I(INx)

–40°C ≤ TJ ≤ 125°C
–40°C ≤ TJ ≤ 125°C TPS2043 200

I(INx)

°

=

J

TPS2043 0.3
TPS2053 0.3

0.03 2
20

0.03 2
20

160 200
200

160 200
200

undervoltage lockout

TPS2043 TPS2053

MIN TYP MAX MIN TYP MAX

Low-level input voltage 2 2.5 2 2.5 V
Hysteresis TJ = 25°C 100 100 mV

µ

µ

µ

µ

overcurrent OCx

Sink current
Output low voltage IO = 5 mA, V
Off-state current

†

Specified by design, not production tested.

†

†

VO = 5 V 10 10 mA

VO = 5 V, VO = 3.3 V 1 1 µA

OL(OCx)

TPS2043 TPS2053

MIN TYP MAX MIN TYP MAX

0.5 0.5 V

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7

TPS2043, TPS2053
TRIPLE POWER-DISTRIBUTION SWITCHES

SLVS191 – JANUARY 1999

PARAMETER MEASUREMENT INFORMATION

OUTx

V

I(EN)

(5 V/div)

V

I(ENx)

V

O(OUTx)

t

RL CL

V

O(OUTx)

TEST CIRCUIT

50%

t

on

50%

90%

10%

V

I(ENx)

t

off

V

O(OUTx)

VOLTAGE WAVEFORMS

r

90%

90%

10%

50%

t

on

10%

50%

90%

10%

t

f

t

off

Figure 1. Test Circuit and Voltage Waveforms

V

I(EN)

(5 V/div)

V

O(OUT)

(2 V/div)

8

V

= 5 V

I(IN)

TA = 25°C
CL = 0.1 µF

0123456

t – Time – ms

78910

Figure 2. Turnon Delay and Rise Time

with 0.1-µF Load

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

V

O(OUT)

(2 V/div)

V

= 5 V

I(IN)

TA = 25°C
CL = 0.1 µF

0 1000 2000 3000

t – Time – ms

4000 5000

Figure 3. Turnoff Delay and Fall Time

with 0.1-µF Load

V

I(EN)

(5 V/div)

V

O(OUT)

(2 V/div)

PARAMETER MEASUREMENT INFORMATION

0123456

t – Time – ms

V

= 5 V

I(IN)

TA = 25°C
CL = 1 µF
RL = 10 Ω

78910

TPS2043, TPS2053

TRIPLE POWER-DISTRIBUTION SWITCHES

SLVS191 – JANUARY 1999

V

I(EN)

(5 V/div)

V

= 5 V

I(IN)

V

O(OUT)

(2 V/div)

TA = 25°C
CL = 1 µF
RL = 10 Ω

0 2 4 6 8 10 12

t – Time – ms

14 16 18 20

Figure 4. Turnon Delay and Rise Time

with 1-µF Load

V

I(EN)

(5 V/div)

I

O(OUT)

(0.2 A/div)

0123 45 6

t – Time – ms

Figure 6. TPS2043, Short-Circuit Current,

Device Enabled into Short

V

= 5 V

I(IN)

TA = 25°C

78910

V

O(OUT)

(2 V/div)

I

O(OUT)

(0.5 A/div)

Figure 5. Turnoff Delay and Fall Time

with 1-µF Load

V

= 5 V

I(IN)

TA = 25°C

01020 30405060

t – Time – ms

70 80 90 100

Figure 7. TPS2043, Threshold Trip Current

with Ramped Load on Enabled Device

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9

TPS2043, TPS2053
TRIPLE POWER-DISTRIBUTION SWITCHES

SLVS191 – JANUARY 1999

PARAMETER MEASUREMENT INFORMATION

V

= 5 V

I(IN)

TA = 25°C
RL = 10 Ω

V

I(EN)

(5 V/div)

I

O(OUT)

(o.2 A/div)

Figure 8. Inrush Current with 100-µF, 220-µF

470 µF

220 µF

100 µF

0 2 4 6 8 10 12

t – Time – ms

and 470-µF Load Capacitance

14 16 18 20

V

O(OC)

(5 V/div)

I

O(OUT)

(0.5 A/div)

V

= 5 V

I(IN)

Load Ramp,1A/100 ms
TA = 25°C

0 20 40 60 80 100 120

t – Time – ms

140 160 180 200

Figure 9. Ramped Load on Enabled Device

V

= 5 V

I(IN)

TA = 25°C

V

O(OC)

(5 V/div)

I

O(OUT)

(0.5 A/div)

0 400 800 1200 1600 2000

t – Time – µs

Figure 10. 4-Ω Load Connected to Enabled Device

V

O(OC)

(5 V/div)

I

O(OUT)

(1 A/div)

V

= 5 V

I(IN)

TA = 25°C

0 20 40 60 80 100 120 140 160 180 200

t – Time – µs

Figure 11. 1-Ω Load Connected

to Enabled Device

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS2043, TPS2053

TRIPLE POWER-DISTRIBUTION SWITCHES

SLVS191 – JANUARY 1999

TYPICAL CHARACTERISTICS

6

5.5

5

4.5

4

Turn-On Delay – ms

3.5

3

2.5 3 3.5 4 4.5

3

V

= 5 V

I(INx)

CL = 1 µF
TA = 25°C

2.9

TURNON DELAY

vs

INPUT VOLTAGE

VI – Input Voltage – V

Figure 12

RISE TIME

vs

LOAD CURRENT

CL = 1 µF
RL = 10 Ω
TA = 25°C

5 5.5 6

17

CL = 1 µF
RL = 10 Ω

16

TA = 25°C

15

14

13

12

Turn-Off Delay – ms

11

10

3

2.5 3 3.5 4 4.5
VI – Input Voltage – V

3.5
V

= 5 V

I(INx)

TA = 25°C
CL = 1 µF

3.3

TURNOFF DELAY

vs

INPUT VOLTAGE

5 5.5 6

Figure 13

FALL TIME

vs

LOAD CURRENT

2.8

2.7

– Rise Time – ms

t

r

2.6

2.5

0.1 0.2 0.3 0.4 0.5

0.6 0.7 0.8 0.9

IL – Load Current – A

Figure 14

3.1

2.9

– Fall Time – ms

t

f

2.7

2.5

0.1 0.2 0.3 0.4 0.5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

0.6 0.7 0.8 0.9

IL – Load Current – A

Figure 15

11

TPS2043, TPS2053
TRIPLE POWER-DISTRIBUTION SWITCHES

SLVS191 – JANUARY 1999

TYPICAL CHARACTERISTICS

SUPPLY CURRENT, OUTPUT ENABLED

vs

JUNCTION TEMPERATURE

200

Aµ

V

180

160

140

120

– Supply Current, Output Enabled –

I(IN)

I

100

–50 –25 0 25 50

TJ – Junction Temperature – °C

I(INx)

V

I(INx)

= 5 V

V

I(INx)

= 3.3 V

Figure 16

SUPPLY CURRENT, OUTPUT ENABLED

vs

INPUT VOLTAGE

200

Aµ

180

TJ = 85°C

V

= 5.5 V

I(INx)

= 4 V

V

= 2.7 V

I(INx)

75 100 125 150

TJ = 125°C

SUPPLY CURRENT, OUTPUT DISABLED

vs

JUNCTION TEMPERATURE

2000
1800

V

V

I(INx)

V

I(INx)

V

I(INx)

I(INx)

= 4 V

= 2.7 V

1600

1400
1200
1000

800
600

400

– Supply Current, Output Disabled – nA

200

I(IN)

0

I

–200

–50 –25 0 25 50 75

TJ – Junction Temperature – °C

Figure 17

SUPPLY CURRENT, OUTPUT DISABLED

vs

INPUT VOLTAGE

2000

1600

TJ = 125°C

= 5.5 V
= 5 V

100 125 150

160

140

120

– Supply Current, Output Enabled –

I(IN)

I

100

2.5 3 3.5 4

TJ = –40°C

VI – Input Voltage – V

Figure 18

12

TJ = 0°C

4.5

1200

800

TJ = 25°C

400

0

– Supply Current, Output Disabled – nA

I(IN)

I

–400

5 5.5 6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2.5 3 3.5 4 4.5

TJ = 85°C

TJ = –40°C

VI – Input Voltage – V

Figure 19

TJ = 25°C

TJ = 0°C

5 5.5 6

TPS2043, TPS2053

TRIPLE POWER-DISTRIBUTION SWITCHES

SLVS191 – JANUARY 1999

TYPICAL CHARACTERISTICS

STATIC DRAIN-SOURCE ON-STATE RESISTANCE

vs

Ω

175

150

125

100

75

– Static Drain-Source On-State Resistance – m

50

–50 –25 0 25 50 75

DS(on)

r

JUNCTION TEMPERATURE

IO = 0.5 A

V

I(INx)

TJ – Junction Temperature –°C

V

I(INx)

= 3.3 V

= 2.7 V

V

I(INx)

V

I(INx)

100 125 150

Figure 20

INPUT-TO-OUTPUT VOLTAGE

vs

LOAD CURRENT

100

TA = 25°C

= 4.5 V

= 5 V

STATIC DRAIN-SOURCE ON-STATE RESISTANCE

vs

Ω

175

150

125

100

75

– Static Drain-Source On-State Resistance – m

50

DS(on)

2.5 3 3.5 4 4.5

r

INPUT VOLTAGE

IO = 0.5 A

TJ = 125°C

TJ = 85°C

TJ = 25°C

TJ = 0°C

TJ = –40°C

5 5.5 6

VI – Input Voltage – V

Figure 21

SHORT-CURCUIT OUTPUT CURRENT

vs

INPUT VOLTAGE

0.95

75

50

– Input-to-Output Voltage – mW

25

O(OUTx)

V
–

I(INx)

0

V

0.1 0.2 0.4

V

V

= 3.3 V

I(INx)

V

= 4.5 V

I(INx)

IL – Load Current – A

Figure 22

= 2.7 V

I(INx)

V

= 5 V

I(INx)

0.5 0.6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

0.9

0.85

– Short-circuit Output Current – A

OS

I

0.8

2.5 3 3.5 4

TJ = –40°C

TJ = 25°C

TJ = 125°C

4.5 5 65.5

VI – Input Voltage – V

Figure 23

13

TPS2043, TPS2053
TRIPLE POWER-DISTRIBUTION SWITCHES

SLVS191 – JANUARY 1999

TYPICAL CHARACTERISTICS

1.2
TA = 25°C
Load Ramp = 1 A/10 ms

1.175

1.15

Threshold Trip Current – A

1.125

1.1

2.5 3 3.5 4

2.5

2.4

THRESHOLD TRIP CURRENT

vs

INPUT VOLTAGE

4.5 5 65.5

VI – Input Voltage – V

Figure 24

UNDERVOLTAGE LOCKOUT

vs

JUNCTION TEMPERATURE

SHORT CIRCUIT OUTPUT CURRENT

JUNCTION TEMPERATURE

0.95

0.9

V

I(INx)

0.85

– Short-circuit Output Current – A

OS

I

0.8
–50 –25 0 25 50

TJ – Junction Temperature – °C

CURRENT-LIMIT RESPONSE

500

450

sµ

400

vs

V

= 4 V

V

= 2.7 V

I(INx)

Figure 25

vs

PEAK CURRENT

= 5 V

I(INx)

75 100 125

V

= 5 V

I(INx)

TA = 25°C

Start Threshold

2.3

2.2

2.1

UVLO – Undervoltage Lockout – V

2

–50 –25 0 25 50 75

TJ – Junction Temperature – °C

Figure 26

14

Stop Threshold

350
300

250

200
150

Current Limit Response –

100

50

100 125 150

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

0

0 2.5 5 7.5

10 12.5

Peak Current – A

Figure 27

TPS2043, TPS2053

TRIPLE POWER-DISTRIBUTION SWITCHES

SLVS191 – JANUARY 1999

TYPICAL CHARACTERISTICS

OVERCURRENT RESPONSE TIME (OCx)

vs

PEAK CURRENT

8

V

= 5 V

I(INx)

TA = 25°C

6

sµ

4

Response Time –

2

Power Supply

2.7 V to 5.5 V

0

0 2.5 5 7.5

Peak Current – A

Figure 28

APPLICATION INFORMATION

2

IN1

6

IN2

16

OC1

13

OC2

12

OC3

9

NC

3

EN1

4
7

EN3

8

NC

OUT1

OUT2

OUT3

NC

GND1

GND2

10 12.5

15

0.1 µF 22 µF

14

0.1 µF 22 µF

11

0.1 µF 22 µF

10EN2

1
5

Load

Load

Load

Figure 29. Typical Application

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

15

TPS2043, TPS2053
TRIPLE POWER-DISTRIBUTION SWITCHES

SLVS191 – JANUARY 1999

APPLICATION INFORMATION

power-supply considerations

A 0.01-µF to 0.1-µF ceramic bypass capacitor between INx and GND, close to the device, is recommended.
Placing a high-value electrolytic capacitor on the output pin(s) is recommended when the output load is heavy .
This precaution reduces power-supply transients that may cause ringing on the input. Additionally , bypassing
the output with a 0.01-µF to 0.1-µF ceramic capacitor improves the immunity of the device to short-circuit
transients.

overcurrent

A sense FET checks for overcurrent conditions. Unlike current-sense resistors, sense FET s do not increase the
series resistance of the current path. When an overcurrent condition is detected, the device maintains a
constant output current and reduces the output voltage accordingly . Complete shutdown occurs only if the fault
is present long enough to activate thermal limiting.

Three possible overload conditions can occur. In the first condition, the output has been shorted before the
device is enabled or before V
and immediately switch into a constant-current output.

has been applied (see Figure 6). The TPS2043 and TPS2053 sense the short

I(INx)

In the second condition, the excessive load occurs while the device is enabled. At the instant the excessive load
occurs, very high currents may flow for a short time before the current-limit circuit can react. After the
current-limit circuit has tripped (reached the overcurrent trip threshhold) the device switches into
constant-current mode.

In the third condition, the load has been gradually increased beyond the recommended operating current. The
current is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device is
exceeded (see Figure 7). The TPS2043 and TPS2053 are capable of delivering current up to the current-limit
threshold without damaging the device. Once the threshold has been reached, the device switches into its
constant-current mode.

OC response

The OC open-drain output is asserted (active low) when an overcurrent or overtemperature condition is
encountered. The output will remain asserted until the overcurrent or overtemperature condition is removed.
Connecting a heavy capacitive load to an enabled device can cause momentary false overcurrent reporting from
the inrush current flowing through the device, charging the downstream capacitor. An RC filter of 500 µs (see
Figure 30) can be connected to the OC
capacitors on the output lowers the inrush current flow through the device during hot-plug events by providing
a low impedance energy source, thereby reducing erroneous overcurrent reporting.

pin to reduce false overcurrent reporting. Using low-ESR electrolytic

16

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

OC

response (continued)

TPS2043, TPS2053

TRIPLE POWER-DISTRIBUTION SWITCHES

SLVS191 – JANUARY 1999

APPLICATION INFORMATION

GND1
IN1
EN1

EN2
GND2

IN2
EN3
NC

TPS2043

OC1
OUT1
OUT2

OC2

OC3
OUT3

NC
NC

V+

R

pullup

GND1
IN1
EN1

EN2
GND2
IN2
EN3

NC

TPS2043

OUT1
OUT2

OUT3

OC1

OC2

OC3

NC
NC

V+

R

pullup

R

filter

To USB
Controller

C

filter

Figure 30. Typical Circuit for OC Pin and RC Filter for Damping Inrush OC Responses

power dissipation and junction temperature

The low on-resistance on the n-channel MOSFET allows small surface-mount packages, such as SOIC, to pass
large currents. The thermal resistances of these packages are high compared to those of power packages; it
is good design practice to check power dissipation and junction temperature. The first step is to find r
the input voltage and operating temperature. As an initial estimate, use the highest operating ambient
temperature of interest and read r

2

P

+

r

D

DS

(on)

I

from Figure 21. Next, calculate the power dissipation using:

DS(on)

DS(on)

at

Finally, calculate the junction temperature:

T

+

P

R

)

JA

T

A

J

q

D

Where:

T

= Ambient Temperature °C

A

R

= Thermal resistance SOIC = 172°C/W

θJA

Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees,
repeat the calculation, using the calculated value as the new estimate. Two or three iterations are generally
sufficient to get an acceptable answer.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

17

TPS2043, TPS2053
TRIPLE POWER-DISTRIBUTION SWITCHES

SLVS191 – JANUARY 1999

APPLICATION INFORMATION

thermal protection

Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present for
extended periods of time. The faults force the TPS2043 and TPS2053 into constant current mode, which causes
the voltage across the high-side switch to increase; under short-circuit conditions, the voltage across the switch
is equal to the input voltage. The increased dissipation causes the junction temperature to rise to high levels.
The protection circuit senses the junction temperature of the switch and shuts it off. Hysteresis is built into the
thermal sense circuit, and after the device has cooled approximately 20 degrees, the switch turns back on. The
switch continues to cycle in this manner until the load fault or input power is removed.

The TPS2043 and TPS2053 implement a dual thermal trip to allow fully independent operation of the power
distribution switches. In an overcurrent or short-circuit condition the junction temperature will rise. Once the die
temperature rises to approximately 140°C, the internal thermal sense circuitry checks which power switch is
in an overcurrent condition and turns that power switch off, thus isolating the fault without interrupting operation
of the adjacent power switch. Should the die temperature exceed the first thermal trip point of 140°C and reach
160°C, both switches turn off. The OC
overcurrent occurs.

open-drain output is asserted (active low) when overtemperature or

undervoltage lockout (UVLO)

An undervoltage lockout ensures that the power switch is in the off state at power up. Whenever the input voltage
falls below approximately 2 V, the power switch will be quickly turned off. This facilitates the design of
hot-insertion systems where it is not possible to turn off the power switch before input power is removed. The
UVLO will also keep the switch from being turned on until the power supply has reached at least 2 V, even if
the switch is enabled. Upon reinsertion, the power switch will be turned on with a controlled rise time to reduce
EMI and voltage overshoots.

universal serial bus (USB) applications

The universal serial bus (USB) interface is a 12-Mb/s, or 1.5-Mb/s, multiplexed serial bus designed for
low-to-medium bandwidth PC peripherals (e.g., keyboards, printers, scanners, and mice). The four-wire USB
interface is conceived for dynamic attach-detach (hot plug-unplug) of peripherals. Two lines are provided for
differential data, and two lines are provided for 5-V power distribution.

USB data is a 3.3-V level signal, but power is distributed at 5 V to allow for voltage drops in cases where power
is distributed through more than one hub across long cables. Each function must provide its own regulated 3.3 V
from the 5-V input or its own internal power supply.

The USB specification defines the following five classes of devices, each differentiated by power-consumption
requirements:

D

Hosts/self-powered hubs (SPH)

D

Bus-powered hubs (BPH)

D

Low-power, bus-powered functions

D

High-power, bus-powered functions

D

Self-powered functions

Self-powered and bus-powered hubs distribute data and power to downstream functions. The TPS2043 and
TPS2053 can provide power-distribution solutions for many of these classes of devices.

18

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS2043, TPS2053

TRIPLE POWER-DISTRIBUTION SWITCHES

SLVS191 – JANUARY 1999

APPLICATION INFORMATION

host/self-powered and bus-powered hubs

Hosts and self-powered hubs have a local power supply that powers the embedded functions and the
downstream ports (see Figure 31). This power supply must provide from 5.25 V to 4.75 V to the board side of
the downstream connection under full-load and no-load conditions. Hosts and SPHs must have current-limit
protection and must report overcurrent conditions to the USB controller. Typical SPHs are desktop PCs,
monitors, printers, and stand-alone hubs.

Downstream

USB Ports

Power Supply

D+

3.3 V
5 V

†

†

USB

Controller

†

An RC filter may be needed, see Figure 36

†

0.1 µF

11

13

12

D–
V

TPS2043

2

IN1

6

IN2

OC1

3

EN1
OC2

4

EN2
OC3

7

EN3

9

NC

8

NC

GND1

OUT1

OUT2

OUT3

GND2

1

5

NC

15

14

11

10

+

+

+

33 µF

33 µF

33 µF

BUS

GND

D+
D–

V

BUS

GND

D+
D–

V

BUS

GND

Figure 31. T ypical Three-Port USB Host/Self-Powered Hub

Bus-powered hubs obtain all power from upstream ports and often contain an embedded function. The hubs
are required to power up with less than one unit load. The BPH usually has one embedded function, and power
is always available to the controller of the hub. If the embedded function and hub require more than 100 mA
on power up, the power to the embedded function may need to be kept off until enumeration is completed. This
can be accomplished by removing power or by shutting off the clock to the embedded function. Power switching
the embedded function is not necessary if the aggregate power draw for the function and controller is less than
one unit load. The total current drawn by the bus-powered device is the sum of the current to the controller, the
embedded function, and the downstream ports, and it is limited to 500 mA from an upstream port.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

19

TPS2043, TPS2053
TRIPLE POWER-DISTRIBUTION SWITCHES

SLVS191 – JANUARY 1999

APPLICATION INFORMATION

low-power bus-powered functions and high-power bus-powered functions

Both low-power and high-power bus-powered functions obtain all power from upstream ports; low-power
functions always draw less than 100 mA, and high-power functions must draw less than 100 mA at power up
and can draw up to 500 mA after enumeration. If the load of the function is more than the parallel combination
of 44 Ω and 10 µF at power up, the device must implement inrush current limiting (see Figure 32).

Power Supply

3.3 V

10 µF

0.1 µF

TPS2043

2

IN1

6

IN2

OUT1

15

0.1 µF 10 µF

Internal

Function

V

D+

D–
BUS
GND

USB

Control

16
13

12

3

EN1

4

EN2

7

EN3

8

NC

OC1
OC2
OC3

9

NC

OUT2

OUT3

GND1

GND2

NC

14

0.1 µF 10 µF

11

0.1 µF 10 µF

10

1
5

Figure 32. High-Power Bus-Powered Function

Internal

Function

Internal

Function

20

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS2043, TPS2053

TRIPLE POWER-DISTRIBUTION SWITCHES

SLVS191 – JANUARY 1999

APPLICATION INFORMATION

USB power-distribution requirements

USB can be implemented in several ways, and, regardless of the type of USB device being developed, several
power distribution features must be implemented.

D

Hosts/self-powered hubs must:
– Current-limit downstream ports
– Report overcurrent conditions on USB V

D

Bus-powered hubs must:
– Enable/disable power to downstream ports
– Power up at <100 mA
– Limit inrush current (<44 Ω and 10 µF)

D

Functions must:
– Limit inrush currents
– Power up at <100 mA

The feature set of the TPS2043 and TPS2053 allows them to meet each of these requirements. The integrated
current-limiting and overcurrent reporting is required by hosts and self-powered hubs. The logic-level enable
and controlled rise times meet the need of both input and output ports on bus-power hubs, as well as the input
ports for bus-power functions (see Figure 39).

BUS

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

21

TPS2043, TPS2053
TRIPLE POWER-DISTRIBUTION SWITCHES

SLVS191 – JANUARY 1999

APPLICATION INFORMATION

TUSB2040

Hub Controller

Upstream
Port

D +
D –

GND

5 V

TPS2041

OC EN

IN

1 µF

1/2 SN75240

A

C

B

D

OUT

0.1 µF

4.7 µF

GND

5 V Power

Supply

TPS76333

IN

3.3 V

GND

48-MHz

Crystal

Tuning

Circuit

4.7 µF

DP0
DM0

V

CC

XTAL1

XTAL2

OCSOFF

GND

BUSPWR

GANGED

DP1

DM1

DP2

DM2

DP3

DM3

DP4

DM4

PWRON1

OVRCUR1

PWRON2

OVRCUR2

PWRON3

OVRCUR3

Tie to TPS2041 EN

ABC

SN75240

ABC

1/2 SN75240

TPS2043

EN1

OUT1
OUT2

OC1

EN2

OC2

IN1

EN3

OUT3

OC3

IN2

Input

D

D

0.1 µF

0.1 µF

Ferrite Beads

Ferrite Beads

Ferrite Beads

Downstream

Ports
D +

D –
GND

5 V

†

47 µF

D +
D –

GND

5 V

†

47 µF

D +
D –

GND

5 V

†

47 µF

†

USB rev 1.1 requires 120 µF per hub.

Figure 33. Hybrid Self/Bus-Powered Hub Implementation

22

GND1
GND2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS2043, TPS2053

TRIPLE POWER-DISTRIBUTION SWITCHES

SLVS191 – JANUARY 1999

APPLICATION INFORMATION

generic hot-plug applications (see Figure 34)

In many applications it may be necessary to remove modules or pc boards while the main unit is still operating.
These are considered hot-plug applications. Such implementations require the control of current surges seen
by the main power supply and the card being inserted. The most effective way to control these surges is to limit
and slowly ramp the current and voltage being applied to the card, similar to the way in which a power supply
normally turns on. Due to the controlled rise times and fall times of the TPS2043 and TPS2053, these devices
can be used to provide a softer start-up to devices being hot-plugged into a powered system. The UVLO feature
of the TPS2043 and TPS2053 also ensures the switch will be off after the card has been removed, and the switch
will be off during the next insertion. The UVLO feature guarantees a soft start with a controlled rise time for every
insertion of the card or module.

PC Board

TPS2043

OC1
OUT1
OUT2

OC2

OC3
OUT3

Block of
Circuitry

Block of
Circuitry

Block of
Circuitry

Power

Supply

2.7 V to 5.5 V

1000 µF
Optimum

0.1 µF

GND1
IN1
EN1
EN2
GND2
IN2
EN3

Overcurrent Response

Figure 34. Typical Hot-Plug Implementation

By placing the TPS2043 and TPS2053 between the V

input and the rest of the circuitry , the input power will

CC

reach these devices first after insertion. The typical rise time of the switch is approximately 2.5 ms, providing
a slow voltage ramp at the output of the device. This implementation controls system surge currents and
provides a hot-plugging mechanism for any device.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

23

TPS2043, TPS2053
TRIPLE POWER-DISTRIBUTION SWITCHES

SLVS191 – JANUARY 1999

MECHANICAL DATA

D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PIN SHOWN

0.050 (1,27)

14

1

0.069 (1,75) MAX

A

0.020 (0,51)

0.014 (0,35)

0.010 (0,25)

0.004 (0,10)

DIM

8

7

PINS **

0.010 (0,25)

0.157 (4,00)

0.150 (3,81)

M

0.244 (6,20)

0.228 (5,80)

Seating Plane

0.004 (0,10)

8

14

0.008 (0,20) NOM

0°–8°

16

Gage Plane

0.010 (0,25)

0.044 (1,12)

0.016 (0,40)

A MAX

A MIN

NOTES: A. All linear dimensions are in inches (millimeters).

24

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

0.197

(5,00)

0.189

(4,80)

0.344
(8,75)

0.337
(8,55)

0.394

(10,00)

0.386
(9,80)

4040047/D 10/96

PACKAGE OPTION ADDENDUM

www.ti.com

6-Dec-2006

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package
Drawing

Pins Package

Qty

Eco Plan

TPS2043D NRND SOIC D 16 40 Green (RoHS &

no Sb/Br)

TPS2043DG4 NRND SOIC D 16 40 Green (RoHS &

no Sb/Br)

TPS2043DR NRND SOIC D 16 2500 Green (RoHS &

no Sb/Br)

TPS2043DRG4 NRND SOIC D 16 2500 Green (RoHS &

no Sb/Br)

TPS2053D NRND SOIC D 16 40 Green (RoHS &

no Sb/Br)

TPS2053DG4 NRND SOIC D 16 40 Green (RoHS &

no Sb/Br)

TPS2053DR NRND SOIC D 16 2500 Green (RoHS &

no Sb/Br)

TPS2053DRG4 NRND SOIC D 16 2500 Green (RoHS &

no Sb/Br)

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

Call TI Level-1-260C-UNLIM

Call TI Level-1-260C-UNLIM

Call TI Level-1-260C-UNLIM

Call TI Level-1-260C-UNLIM

(3)

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

Addendum-Page 1

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty . Except where mandated by government requirements, testing of all
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TI assumes no liability for applications assistance or customer product design. Customers are responsible for
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Following are URLs where you can obtain information on other Texas Instruments products and application
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Products Applications

Amplifiers amplifier.ti.com Audio www.ti.com/audio
Data Converters dataconverter.ti.com Automotive www.ti.com/automotive

DSP dsp.ti.com Broadband www.ti.com/broadband
Interface interface.ti.com Digital Control www.ti.com/digitalcontrol
Logic logic.ti.com Military www.ti.com/military
Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork
Microcontrollers microcontroller.ti.com Security www.ti.com/security
Low Power Wireless www.ti.com/lpw Telephony www.ti.com/telephony

Video & Imaging www.ti.com/video
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