Texas Instruments TPS2042P, TPS2042DR, TPS2042D, TPS2052P, TPS2052DR Datasheet

TPS2042, TPS2052

DUAL POWER-DISTRIBUTION SWITCHES

SLVS173A – AUGUST 1998 – REVISED APRIL 1999

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

135-mΩ -Maximum (5-V Input) High-Side
MOSFET Switch

D

500 mA Continuous Current per Channel

D

Short-Circuit and Thermal Protection With
Overcurrent Logic Output

D

Operating Range . . . 2.7-V to 5.5-V

D

Logic-Level Enable Input

D

2.5-ms Typical Rise Time

D

Undervoltage Lockout

D

10 µA Maximum Standby Supply Current

D

Bidirectional Switch

D

Available in 8-pin SOIC and PDIP Packages

D

Ambient Temperature Range, –40°C to 85°C

D

2-kV Human-Body-Model, 200-V
Machine-Model ESD Protection

D

UL Listed – File No. E169910

description

The TPS2042 and TPS2052 dual power distribution switches are intended for applications where heavy
capacitive loads and short circuits are likely to be encountered. The TPS2042 and the TPS2052 incorporate
in single packages two 135-mΩ N-channel MOSFET high-side power switches for power distribution systems
that require multiple power switches. Each switch is controlled by a logic enable that is compatible with 5-V logic
and 3-V logic. Gate drive is provided by an internal charge pump designed to control the power-switch rise times
and fall times to minimize current surges during switching. The charge pump requires no external components
and allows operation from supplies as low as 2.7 V.

When the output load exceeds the current-limit threshold or a short is present, the TPS2042 and TPS2052 limit
the output current to a safe level by switching into a constant-current mode, pulling the overcurrent (OCx

) logic
output low. When continuous heavy overloads and short circuits increase the power dissipation in the switch
causing the junction temperature to rise, a thermal protection circuit shuts off the switch to prevent damage.
Recovery from a thermal shutdown is automatic once the device has cooled sufficiently. Internal circuitry
ensures the switch remains off until valid input voltage is present.

The TPS2042 and TPS2052 are designed to limit at 0.9-A load. These power distribution switches are available
in 8-pin small-outline integrated circuit (SOIC) and 8-pin plastic dual-in-line packages (PDIP) and operate over
an ambient temperature range of –40°C to 85°C.

AVAILABLE OPTIONS

RECOMMENDED

TYPICAL

PACKAGED DEVICES

T

A

ENABLE

MAXIMUM CONTINUOUS

LOAD CURRENT

(A)

SHORT-CIRCUIT CURRENT

LIMIT AT 25°C

(A)

SOIC

(D)

†

PDIP

(P)

–40°C to 85°C Active low 0.5 0.9 TPS2042D TPS2042P
–40°C to 85°C Active high 0.5 0.9 TPS2052D TPS2052P

†

The D package is available taped and reeled. Add an R suffix to device type (e.g., TPS2042DR)

Copyright  1999, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

1
2
3
4

8
7
6
5

GND

IN
EN1
EN2

OC1
OUT1
OUT2
OC2

TPS2042

D OR P PACKAGE

(TOP VIEW)

1
2
3
4

8
7
6
5

GND

IN
EN1
EN2

OC1
OUT1
OUT2
OC2

TPS2052

D OR P PACKAGE

(TOP VIEW)

TPS2042, TPS2052
DUAL POWER-DISTRIBUTION SWITCHES

SLVS173A – AUGUST 1998 – REVISED APRIL 1999

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS2042 functional block diagram

†

Current sense

Thermal

Sense

Driver

Current

Limit

Charge

Pump

UVLO

CS

†

Driver

Current

Limit

CS

†

Thermal

Sense

Charge

Pump

Power Switch

GND

EN1

IN

EN2

OC1

OUT1

OUT2

OC2

Terminal Functions

TERMINAL

NO.

NAME

D OR P

I/O

DESCRIPTION

TPS2042 TPS2052

EN1 3 – I Enable input. Logic low turns on power switch, IN-OUT1.
EN2 4 – I Enable input. Logic low turns on power switch, IN-OUT2.
EN1 – 3 I Enable input. Logic high turns on power switch, IN-OUT1.
EN2 – 4 I Enable input. Logic high turns on power switch, IN-OUT2.
GND 1 1 I Ground
IN 2 2 I Input voltage
OC1 8 8 O Over current. Logic output active low, for power switch, IN-OUT1
OC2 5 5 O Over current. Logic output active low, for power switch, IN-OUT2
OUT1 7 7 O Power-switch output
OUT2 6 6 O Power-switch output

TPS2042, TPS2052

DUAL POWER-DISTRIBUTION SWITCHES

SLVS173A – AUGUST 1998 – REVISED APRIL 1999

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

detailed description

power switch

The power switch is an N-channel MOSFET with a maximum on-state resistance of 135 mΩ (V

I(IN)

= 5 V).
Configured as a high-side switch, the power switch prevents current flow from OUTx to IN and IN to OUTx when
disabled. The power switch supplies a minimum of 500 mA per switch.

charge pump

An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate
of the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requires
very little supply current.

driver

The driver controls the gate voltage of the power switch. T o limit large current surges and reduce the associated
electromagnetic interference (EMI) produced, the driver incorporates circuitry that controls the rise times and
fall times of the output voltage. The rise and fall times are typically in the 2-ms to 4-ms range.

enable (ENx or ENx)

The logic enable disables the power switch and the bias for the charge pump, driver, and other circuitry to reduce
the supply current to less than 10 µA when a logic high is present on ENx (TPS2042) or a logic low is present
on ENx (TPS2052). A logic zero input on ENx or logic high on ENx restores bias to the drive and control circuits
and turns the power on. The enable input is compatible with both TTL and CMOS logic levels.

overcurrent (OCx)

The OCx

open-drain output is asserted (active low) when an overcurrent or overtemperature condition is

encountered. The output will remain asserted until the overcurrent or overtemperature condition is removed.

current sense

A sense FET monitors the current supplied to the load. The sense FET measures current more efficiently than
conventional resistance methods. When an overload or short circuit is encountered, the current-sense circuitry
sends a control signal to the driver. The driver in turn reduces the gate voltage and drives the power FET into
its saturation region, which switches the output into a constant current mode and holds the current constant
while varying the voltage on the load.

thermal sense

The TPS2042 and TPS2052 implement a dual-threshold thermal trip to allow fully independent operation of the
power distribution switches. In an overcurrent or short-circuit condition the junction temperature rises. When
the die temperature rises to approximately 140°C, the internal thermal sense circuitry checks to determine which
power switch is in an overcurrent condition and turns off that switch, thus isolating the fault without interrupting
operation of the adjacent power switch. Hysteresis is built into the thermal sense, and after the device has cooled
approximately 20 degrees, the switch turns back on. The switch continues to cycle off and on until the fault is
removed. The (OCx

) open-drain output is asserted (active low) when overtemperature or overcurrent occurs.

undervoltage lockout

A voltage sense circuit monitors the input voltage. When the input voltage is below approximately 2 V , a control
signal turns off the power switch.

TPS2042, TPS2052
DUAL POWER-DISTRIBUTION SWITCHES

SLVS173A – AUGUST 1998 – REVISED APRIL 1999

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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Input voltage range, V

I(IN)

(see Note1) –0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, V

O(OUTx)

(see Note1) –0.3 V to V

I(IN)

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

I(ENx)

or V

I(ENx)

–0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current, I

O(OUTx)

internally limited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating virtual junction temperature range, T

J

–40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . .

Electrostatic discharge (ESD) protection: Human body model MIL-STD-883C 2 kV. . . . . . . . . . . . . . . . . . . . .

Machine model 0.2 kV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltages are with respect to GND.

DISSIPATION RATING TABLE

PACKAGE

TA ≤ 25°C

POWER RATING

DERATING FACTOR

ABOVE TA = 25°C

TA = 70°C

POWER RATING

TA = 85°C

POWER RATING

D 725 mW 5.8 mW/°C 464 mW 377 mW
P 1175 mW 9.4 mW/°C 752 mW 611 mW

recommended operating conditions

TPS2042 TPS2052

MIN MAX MIN MAX

UNIT

Input voltage, V

I(IN)

2.7 5.5 2.7 5.5 V

Input voltage, V

I(ENx

)

or V

I(ENx)

0 5.5 0 5.5 V

Continuous output current, I

O(OUTx)

0 500 0 500 mA

Operating virtual junction temperature, T

J

–40 125 –40 125 °C

TPS2042, TPS2052

DUAL POWER-DISTRIBUTION SWITCHES

SLVS173A – AUGUST 1998 – REVISED APRIL 1999

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating junction temperature range, V

I(IN)

= 5.5 V,

I

O

= rated current, V

I(ENx)

= 0 V, V

I(ENx)

= Hi (unless otherwise noted)

power switch

TPS2042 TPS2052

PARAMETER

TEST CONDITIONS

†

MIN TYP MAX MIN TYP MAX

UNIT

V

I(IN)

= 5 V,

IO = 0.5 A

TJ = 25°C,

80 95 80 95

Static drain-source on-state
resistance, 5-V operation

V

I(IN)

= 5 V,

IO = 0.5 A

TJ = 85°C,

90 120 90 120

V

I(IN)

= 5 V,

IO = 0.5 A

TJ = 125°C,

100 135 100 135

mΩ

r

DS(on)

V

I(IN)

= 3.3 V,

IO = 0.5 A

TJ = 25°C,

85 105 85 105

Static drain-source on-state
resistance, 3.3-V operation

V

I(IN)

= 3.3 V,

IO = 0.5 A

TJ = 85°C,

100 135 100 135

V

I(IN)

= 3.3 V,

IO = 0.5 A

TJ = 125°C,

115 150 115 150

p

V

I(IN)

= 5.5 V,

CL = 1 µF,

TJ = 25°C,
RL=10 Ω

2.5 2.5

trRise time, output

V

I(IN)

= 2.7 V,

CL = 1 µF,

TJ = 25°C,
RL=10 Ω

3 3

ms

p

V

I(IN)

= 5.5 V,

CL = 1 µF,

TJ = 25°C,
RL=10 Ω

4.4 4.4

tfFall time, output

V

I(IN)

= 2.7 V,

CL = 1 µF,

TJ = 25°C,
RL=10 Ω

2.5 2.5

ms

†

Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.

enable input ENx or ENx

TPS2042 TPS2052

PARAMETER

TEST CONDITIONS

MIN TYP MAX MIN TYP MAX

UNIT

V

IH

High-level input voltage 2.7 V ≤ V

I(IN)

≤ 5.5 V 2 2 V

p

4.5 V ≤ V

I(IN)

≤ 5.5 V 0.8 0.8 V

VILLow-level input voltage

2.7 V≤ V

I(IN)

≤ 4.5 V 0.4 0.4

p

TPS2042 V

I(ENx

)

= 0 V or V

I(ENx)

= V

I(IN)

–0.5 0.5

IIInput current

TPS2052 V

I(ENx)

= V

I(IN)

or V

I(ENx)

= 0 V –0.5 0.5

µ

A

t

on

Turnon time CL = 100 µF, RL=10 Ω 20 20 ms

t

off

Turnoff time CL = 100 µF, RL=10 Ω 40 40

current limit

TPS2042 TPS2052

PARAMETER

TEST CONDITIONS

†

MIN TYP MAX MIN TYP MAX

UNIT

I

OS

Short-circuit output current

V

I(IN)

= 5 V, OUT connected to GND,

Device enable into short circuit

0.7 0.9 1.1 0.7 0.9 1.1 A

†

Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.

TPS2042, TPS2052
DUAL POWER-DISTRIBUTION SWITCHES

SLVS173A – AUGUST 1998 – REVISED APRIL 1999

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating junction temperature range, V

I(IN)

= 5.5 V,

I

O

= rated current, V

I(ENx)

= 0 V, V

I(ENx)

= Hi (unless otherwise noted) (continued)

supply current

TPS2042 TPS2052

PARAMETER

TEST CONDITIONS

MIN TYP MAX MIN TYP MAX

UNIT

pp

TJ = 25°C

0.015 1

Su ly

current,

No Load

V

I(ENx)

= V

I(IN)

–40°C ≤ TJ ≤ 125°C

TPS2042

10

,

low-level

on OUT

TJ = 25°C

0.015 1

µ

A

output

V

I(ENx)

= 0

V

–40°C ≤ TJ ≤ 125°C

TPS2052

10

pp

TJ = 25°C

80 100

Su ly

current,

No Load

V

I(ENx)

= 0

V

–40°C ≤ TJ ≤ 125°C

TPS2042

100

,

high-level

on OUT

TJ = 25°C

80 100

µ

A

output

V

I(ENx)

=

V

I(IN)

–40°C ≤ TJ ≤ 125°C

TPS2052

100

Leakage

OUT

V

I(ENx)

= V

I(IN)

–40°C ≤ TJ ≤ 125°C TPS2042 100

g

current

connecte

d

to ground

V

I(ENx)

= 0 V –40°C ≤ TJ ≤ 125°C TPS2052 100

µ

A

Reverse

IN = high

V

I(EN

)

= 0 V

°

TPS2042 0.3

leak

age

current

g

impedance

V

I(EN)

= Hi

T

J

=

25°C

TPS2052 0.3

µ

A

undervoltage lockout

TPS2042 TPS2052

PARAMETER

TEST CONDITIONS

MIN TYP MAX MIN TYP MAX

UNIT

Low-level input voltage 2 2.5 2 2.5 V
Hysteresis TJ = 25°C 100 100 mV

overcurrent OCx

TPS2042 TPS2052

PARAMETER

TEST CONDITIONS

MIN TYP MAX MIN TYP MAX

UNIT

Sink current

†

VO = 5 V 10 10 mA

Output low voltage IO = 5 mA, V

OL(OCx)

0.5 0.5 V

Off-state current

†

VO = 5 V, VO = 3.3 V 1 1 µA

†

Specified by design, not production tested.

TPS2042, TPS2052

DUAL POWER-DISTRIBUTION SWITCHES

SLVS173A – AUGUST 1998 – REVISED APRIL 1999

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

RL CL

OUTx

t

r

t

f

90%

90%

10%

10%

50%

50%

90%

10%

V

O(OUTx)

V

I(ENx)

V

O(OUTx)

VOLTAGE WA VEFORMS

TEST CIRCUIT

t

on

t

off

50%

50%

90%

10%

V

I(ENx)

V

O(OUTx)

t

on

t

off

Figure 1. Test Circuit and Voltage Waveforms

Figure 2. Turnon Delay and Rise Time

with 0.1-µF Load

V

O(OUT)

(2 V/div)

0123456

t – Time – ms

78910

V

I(IN)

= 5 V
TA = 25°C
CL = 0.1 µF

V

I(EN)

(5 V/div)

Figure 3. Turnoff Delay and Fall Time

with 0.1-µF Load

0 1000 2000 3000

t – Time – ms

4000 5000

V

I(IN)

= 5 V
TA = 25°C
CL = 0.1 µF

V

I(EN)

(5 V/div)

V

O(OUT)

(2 V/div)

TPS2042, TPS2052
DUAL POWER-DISTRIBUTION SWITCHES

SLVS173A – AUGUST 1998 – REVISED APRIL 1999

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

Figure 4. Turnon Delay and Rise Time

with 1-µF Load

Figure 5. Turnoff Delay and Fall Time

with 1-µF Load

0123456

t – Time – ms

78910

V

I(EN)

(5 V/div)

V

O(OUT)

(2 V/div)

V

I(IN)

= 5 V
TA = 25°C
CL = 1 µF
RL = 10 Ω

0 2 4 6 8 10 12

t – Time – ms

14 16 18 20

V

I(IN)

= 5 V
TA = 25°C
CL = 1 µF
RL = 10 Ω

V

I(EN)

(5 V/div)

V

O(OUT)

(2 V/div)

Figure 6. TPS2042, Short-Circuit Current,

Device Enabled into Short

012 345 6

t – Time – ms

78910

I

O(OUT)

(0.2 A/div)

V

I(IN)

= 5 V

TA = 25°C

V

I(EN)

(5 V/div)

Figure 7. TPS2042, Threshold Trip Current

with Ramped Load on Enabled Device

01020 30405060

t – Time – ms

70 80 90 100

I

O(OUT)

(0.5 A/div)

V

I(IN)

= 5 V
TA = 25°C

V

O(OUT)

(2 V/div)