TEXAS INSTRUMENTS TPS2042, TPS2052 Technical data

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MAXIMUM CONTINUOUS

SHORT-CIRCUIT CURRENT

135-mΩ -Maximum (5-V Input) High-Side MOSFET Switch

500 mA Continuous Current per Channel

Short-Circuit and Thermal Protection With Overcurrent Logic Output

Operating Range . . . 2.7-V to 5.5-V

Logic-Level Enable Input

2.5-ms Typical Rise Time

Undervoltage Lockout

10 µA Maximum Standby Supply Current

Bidirectional Switch

Available in 8-pin SOIC and PDIP Packages

Ambient Temperature Range, –40°C to 85°C

2-kV Human-Body-Model, 200-V Machine-Model ESD Protection

UL Listed – File No. E169910

description

TPS2042, TPS2052

DUAL POWER-DISTRIBUTION SWITCHES

SLVS173A – AUGUST 1998 – REVISED APRIL 1999

TPS2042

D OR P PACKAGE

(TOP VIEW)

GND

EN1 EN2

GND

2 3 4

TPS2052

D OR P PACKAGE

(TOP VIEW)

EN1 EN2

3 4

8 7 6 5

OC1 OUT1 OUT2 OC2

The TPS2042 and TPS2052 dual power distribution switches are intended for applications where heavy capacitive loads and short circuits are likely to be encountered. The TPS2042 and the TPS2052 incorporate in single packages two 135-mΩ N-channel MOSFET high-side power switches for power distribution systems that require multiple power switches. Each switch is controlled by a logic enable that is compatible with 5-V logic and 3-V logic. Gate drive is provided by an internal charge pump designed to control the power-switch rise times and fall times to minimize current surges during switching. The charge pump requires no external components and allows operation from supplies as low as 2.7 V.

When the output load exceeds the current-limit threshold or a short is present, the TPS2042 and TPS2052 limit the output current to a safe level by switching into a constant-current mode, pulling the overcurrent (OCx

) logic output low. When continuous heavy overloads and short circuits increase the power dissipation in the switch causing the junction temperature to rise, a thermal protection circuit shuts off the switch to prevent damage. Recovery from a thermal shutdown is automatic once the device has cooled sufficiently. Internal circuitry ensures the switch remains off until valid input voltage is present.

The TPS2042 and TPS2052 are designed to limit at 0.9-A load. These power distribution switches are available in 8-pin small-outline integrated circuit (SOIC) and 8-pin plastic dual-in-line packages (PDIP) and operate over an ambient temperature range of –40°C to 85°C.

AVAILABLE OPTIONS

RECOMMENDED

–40°C to 85°C Active low 0.5 0.9 TPS2042D TPS2042P –40°C to 85°C Active high 0.5 0.9 TPS2052D TPS2052P

†

The D package is available taped and reeled. Add an R suffix to device type (e.g., TPS2042DR)

ENABLE

LOAD CURRENT

(A)

TYPICAL

LIMIT AT 25°C

(A)

PACKAGED DEVICES

SOIC

(D)

†

PDIP

(P)

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS2042, TPS2052

I/O

DESCRIPTION

DUAL POWER-DISTRIBUTION SWITCHES

SLVS173A – AUGUST 1998 – REVISED APRIL 1999

TPS2042 functional block diagram

OC1

†

Current sense

GND

EN1

EN2

Thermal

Sense

Driver

Charge

Pump

UVLO

Power Switch

Charge

Pump

Driver

Thermal

Sense

Current

Limit

Current

Limit

†

OUT1

†

OUT2

OC2

Terminal Functions

TERMINAL

NO.

NAME

EN1 3 – I Enable input. Logic low turns on power switch, IN-OUT1. EN2 4 – I Enable input. Logic low turns on power switch, IN-OUT2. EN1 – 3 I Enable input. Logic high turns on power switch, IN-OUT1. EN2 – 4 I Enable input. Logic high turns on power switch, IN-OUT2. GND 1 1 I Ground IN 2 2 I Input voltage OC1 8 8 O Over current. Logic output active low, for power switch, IN-OUT1 OC2 5 5 O Over current. Logic output active low, for power switch, IN-OUT2 OUT1 7 7 O Power-switch output OUT2 6 6 O Power-switch output

D OR P

TPS2042 TPS2052

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

detailed description

power switch

TPS2042, TPS2052

DUAL POWER-DISTRIBUTION SWITCHES

SLVS173A – AUGUST 1998 – REVISED APRIL 1999

The power switch is an N-channel MOSFET with a maximum on-state resistance of 135 mΩ (V Configured as a high-side switch, the power switch prevents current flow from OUTx to IN and IN to OUTx when disabled. The power switch supplies a minimum of 500 mA per switch.

charge pump

An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate of the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requires very little supply current.

driver

The driver controls the gate voltage of the power switch. T o limit large current surges and reduce the associated electromagnetic interference (EMI) produced, the driver incorporates circuitry that controls the rise times and fall times of the output voltage. The rise and fall times are typically in the 2-ms to 4-ms range.

enable (ENx or ENx)

The logic enable disables the power switch and the bias for the charge pump, driver, and other circuitry to reduce the supply current to less than 10 µA when a logic high is present on ENx (TPS2042) or a logic low is present on ENx (TPS2052). A logic zero input on ENx or logic high on ENx restores bias to the drive and control circuits and turns the power on. The enable input is compatible with both TTL and CMOS logic levels.

overcurrent (OCx)

The OCx encountered. The output will remain asserted until the overcurrent or overtemperature condition is removed.

current sense

open-drain output is asserted (active low) when an overcurrent or overtemperature condition is

I(IN)

= 5 V).

A sense FET monitors the current supplied to the load. The sense FET measures current more efficiently than conventional resistance methods. When an overload or short circuit is encountered, the current-sense circuitry sends a control signal to the driver. The driver in turn reduces the gate voltage and drives the power FET into its saturation region, which switches the output into a constant current mode and holds the current constant while varying the voltage on the load.

thermal sense

The TPS2042 and TPS2052 implement a dual-threshold thermal trip to allow fully independent operation of the power distribution switches. In an overcurrent or short-circuit condition the junction temperature rises. When the die temperature rises to approximately 140°C, the internal thermal sense circuitry checks to determine which power switch is in an overcurrent condition and turns off that switch, thus isolating the fault without interrupting operation of the adjacent power switch. Hysteresis is built into the thermal sense, and after the device has cooled approximately 20 degrees, the switch turns back on. The switch continues to cycle off and on until the fault is removed. The (OCx

undervoltage lockout

A voltage sense circuit monitors the input voltage. When the input voltage is below approximately 2 V , a control signal turns off the power switch.

) open-drain output is asserted (active low) when overtemperature or overcurrent occurs.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS2042, TPS2052

UNIT

DUAL POWER-DISTRIBUTION SWITCHES

SLVS173A – AUGUST 1998 – REVISED APRIL 1999

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Input voltage range, V Output voltage range, V Input voltage range, V Continuous output current, I

Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating virtual junction temperature range, T Storage temperature range, T

Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . .

Electrostatic discharge (ESD) protection: Human body model MIL-STD-883C 2 kV. . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltages are with respect to GND.

PACKAGE

D 725 mW 5.8 mW/°C 464 mW 377 mW P 1175 mW 9.4 mW/°C 752 mW 611 mW

(see Note1) –0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I(IN)

O(OUTx)

I(ENx)

(see Note1) –0.3 V to V

or V

I(ENx)

O(OUTx)

stg

Machine model 0.2 kV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DISSIPATION RATING TABLE

TA ≤ 25°C

POWER RATING

DERATING FACTOR

ABOVE TA = 25°C

TA = 70°C

POWER RATING

TA = 85°C

POWER RATING

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I(IN)

–0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

internally limited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

recommended operating conditions

TPS2042 TPS2052

MIN MAX MIN MAX

Input voltage, V Input voltage, V Continuous output current, I Operating virtual junction temperature, T

I(IN) I(ENx

or V

)

I(ENx)

O(OUTx)

2.7 5.5 2.7 5.5 V 0 5.5 0 5.5 V 0 500 0 500 mA

–40 125 –40 125 °C

†

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER

TEST CONDITIONS

†

UNIT

trRise time, output

tfFall time, output

PARAMETER

TEST CONDITIONS

UNIT

VILLow-level input voltage

IIInput current

PARAMETER

TEST CONDITIONS

†

UNIT

TPS2042, TPS2052

DUAL POWER-DISTRIBUTION SWITCHES

SLVS173A – AUGUST 1998 – REVISED APRIL 1999

electrical characteristics over recommended operating junction temperature range, V

= rated current, V

I(ENx)

= 0 V, V

= Hi (unless otherwise noted)

I(ENx)

I(IN)

= 5.5 V,

power switch

TPS2042 TPS2052

MIN TYP MAX MIN TYP MAX

= 5 V,

I(IN)

IO = 0.5 A

Static drain-source on-state resistance, 5-V operation

DS(on)

Static drain-source on-state resistance, 3.3-V operation

†

Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.

= 5 V,

I(IN)

IO = 0.5 A V

= 5 V,

I(IN)

IO = 0.5 A V

= 3.3 V,

I(IN)

IO = 0.5 A V

= 3.3 V,

I(IN)

IO = 0.5 A V

= 3.3 V,

I(IN)

IO = 0.5 A V

= 5.5 V,

I(IN)

CL = 1 µF, V

= 2.7 V,

I(IN)

CL = 1 µF, V

= 5.5 V,

I(IN)

CL = 1 µF, V

= 2.7 V,

I(IN)

CL = 1 µF,

TJ = 25°C,

TJ = 85°C,

TJ = 125°C,

TJ = 25°C,

TJ = 85°C,

TJ = 125°C,

TJ = 25°C, RL=10 Ω

80 95 80 95

90 120 90 120

100 135 100 135

85 105 85 105

100 135 100 135

115 150 115 150

2.5 2.5

3 3

4.4 4.4

2.5 2.5

mΩ

enable input ENx or ENx

TPS2042 TPS2052

MIN TYP MAX MIN TYP MAX

High-level input voltage 2.7 V ≤ V

Turnon time CL = 100 µF, RL=10 Ω 20 20 ms

Turnoff time CL = 100 µF, RL=10 Ω 40 40

off

TPS2042 V TPS2052 V

4.5 V ≤ V

2.7 V≤ V I(ENx

I(ENx)

≤ 5.5 V 2 2 V

I(IN)

≤ 5.5 V 0.8 0.8 V

I(IN)

≤ 4.5 V 0.4 0.4

I(IN)

= 0 V or V

)

= V

I(IN)

I(ENx)

or V

= V

I(IN)

= 0 V –0.5 0.5

I(ENx)

–0.5 0.5

current limit

TPS2042 TPS2052

MIN TYP MAX MIN TYP MAX

= 5 V, OUT connected to GND,

Short-circuit output current

†

Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.

I(IN)

Device enable into short circuit

0.7 0.9 1.1 0.7 0.9 1.1 A

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS2042, TPS2052

PARAMETER

TEST CONDITIONS

UNIT

Su ly

TPS2042

TPS2052

Su ly

TPS2042

TPS2052

leak

25°C

PARAMETER

TEST CONDITIONS

UNIT

PARAMETER

TEST CONDITIONS

UNIT

DUAL POWER-DISTRIBUTION SWITCHES

SLVS173A – AUGUST 1998 – REVISED APRIL 1999

electrical characteristics over recommended operating junction temperature range, V

= rated current, V

I(ENx)

= 0 V, V

= Hi (unless otherwise noted) (continued)

I(ENx)

I(IN)

= 5.5 V,

supply current

TPS2042 TPS2052

MIN TYP MAX MIN TYP MAX

pp current, low-level output

pp current, high-level output

Leakage current

Reverse

age

current

No Load on OUT

OUT connecte to ground

IN = high impedance

= V

I(ENx)

= 0

I(ENx)

= 0

I(ENx)

= V

I(ENx)

= 0 V –40°C ≤ TJ ≤ 125°C TPS2052 100

I(ENx)

= 0 V

I(EN

)

= Hi

I(EN)

TJ = 25°C

I(IN)

–40°C ≤ TJ ≤ 125°C TJ = 25°C –40°C ≤ TJ ≤ 125°C TJ = 25°C –40°C ≤ TJ ≤ 125°C TJ = 25°C

I(IN)

–40°C ≤ TJ ≤ 125°C –40°C ≤ TJ ≤ 125°C TPS2042 100

I(IN)

TPS2042 0.3 TPS2052 0.3

0.015 1 10

80 100

100

80 100

100

undervoltage lockout

TPS2042 TPS2052

MIN TYP MAX MIN TYP MAX

Low-level input voltage 2 2.5 2 2.5 V Hysteresis TJ = 25°C 100 100 mV

overcurrent OCx

Sink current Output low voltage IO = 5 mA, V Off-state current

†

Specified by design, not production tested.

†

VO = 5 V 10 10 mA

VO = 5 V, VO = 3.3 V 1 1 µA

OL(OCx)

TPS2042 TPS2052

MIN TYP MAX MIN TYP MAX

0.5 0.5 V

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS2042, TPS2052

DUAL POWER-DISTRIBUTION SWITCHES

SLVS173A – AUGUST 1998 – REVISED APRIL 1999

PARAMETER MEASUREMENT INFORMATION

OUTx

I(EN)

(5 V/div)

I(ENx)

O(OUTx)

RL CL

O(OUTx)

TEST CIRCUIT

50%

90%

10%

I(ENx)

off

O(OUTx)

VOLTAGE WA VEFORMS

90%

10%

50%

10%

50%

90%

10%

off

Figure 1. Test Circuit and Voltage Waveforms

I(EN)

(5 V/div)

O(OUT)

(2 V/div)

0123456

t – Time – ms

Figure 2. Turnon Delay and Rise Time

with 0.1-µF Load

= 5 V

I(IN)

TA = 25°C CL = 0.1 µF

78910

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

O(OUT)

(2 V/div)

V TA = 25°C CL = 0.1 µF

0 1000 2000 3000

= 5 V

I(IN)

4000 5000

t – Time – ms

Figure 3. Turnoff Delay and Fall Time

with 0.1-µF Load

TPS2042, TPS2052 DUAL POWER-DISTRIBUTION SWITCHES

SLVS173A – AUGUST 1998 – REVISED APRIL 1999

PARAMETER MEASUREMENT INFORMATION

I(EN)

(5 V/div)

= 5 V

I(IN)

O(OUT)

(2 V/div)

0123456

t – Time – ms

TA = 25°C CL = 1 µF RL = 10 Ω

78910

I(EN)

(5 V/div)

O(OUT)

(2 V/div)

= 5 V

I(IN)

TA = 25°C CL = 1 µF RL = 10 Ω

0 2 4 6 8 10 12

t – Time – ms

14 16 18 20

Figure 4. Turnon Delay and Rise Time

with 1-µF Load

I(EN)

(5 V/div)

O(OUT)

(0.2 A/div)

012 345 6

t – Time – ms

Figure 6. TPS2042, Short-Circuit Current,

Device Enabled into Short

= 5 V

I(IN)

TA = 25°C

78910

O(OUT)

(2 V/div)

O(OUT)

(0.5 A/div)

Figure 5. Turnoff Delay and Fall Time

with 1-µF Load

= 5 V

I(IN)

TA = 25°C

01020 30405060

t – Time – ms

70 80 90 100

Figure 7. TPS2042, Threshold Trip Current

with Ramped Load on Enabled Device

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

I(EN)

(5 V/div)

O(OUT)

(o.2 A/div)

PARAMETER MEASUREMENT INFORMATION

= 5 V

I(IN)

TA = 25°C RL = 10 Ω

470 µF

220 µF

100 µF

0 2 4 6 8 10 12

t – Time – ms

Figure 8. Inrush Current with 100-µF, 220-µF

and 470-µF Load Capacitance

14 16 18 20

TPS2042, TPS2052

DUAL POWER-DISTRIBUTION SWITCHES

SLVS173A – AUGUST 1998 – REVISED APRIL 1999

O(OC)

(5 V/div)

= 5 V

I(IN)

O(OUT)

(0.5 A/div)

0 20 40 60 80 100 120

Figure 9. Ramped Load on Enabled Device

Load Ramp,1A/100 ms TA = 25°C

140 160 180 200

t – Time – ms

= 5 V

I(IN)

TA = 25°C

O(OC)

(5 V/div)

O(OUT)

(0.5 A/div)

0 400 800 1200 1600 2000

t – Time – µs

Figure 10. 4-Ω Load Connected to Enabled Device

O(OC)

(5 V/div)

O(OUT)

(1 A/div)

= 5 V

I(IN)

TA = 25°C

0 20 40 60 80 100 120 140 160 180 200

t – Time – µs

Figure 11. 1-Ω Load Connected

to Enabled Device

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS2042, TPS2052 DUAL POWER-DISTRIBUTION SWITCHES

SLVS173A – AUGUST 1998 – REVISED APRIL 1999

TYPICAL CHARACTERISTICS

5.5

4.5

Turn-On Delay – ms

3.5

2.5 3 3.5 4 4.5

= 5 V

I(IN)

CL = 1 µF TA = 25°C

2.9

TURNON DELAY

INPUT VOLTAGE

CL = 1 µF RL = 10 Ω TA = 25°C

VI – Input Voltage – V

Figure 12

RISE TIME

LOAD CURRENT

5 5.5 6

CL = 1 µF RL = 10 Ω

TA = 25°C

Turn-Off Delay – ms

2.5 3 3.5 4 4.5 VI – Input Voltage – V

3.5 V

= 5 V

I(IN)

TA = 25°C CL = 1 µF

3.3

TURNOFF DELAY

INPUT VOLTAGE

5 5.5 6

Figure 13

FALL TIME

LOAD CURRENT

– Rise Time – ms

2.8

2.7

2.6

2.5

0.1 0.2 0.3 0.4 0.5 IL – Load Current – A

Figure 14

– Fall Time – ms

0.6 0.7 0.8 0.9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3.1

2.9

2.7

2.5

0.1 0.2 0.3 0.4 0.5 IL – Load Current – A

Figure 15

0.6 0.7 0.8 0.9

TPS2042, TPS2052

DUAL POWER-DISTRIBUTION SWITCHES

SLVS173A – AUGUST 1998 – REVISED APRIL 1999

TYPICAL CHARACTERISTICS

SUPPLY CURRENT, OUTPUT ENABLED

JUNCTION TEMPERATURE

100

Aµ

I(IN)

= 5 V

I(IN)

= 3.3 V

= 4 V

– Supply Current, Output Enabled –

I(IN)

–50 –25 0 25 50

TJ – Junction Temperature – °C

Figure 16

SUPPLY CURRENT, OUTPUT ENABLED

INPUT VOLTAGE

100

Aµ

TJ = 85°C

= 5.5 V

I(IN)

= 2.7 V

I(IN)

75 100 125 150

TJ = 125°C

SUPPLY CURRENT, OUTPUT DISABLED

JUNCTION TEMPERATURE

1000

900

I(IN)

= 4 V

= 2.7 V

800 700

600 500 400 300 200

– Supply Current, Output Disabled – nA

100

I(IN)

–100

–50 –25 0 25 50 75

TJ – Junction Temperature – °C

Figure 17

SUPPLY CURRENT, OUTPUT DISABLED

INPUT VOLTAGE

1000

800

TJ = 125°C

= 5.5 V = 5 V

100 125 150

TJ = 0°C

– Supply Current, Output Enabled –

I(IN)

2.5 3 3.5 4

TJ = –40°C

VI – Input Voltage – V

Figure 18

4.5

600

400

TJ = 25°C

200

– Supply Current, Output Disabled – nA

I(IN)

5 5.5 6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

–200

2.5 3 3.5 4 4.5

TJ = 85°C

TJ = –40°C

VI – Input Voltage – V

Figure 19

TJ = 25°C

TJ = 0°C

5 5.5 6

TPS2042, TPS2052 DUAL POWER-DISTRIBUTION SWITCHES

SLVS173A – AUGUST 1998 – REVISED APRIL 1999

TYPICAL CHARACTERISTICS

STATIC DRAIN-SOURCE ON-STATE RESISTANCE

Ω

175

150

125

100

– Static Drain-Source On-State Resistance – m

–50 –25 0 25 50 75

DS(on)

JUNCTION TEMPERATURE

IO = 0.5 A

TJ – Junction Temperature –°C

I(IN)

= 2.7 V

I(IN)

100 125 150

Figure 20

INPUT-TO-OUTPUT VOLTAGE

LOAD CURRENT

100

TA = 25°C

= 3.3 V

= 4.5 V = 5 V

STATIC DRAIN-SOURCE ON-STATE RESISTANCE

Ω

175

150

125

100

– Static Drain-Source On-State Resistance – m

DS(on)

2.5 3 3.5 4 4.5

INPUT VOLTAGE

IO = 0.5 A

TJ = 125°C

TJ = 85°C

TJ = 25°C

TJ = 0°C

TJ = –40°C

5 5.5 6

VI – Input Voltage – V

Figure 21

SHORT-CURCUIT OUTPUT CURRENT

INPUT VOLTAGE

0.95

– Input-to-Output Voltage – mV

I(OUTx)

–

I(IN)

0.1 0.2 0.4

I(IN)

IL – Load Current – A

Figure 22

= 3.3 V

I(IN)

= 2.7 V

I(IN)

= 5 V

I(IN)

= 4.5 V

0.5 0.6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

– Short-circuit Output Current – A

0.9

0.85

0.8

2.5 3 3.5 4

TJ = –40°C

TJ = 25°C

TJ = 125°C

4.5 5 65.5

VI – Input Voltage – V

Figure 23

TPS2042, TPS2052

DUAL POWER-DISTRIBUTION SWITCHES

SLVS173A – AUGUST 1998 – REVISED APRIL 1999

TYPICAL CHARACTERISTICS

1.2 TA = 25°C Load Ramp = 1 A/10 ms

1.175

1.15

Threshold Trip Current – A

1.125

1.1

2.5 3 3.5 4

2.5

2.4

THRESHOLD TRIP CURRENT

INPUT VOLTAGE

4.5 5 65.5

VI – Input Voltage – V

Figure 24

UNDERVOLTAGE LOCKOUT

JUNCTION TEMPERATURE

SHORT CIRCUIT OUTPUT CURRENT

JUNCTION TEMPERATURE

0.95

0.9

0.85

– Short-circuit Output Current – A

0.8 –50 –25 0 25 50

TJ – Junction Temperature – °C

CURRENT-LIMIT RESPONSE

500

450

sµ

400

= 4 V

I(IN)

= 2.7 V

I(IN)

Figure 25

PEAK CURRENT

= 5 V

I(IN)

75 100 125

= 5 V

I(IN)

TA = 25°C

Start Threshold

2.3

Stop Threshold

2.2

2.1

UVLO – Undervoltage Lockout – V

–50 –25 0 25 50 75

TJ – Junction Temperature – °C

Figure 26

350 300

250

200 150

Current Limit Response –

100

100 125 150

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

0 2.5 5 7.5

10 12.5

Peak Current – A

Figure 27

TPS2042, TPS2052 DUAL POWER-DISTRIBUTION SWITCHES

SLVS173A – AUGUST 1998 – REVISED APRIL 1999

TYPICAL CHARACTERISTICS

OVERCURRENT RESPONSE TIME (OCx)

sµ

Response Time –

PEAK CURRENT

= 5 V

I(IN)

TA = 25°C

Power Supply

2.7 V to 5.5 V

0 2.5 5 7.5

Peak Current – A

Figure 28

APPLICATION INFORMATION

TPS2042

0.1 µF

OC1

EN1

OC2

EN2

GND

Figure 29. Typical Application

OUT1

OUT2

10 12.5

0.1 µF 22 µF

Load

power-supply considerations

A 0.01-µF to 0.1-µF ceramic bypass capacitor between INx and GND, close to the device, is recommended. Placing a high-value electrolytic capacitor on the output pin(s) is recommended when the output load is heavy . This precaution reduces power-supply transients that may cause ringing on the input. Additionally , bypassing the output with a 0.01-µF to 0.1-µF ceramic capacitor improves the immunity of the device to short-circuit transients.

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TPS2042, TPS2052

DUAL POWER-DISTRIBUTION SWITCHES

SLVS173A – AUGUST 1998 – REVISED APRIL 1999

APPLICATION INFORMATION

overcurrent

A sense FET checks for overcurrent conditions. Unlike current-sense resistors, sense FET s do not increase the series resistance of the current path. When an overcurrent condition is detected, the device maintains a constant output current and reduces the output voltage accordingly . Complete shutdown occurs only if the fault is present long enough to activate thermal limiting.

Three possible overload conditions can occur. In the first condition, the output has been shorted before the device is enabled or before V and immediately switch into a constant-current output.

In the second condition, the short occurs while the device is enabled. At the instant the short occurs, very high currents may flow for a short time before the current-limit circuit can react. After the current-limit circuit has tripped (reached the overcurrent trip threshhold) the device switches into constant-current mode.

In the third condition, the load has been gradually increased beyond the recommended operating current. The current is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device is exceeded (see Figure 7). The TPS2042 and TPS2052 are capable of delivering current up to the current-limit threshold without damaging the device. Once the threshold has been reached, the device switches into its constant-current mode.

has been applied (see Figure 6). The TPS2042 and TPS2052 sense the short

I(IN)

OC response

The OC open-drain output is asserted (active low) when an overcurrent or overtemperature condition is encountered. The output will remain asserted until the overcurrent or overtemperature condition is removed. Connecting a heavy capacitive load to an enabled device can cause momentary false overcurrent reporting from the inrush current flowing through the device, charging the downstream capacitor. An RC filter of 500 µs (see Figure 30) can be connected to the OC capacitors on the output lowers the inrush current flow through the device during hot-plug events by providing a low impedance energy source, thereby reducing erroneous overcurrent reporting.

TPS2042

GND IN EN1

EN2

OC1 OUT1 OUT2

OC2

Figure 30. Typical Circuit for OC Pin and RC Filter for Damping Inrush OC Responses

pin to reduce false overcurrent reporting. Using low-ESR electrolytic

V+

pullup

GND IN EN1

EN2

TPS2042

OC1 OUT1 OUT2

OC2

V+

pullup

filter

To USB Controller

filter

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TPS2042, TPS2052 DUAL POWER-DISTRIBUTION SWITCHES

SLVS173A – AUGUST 1998 – REVISED APRIL 1999

APPLICATION INFORMATION

power dissipation and junction temperature

The low on-resistance on the n-channel MOSFET allows small surface-mount packages, such as SOIC, to pass large currents. The thermal resistances of these packages are high compared to that of power packages; it is good design practice to check power dissipation and junction temperature. The first step is to find r input voltage and operating temperature. As an initial estimate, use the highest operating ambient temperature of interest and read r

DS(on

)

Finally, calculate the junction temperature:

Where:

TA = Ambient Temperature °C R

θJA

Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees, repeat the calculation, using the calculated value as the new estimate. Two or three iterations are generally sufficient to get a reasonable answer.

= Thermal resistance SOIC = 172°C/W, PDIP = 106°C/W

from Figure 21. Next, calculate the power dissipation using:

DS(on)

)

DS(on)

at the

thermal protection

Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present for extended periods of time. The faults force the TPS2042 and TPS2052 into constant current mode, which causes the voltage across the high-side switch to increase; under short-circuit conditions, the voltage across the switch is equal to the input voltage. The increased dissipation causes the junction temperature to rise to high levels. The protection circuit senses the junction temperature of the switch and shuts it off. Hysteresis is built into the thermal sense circuit, and after the device has cooled approximately 20 degrees, the switch turns back on. The switch continues to cycle in this manner until the load fault or input power is removed.

The TPS2042 and TPS2052 implement a dual thermal trip to allow fully independent operation of the power distribution switches. In an overcurrent or short-circuit condition the junction temperature will rise. Once the die temperature rises to approximately 140°C, the internal thermal sense circuitry checks which power switch is in an overcurrent condition and turns that power switch off, thus isolating the fault without interrupting operation of the adjacent power switch. Should the die temperature exceed the first thermal trip point of 140°C and reach 160°C, both switches turn off. The OC overcurrent occurs.

open-drain output is asserted (active low) when overtemperature or

undervoltage lockout (UVLO)

An undervoltage lockout ensures that the power switch is in the off state at power up. Whenever the input voltage falls below approximately 2 V, the power switch will be quickly turned off. This facilitates the design of hot-insertion systems where it is not possible to turn off the power switch before input power is removed. The UVLO will also keep the switch from being turned on until the power supply has reached at least 2 V, even if the switch is enabled. Upon reinsertion, the power switch will be turned on with a controlled rise time to reduce EMI and voltage overshoots.

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TPS2042, TPS2052

DUAL POWER-DISTRIBUTION SWITCHES

SLVS173A – AUGUST 1998 – REVISED APRIL 1999

APPLICATION INFORMATION

universal serial bus (USB) applications

The universal serial bus (USB) interface is a 12-Mb/s, or 1.5-Mb/s, multiplexed serial bus designed for low-to-medium bandwidth PC peripherals (e.g., keyboards, printers, scanners, and mice). The four-wire USB interface is conceived for dynamic attach-detach (hot plug-unplug) of peripherals. Two lines are provided for differential data, and two lines are provided for 5-V power distribution.

USB data is a 3.3-V level signal, but power is distributed at 5 V to allow for voltage drops in cases where power is distributed through more than one hub across long cables. Each function must provide its own regulated 3.3 V from the 5-V input or its own internal power supply.

The USB specification defines the following five classes of devices, each differentiated by power-consumption requirements:

Hosts/self-powered hubs (SPH)

Bus-powered hubs (BPH)

Low-power, bus-powered functions

High-power, bus-powered functions

Self-powered functions

Self-powered and bus-powered hubs distribute data and power to downstream functions. The TPS2042 and TPS2052 can provide power-distribution solutions for many of these classes of devices.

host/self-powered and bus-powered hubs

Hosts and self-powered hubs have a local power supply that powers the embedded functions and the downstream ports (see Figure 31). This power supply must provide from 5.25 V to 4.75 V to the board side of the downstream connection under full-load and no-load conditions. Hosts and SPHs are required to have current-limit protection and must report overcurrent conditions to the USB controller. T ypical SPHs are desktop PCs, monitors, printers, and stand-alone hubs.

USB

Control

Power Supply

3.3 V 5 V

0.1 µF

†

TPS2042

OUT1

OC1

EN1

OC2

EN2

OUT2

GND

0.1 µF 68 µF

Downstream

USB Ports

D+ D–

BUS

GND

D+ D–

BUS

GND

†

May need RC filter (see Figure 36)

Figure 31. T ypical Two-Port USB Host/Self-Powered Hub

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TPS2042, TPS2052 DUAL POWER-DISTRIBUTION SWITCHES

SLVS173A – AUGUST 1998 – REVISED APRIL 1999

APPLICATION INFORMATION

host/self-powered and bus-powered hubs (continued)

Bus-powered hubs obtain all power from upstream ports and often contain an embedded function. The hubs are required to power up with less than one unit load. The BPH usually has one embedded function, and power is always available to the controller of the hub. If the embedded function and hub require more than 100 mA on power up, the power to the embedded function may need to be kept off until enumeration is completed. This can be accomplished by removing power or by shutting off the clock to the embedded function. Power switching the embedded function is not necessary if the aggregate power draw for the function and controller is less than one unit load. The total current drawn by the bus-powered device is the sum of the current to the controller, the embedded function, and the downstream ports, and it is limited to 500 mA from an upstream port.

low-power bus-powered functions and high-power bus-powered functions

Both low-power and high-power bus-powered functions obtain all power from upstream ports; low-power functions always draw less than 100 mA, and high-power functions must draw less than 100 mA at power up and can draw up to 500 mA after enumeration. If the load of the function is more than the parallel combination of 44 Ω and 10 µF at power up, the device must implement inrush current limiting (see Figure 32).

Power Supply

BUS

GND

D+ D–

10 µF

3.3 V

0.1 µF

TPS2042

OUT1

0.1 µF 10 µF

Internal Function

USB

Control

OC1

EN1

OC2

EN2

OUT2

GND

0.1 µF 10 µF

Figure 32. High-Power Bus-Powered Function

Internal Function

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TPS2042, TPS2052

DUAL POWER-DISTRIBUTION SWITCHES

SLVS173A – AUGUST 1998 – REVISED APRIL 1999

APPLICATION INFORMATION

USB power-distribution requirements

USB can be implemented in several ways, and, regardless of the type of USB device being developed, several power-distribution features must be implemented.

Hosts/self-powered hubs must: – Current-limit downstream ports – Report overcurrent conditions on USB V

Bus-powered hubs must: – Enable/disable power to downstream ports – Power up at <100 mA – Limit inrush current (<44 Ω and 10 µF)

Functions must: – Limit inrush currents – Power up at <100 mA

The feature set of the TPS2042 and TPS2052 allows them to meet each of these requirements. The integrated current-limiting and overcurrent reporting is required by hosts and self-powered hubs. The logic-level enable and controlled rise times meet the need of both input and output ports on bus-power hubs, as well as the input ports for bus-power functions (see Figure 33).

BUS

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SLVS173A – AUGUST 1998 – REVISED APRIL 1999

APPLICATION INFORMATION

TUSB2040

Hub Controller

Upstream Port

D + D –

GND

5 V

TPS2041

OC EN

1 µF

0.1 µF

SN75240

OUT

4.7 µF

C D

GND

5 V Power

Supply

TPS76333

3.3 V

GND

48-MHz Crystal

Tuning Circuit

4.7 µF

DP0 DM0

XTAL1

XTAL2

OCSOFF

GND

BUSPWR GANGED

DP1

DM1

DP2

DM2

DP3

DM3

DP4

DM4

PWRON1

OVRCUR1

PWRON2

OVRCUR2

PWRON3

OVRCUR3

PWRON4

OVRCUR4

Tie to TPS2041 EN

ABC

SN75240

ABC

SN75240

TPS2042

EN1

OUT1 OUT2

OC1

EN2

OC2

TPS2042

EN1

OUT1 OUT2

OC1

EN2

OC2

Input

0.1 µF

Ferrite Beads

Downstream

Ports D +

D – GND

5 V

†

33 µF

D + D –

GND

5 V

†

33 µF

D + D –

GND

5 V

†

33 µF

D + D –

GND

†

USB rev 1.1 requires 120 µF per hub.

Figure 33. Hybrid Self/Bus-Powered Hub Implementation

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33 µF

5 V

†

TPS2042, TPS2052

DUAL POWER-DISTRIBUTION SWITCHES

SLVS173A – AUGUST 1998 – REVISED APRIL 1999

APPLICATION INFORMATION

generic hot-plug applications (see Figure 34)

In many applications it may be necessary to remove modules or pc boards while the main unit is still operating. These are considered hot-plug applications. Such implementations require the control of current surges seen by the main power supply and the card being inserted. The most effective way to control these surges is to limit and slowly ramp the current and voltage being applied to the card, similar to the way in which a power supply normally turns on. Due to the controlled rise times and fall times of the TPS2042 and TPS2052, these devices can be used to provide a softer start-up to devices being hot-plugged into a powered system. The UVLO feature of the TPS2042 and TPS2052 also ensures the switch will be off after the card has been removed, and the switch will be off during the next insertion. The UVLO feature guarantees a soft start with a controlled rise time for every insertion of the card or module.

PC Board

Power

Supply

2.7 V to 5.5 V

1000 µF Optimum

0.1 µF

Overcurrent Response

TPS2042

GND IN

EN1 EN2

OC1

OUT1 OUT2

OC2

Block of Circuitry

Figure 34. Typical Hot-Plug Implementation

By placing the TPS2042 and TPS2052 between the VCC input and the rest of the circuitry , the input power will reach these devices first after insertion. The typical rise time of the switch is approximately 2.5 ms, providing a slow voltage ramp at the output of the device. This implementation controls system surge currents and provides a hot-plugging mechanism for any device.

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MECHANICAL DATA

D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PIN SHOWN

0.050 (1,27)

0.069 (1,75) MAX

0.020 (0,51)

0.014 (0,35) 8

0.010 (0,25)

0.004 (0,10)

DIM

0.157 (4,00)

0.150 (3,81)

PINS **

0.010 (0,25)

0.244 (6,20)

0.228 (5,80)

Seating Plane

0.004 (0,10)

0.008 (0,20) NOM

0°–8°

Gage Plane

0.010 (0,25)

0.044 (1,12)

0.016 (0,40)

A MAX

A MIN

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). D. Falls within JEDEC MS-012

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0.197

(5,00)

0.189

(4,80)

0.344

(8,75)

0.337

(8,55)

0.394

(10,00)

0.386

(9,80)

4040047/D 10/96

TPS2042, TPS2052

DUAL POWER-DISTRIBUTION SWITCHES

SLVS173A – AUGUST 1998 – REVISED APRIL 1999

MECHANICAL DATA

P (R-PDIP-T8) PLASTIC DUAL-IN-LINE PACKAGE

0.400 (10,60)

0.355 (9,02)

0.260 (6,60)

0.240 (6,10)

0.070 (1,78) MAX

0.020 (0,51) MIN

0.200 (5,08) MAX

0.125 (3,18) MIN

0.100 (2,54)

0.021 (0,53)

0.015 (0,38)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001

0.010 (0,25)

0.310 (7,87)

0.290 (7,37)

Seating Plane

0°–15°

0.010 (0,25) NOM

4040082/B 03/95

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PACKAGE OPTION ADDENDUM

www.ti.com

6-Dec-2006

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package

Drawing

Pins Package

Qty

Eco Plan

TPS2042D NRND SOIC D 8 75 Green (RoHS &

no Sb/Br)

TPS2042DG4 NRND SOIC D 8 75 Green (RoHS &

no Sb/Br)

TPS2042DR NRND SOIC D 8 2500 Green (RoHS &

no Sb/Br)

TPS2042DRG4 NRND SOIC D 8 2500 Green (RoHS &

no Sb/Br)

TPS2042P NRND PDIP P 8 50 Pb-Free

TPS2042PE4 NRND PDIP P 8 50 Pb-Free

TPS2052D NRND SOIC D 8 75 Green (RoHS &

no Sb/Br)

TPS2052DG4 NRND SOIC D 8 75 Green (RoHS &

no Sb/Br)

TPS2052DR NRND SOIC D 8 2500 Green (RoHS &

no Sb/Br)

TPS2052DRG4 NRND SOIC D 8 2500 Green (RoHS &

no Sb/Br)

TPS2052P NRND PDIP P 8 50 Pb-Free

TPS2052PE4 NRND PDIP P 8 50 Pb-Free

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

(RoHS)

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU N / A for Pkg Type

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU N / A for Pkg Type

(3)

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

6-Dec-2006

Addendum-Page 2

IMPORTANT NOTICE

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TEXAS INSTRUMENTS TPS2042, TPS2052 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual