Texas Instruments TPS2010APWP, TPS2010APWPR, TPS2010ADR, TPS2010AD, TPS2013ADR Datasheet

TPS2010A, TPS2011A, TPS2012A, TPS2013A

POWER-DISTRIBUTION SWITCHES

SLVS189A – DECEMBER 1998 – REVISED NOVEMBER 1999

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

33-mΩ (5-V Input) High-Side MOSFET
Switch

D

Short-Circuit and Thermal Protection

D

Operating Range . . . 2.7 V to 5.5 V

D

Logic-Level Enable Input

D

Typical Rise Time . . . 6.1 ms

D

Undervoltage Lockout

D

Maximum Standby Supply
Current ...10 µA

D

No Drain-Source Back-Gate Diode

D

Available in 8-pin SOIC and 14-Pin TSSOP
Packages

D

Ambient Temperature Range, –40°C to 85°C

D

2-kV Human-Body-Model, 200-V
Machine-Model ESD Protection

description

The TPS201xA family of power distribution switches is intended for applications where heavy capacitive loads
and short circuits are likely to be encountered. These devices are 50-mΩ N-channel MOSFET high-side power
switches. The switch is controlled by a logic enable compatible with 5-V logic and 3-V logic. Gate drive is
provided by an internal charge pump designed to control the power-switch rise times and fall times to minimize
current surges during switching. The charge pump requires no external components and allows operation from
supplies as low as 2.7 V.

When the output load exceeds the current-limit threshold or a short is present, the TPS201xA limits the output
current to a safe level by switching into a constant-current mode. When continuous heavy overloads and short
circuits increase the power dissipation in the switch, causing the junction temperature to rise, a thermal
protection circuit shuts off the switch to prevent damage. Recovery from a thermal shutdown is automatic once
the device has cooled sufficiently. Internal circuitry ensures the switch remains off until valid input voltage is
present.

The TPS201xA devices differ only in short-circuit current threshold. The TPS2010A limits at 0.3-A load, the
TPS201 1 at 0.9-A load, the TPS2012A at 1.5-A load, and the TPS2013A at 2.2-A load (see Available Options).
The TPS201xA is available in an 8-pin small-outline integrated-circuit (SOIC) package and in a 14-pin
thin-shrink small-outline package (TSSOP) and operates over a junction temperature range of –40°C to 125°C.

TPS201xA

TPS202x
TPS203x

33 mΩ, single

0.2 A – 2 A

0.2 A – 2 A

0.2 A – 2 A

TPS2014
TPS2015
TPS2041
TPS2051
TPS2045
TPS2055

80 mΩ, single

600 mA
1 A
500 mA
500 mA
250 mA
250 mA

GENERAL SWITCH CATALOG

TPS2042
TPS2052
TPS2046
TPS2056

80 mΩ, dual

500 mA
500 mA
250 mA
250 mA

TPS2100/1

260 mΩ

IN1 500 mA
IN2 10 mA

OUT

IN1
IN2

TPS2102/3/4/5

IN1 500 mA
IN2 100 mA

1.3 Ω

TPS2043
TPS2053
TPS2047
TPS2057

80 mΩ, triple

500 mA
500 mA
250 mA
250 mA

TPS2044
TPS2054
TPS2048
TPS2058

80 mΩ, quad

500 mA
500 mA
250 mA
250 mA

Copyright  1998, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

1
2
3
4

8
7
6
5

GND

IN
IN

EN

OUT
OUT
OUT
OUT

D PACKAGE

(TOP VIEW)

1
2
3
4
5
6
7

14
13
12
11
10

9
8

GND

IN
IN
IN
IN
IN

EN

OUT
OUT
OUT
OUT
OUT
OUT
OUT

PWP PACKAGE

(TOP VIEW)

TPS2010A, TPS2011A, TPS2012A, TPS2013A
POWER-DISTRIBUTION SWITCHES

SLVS189A – DECEMBER 1998 – REVISED NOVEMBER 1999

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

AVAILABLE OPTIONS

RECOMMENDED

TYPICAL SHORT-CIRCUIT

PACKAGED DEVICES

T

A

ENABLE

MAXIMUM CONTINUOUS

LOAD CURRENT

(A)

CURRENT LIMIT AT 25°C

(A)

SMALL OUTLINE

(D)

†

TSSOP
(PWP)

‡

0.2 0.3 TPS2010AD TPS2010APWPR

°

°

0.6 0.9 TPS2011AD TPS2011APWPR

–

40°C to 85°C

Active lo

w

1 1.5 TPS2012AD TPS2012APWPR

1.5 2.2 TPS2013AD TPS2013APWPR

†

The D package is available taped and reeled. Add an R suffix to device type (e.g., TPS2010DR)

‡

The PWP package is only available left-end taped-and-reeled.

TPS201xA functional block diagram

OUTIN

EN

GND

Current

Limit

Driver

UVLO

Charge

Pump

CS

Thermal

Sense

Power Switch

†

†

Current Sense

Terminal Functions

TERMINAL

NAME

NO.

D

NO.

PWP

I/O DESCRIPTION

EN 4 7 I Enable input. Logic low turns on power switch.
GND 1 1 I Ground
IN 2, 3 2–6 I Input voltage
OUT 5, 6, 7, 8 8–14 O Power-switch output

TPS2010A, TPS2011A, TPS2012A, TPS2013A

POWER-DISTRIBUTION SWITCHES

SLVS189A – DECEMBER 1998 – REVISED NOVEMBER 1999

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

detailed description

power switch

The power switch is an N-channel MOSFET with a maximum on-state resistance of 50 mΩ (V

I(IN)

= 5 V).
Configured as a high-side switch, the power switch prevents current flow from OUT to IN and IN to OUT when
disabled.

charge pump

An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate
of the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requires
very little supply current.

driver

The driver controls the gate voltage of the power switch. T o limit large current surges and reduce the associated
electromagnetic interference (EMI) produced, the driver incorporates circuitry that controls the rise times and
fall times of the output voltage. The rise and fall times are typically in the 2-ms to 9-ms range.

enable (EN

)

The logic enable disables the power switch, the bias for the charge pump, driver, and other circuitry to reduce
the supply current to less than 10 µA when a logic high is present on EN . A logic zero input on EN restores bias
to the drive and control circuits and turns the power on. The enable input is compatible with both TTL and CMOS
logic levels.

current sense

A sense FET monitors the current supplied to the load. The sense FET measures current more efficiently than
conventional resistance methods. When an overload or short circuit is encountered, the current-sense circuitry
sends a control signal to the driver. The driver, in turn, reduces the gate voltage and drives the power FET into
its saturation region, which switches the output into a constant current mode and holds the current constant
while varying the voltage on the load.

thermal sense

An internal thermal-sense circuit shuts off the power switch when the junction temperature rises to
approximately 140°C. Hysteresis is built into the thermal sense circuit. After the device has cooled
approximately 20°C, the switch turns back on. The switch continues to cycle off and on until the fault is removed.

undervoltage lockout

A voltage sense circuit monitors the input voltage. When the input voltage is below approximately 2 V , a control
signal turns off the power switch.

TPS2010A, TPS2011A, TPS2012A, TPS2013A
POWER-DISTRIBUTION SWITCHES

SLVS189A – DECEMBER 1998 – REVISED NOVEMBER 1999

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Input voltage range, V

I(IN)

(see Note 1) –0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, V

O(OUT)

(see Note 1) –0.3 V to V

I(IN)

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

I(EN)

–0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current, I

O(OUT)

internally limited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating virtual junction temperature range, T

J

–40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . .

Electrostatic discharge (ESD) protection: Human body model 2 kV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Machine model 200V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltages are with respect to GND.

DISSIPATION RATING TABLE

PACKAGE

TA ≤ 25°C

POWER RATING

DERATING FACTOR

ABOVE TA = 25°C

TA = 70°C

POWER RATING

TA = 85°C

POWER RATING

D 725 mW 5.8 mW/°C 464 mW 377 mW

PWP 700 mW 5.6 mW/°C 448 mW 364 mW

recommended operating conditions

MIN MAX UNIT

p

V

I(IN)

2.7 5.5 V

Input voltage

V

I(EN)

0 5.5 V

TPS2010A 0 0.2

p

TPS2011A 0 0.6

Continuous output current, I

O

TPS2012A 0 1

A

TPS2013A 0 1.5

Operating virtual junction temperature, T

J

–40 125 °C

TPS2010A, TPS2011A, TPS2012A, TPS2013A

POWER-DISTRIBUTION SWITCHES

SLVS189A – DECEMBER 1998 – REVISED NOVEMBER 1999

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating junction temperature range, V

I(IN)

= 5.5 V,

I

O

= rated current, EN = 0 V (unless otherwise noted)

power switch

PARAMETER

TEST CONDITIONS

†

MIN TYP MAX UNIT

V

I(IN)

= 5 V, TJ = 25°C, IO = 1.5 A 33 36

V

I(IN)

= 5 V, TJ = 85°C, IO = 1.5 A 38 46

V

I(IN)

= 5 V, TJ = 125°C, IO = 1.5 A 44 50

V

I(IN)

= 3.3 V, TJ = 25°C, IO = 1.5 A 37 41

V

I(IN)

= 3.3 V, TJ = 85°C, IO = 1.5 A 43 52

V

I(IN)

= 3.3 V, TJ = 125°C, IO = 1.5 A 51 61

r

DS(on)

Static drain-source on-state resistance

V

I(IN)

= 5 V, TJ = 25°C, IO = 0.18 A 30 34

mΩ

V

I(IN)

= 5 V, TJ = 85°C, IO = 0.18 A 35 41

V

I(IN)

= 5 V, TJ = 125°C, IO = 0.18 A 39 47

V

I(IN)

= 3.3 V, TJ = 25°C, IO = 0.18 A 33 37

V

I(IN)

= 3.3 V, TJ = 85°C, IO = 0.18 A 39 46

V

I(IN)

= 3.3 V, TJ = 125°C, IO = 0.18 A 44 56

p

V

I(IN)

= 5.5 V,

CL = 1 µF,

TJ = 25°C,
RL = 10 Ω

6.1

trRise time, output

V

I(IN)

= 2.7 V,

CL = 1 µF,

TJ = 25°C,
RL = 10 Ω

8.6

ms

p

V

I(IN)

= 5.5 V,

CL = 1 µF,

TJ = 25°C,
RL = 10 Ω

3.4

tfFall time, output

V

I(IN)

= 2.7 V,

CL = 1 µF,

TJ = 25°C,
RL = 10 Ω

3

ms

†

Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.

enable input (EN)

PARAMETER TEST CONDITIONS

MIN TYP MAX UNIT

V

IH

High-level input voltage 2.7 V ≤ V

I(IN)

≤ 5.5 V 2 V

p

4.5 V ≤ V

I(IN)

≤ 5.5 V 0.8

VILLow-level in ut voltage

2.7 V ≤ V

I(IN)

≤ 4.5 V 0.5

V

I

I

Input current EN = 0 V or EN = V

I(IN)

–0.5 0.5 µA

t

on

Turnon time CL = 100 µF, RL = 10 Ω 20

t

off

Turnoff time CL = 100 µF, RL = 10 Ω 40

ms

current limit

PARAMETER

TEST CONDITIONS

†

MIN TYP MAX UNIT

TPS2010A 0.22 0.3 0.4

p

TJ = 25°C, VI = 5.5 V,

TPS2011A 0.66 0.9 1.1

IOSShort-circuit output current

OUT

connected to

GND

,

D

evice enable

into short circuit

TPS2012A 1.1 1.5 1.8

A

Device enable into short circuit

TPS2013A 1.65 2.2 2.7

†

Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.

TPS2010A, TPS2011A, TPS2012A, TPS2013A
POWER-DISTRIBUTION SWITCHES

SLVS189A – DECEMBER 1998 – REVISED NOVEMBER 1999

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating junction temperature range, V

I(IN)

= 5.5 V,

I

O

= rated current, EN = 0 V (unless otherwise noted) (continued)

supply current

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

pp

p

TJ = 25°C 0.3 1

Supply current, low-level output

No Load on OUT

EN = V

I(IN)

–40°C ≤ TJ ≤ 125°C 10

µ

A

pp

p

TJ = 25°C 58 75

Supply current, high-level output

No Load on OUT

EN

= 0

V

–40°C ≤ TJ ≤ 125°C 75 100

µ

A

Leakage current OUT connected to ground EN = V

I(IN)

–40°C ≤ TJ ≤ 125°C 10 µA

undervoltage lockout

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Low-level input voltage 2 2.5 V
Hysteresis TJ = 25°C 100 mV

TPS2010A, TPS2011A, TPS2012A, TPS2013A

POWER-DISTRIBUTION SWITCHES

SLVS189A – DECEMBER 1998 – REVISED NOVEMBER 1999

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

RL CL

OUT

t

r

t

f

90%

90%

10%

10%

50%

50%

90%

10%

V

O(OUT)

V

I(EN)

V

O(OUT)

VOLTAGE WAVEFORMS

TEST CIRCUIT

t

on

t

off

Figure 1. Test Circuit and Voltage Waveforms

Table of Timing Diagrams

FIGURE

Turnon Delay and Rise TIme 2
Turnoff Delay and Fall Time 3
Turnon Delay and Rise TIme with 1-µF Load 4
Turnoff Delay and Rise TIme with 1-µF Load 5
Device Enabled into Short 6
TPS2010A, TPS201 1A, TPS2012A, and TPS2013A, Ramped Load on Enabled Device 7, 8, 9, 10
TPS2013A, Inrush Current 11

7.9-Ω Load Connected to an Enabled TPS2010A Device 12

3.7-Ω Load Connected to an Enabled TPS2010A Device 13

3.7-Ω Load Connected to an Enabled TPS2011A Device 14

2.6-Ω Load Connected to an Enabled TPS2011A Device 15

2.6-Ω Load Connected to an Enabled TPS2012A Device 16

1.2-Ω Load Connected to an Enabled TPS2012A Device 17

1.2-Ω Load Connected to an Enabled TPS2013A Device 18

0.9-Ω Load Connected to an Enabled TPS2013A Device 19