Texas Instruments TP3056BN, TP3056BDWR, TP3056BDW Datasheet

TP3056B

MONOLITHIC SERIAL INTERFACE

COMBINED PCM CODEC AND FILTER

SLWS072A – MAY 1998 – REVISED AUGUST 1998

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Complete PCM Codec and Filtering
Systems Include:
– Transmit High-Pass and Low-Pass

Filtering

– Receive Low-Pass Filter With (sin x)/x

Correction

– Active RC Noise Filters
– µ-Law and A-Law Compatible Coder and

Decoder
– Internal Precision Voltage Reference
– Serial I/O Interface
– Internal Autozero Circuitry

D

µ-Law/A-Law Operation Pin-Selectable

D

±5-V Operation

D

Low Operating Power . . . 60 mW T yp

D

Power-Down Mode ...5 mW Typ

D

Automatic Power Down

D

TTL- or CMOS-Compatible Digital Interface

D

Maximizes Line Interface Card Circuit
Density

description

The TP3056B monolithic serial interface
combined PCM codec and filter device is
comprised of a single-chip PCM codec (pulse
code-modulated encoder and decoder) and
analog filters. This device provides all the
functions required to interface a full-duplex
(2-wire) voice telephone circuit with a TDM
(time-division-multiplexed) system. Primary
applications include:

• Line interface for digital transmission and

switching of T1/E1 carrier, PABX, and central
office telephone systems

• Subscriber line concentrators

• Digital-encryption systems

• Digital voice-band data-storage systems

• Digital signal processing

The TP3056B is designed to perform the transmit encoding (A/D conversion) and receive decoding (D/A
conversion), and the appropriate filtering of analog signals in a PCM system. This device is intended to be used
at the analog termination of a PCM line or trunk. It requires a master clock of 2.048 MHz, a transmit/receive data
clock that is synchronous with the master clock (but can vary from 64 kHz to 2.048 MHz), and transmit and
receive frame-sync pulses. The TP3056B contains patented circuitry to achieve low transmit channel idle noise
and is not recommended for applications in which the composite signals on the transmit side are below
–55 dBm0.

This device, available in 16-pin N PDIP (plastic dual-in-line package) and 16-pin DW SOIC (small outline IC)
packages, is characterized for operation from 0°C to 70°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

Copyright  1998, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

1
2
3
4
5
6
7
8

16
15
14
13
12
11
10

9

V

BB

ANLG GND

VFRO

V

CC

FSR

DR

ASEL

PDN

VFXI+
VFXI–
GSX
TSX
FSX
DX
BCLK
MCLK

DW OR N PACKAGE

(TOP VIEW)

TP3056B
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER

SLWS072A – MAY 1998 – REVISED AUGUST 1998

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

GSX

14

V

BB

ANLG GNDV

CC

412

–5 V

FSX

5 V

9 8 10 7 125

MCLK PDN BCLK ASEL FSR

TSX

13

Power

Amplifier

Timing and Control

DR

6

CLK

Receive

Regulator

S/H

DAC

RC Active

Filter

11

DX

OE

Transmit

Regulator

Voltage

Reference

S/H

DAC

Switched­Capacitor

Band-Pass Filter

RC

Active Filter

3

VFRO

+

–

VFXI+

16

15
VFXI–

Analog

Input

Switched­Capacitor

Low-Pass Filter

Analog
Output

Digital

Output

Digital

Input

TP3056B

MONOLITHIC SERIAL INTERFACE

COMBINED PCM CODEC AND FILTER

SLWS072A – MAY 1998 – REVISED AUGUST 1998

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

NAME NO.

I/O

DESCRIPTION

ANLG GND 2 Analog ground. All signals are referenced to ANLG GND.
ASEL 7 I A-law/µ-law select. When ASEL is connected to VCC, A-law is selected. When ASEL is connected to GND or VBB,

µ-law is selected.

BCLK 10 I Transmit/receive bit clock. BCLK shifts PCM data out on DX during transmit and shifts PCM data in through DR

during receive. BCLK can vary from 64 kHz to 2.048 MHz, but must be synchronous with MCLK.
DR 6 I Receive data input. PCM data is shifted into DR at the trailing edge of the BCLK following the FSR leading edge.
DX 11 O DX is the 3-state PCM data output that is enabled by FSX. Data is shifted out on the rising edge of BCLK.
FSR 5 I Receive-frame sync pulse input. FSR enables BCLK to shift PCM data in DR. FSR is an 8-kHz pulse train (see

Figures 1 and 2 for timing details).
FSX 12 I Transmit-frame sync pulse. FSX enables BCLK to shift out the PCM data on DX. FSX is an 8-kHz pulse train (see

Figures 1 and 2 for timing details).
GSX 14 O Analog output of the transmit input amplifier . GSX is used to set gain externally.
MCLK 9 I Transmit/receive master clock. MCLK must be 2.048 MHz.
PDN 8 I Power down. When PDN is connected high, the device is powered down. When PDN is connected low or left

floating, the device is powered up. PDN is internally tied low.
TSX 13 O Transmit channel time-slot strobe. TSX is an open-drain output that pulses low during the encoder time slot.
V

BB

1 Negative power supply. VBB = –5 V ±5%

V

CC

4 Positive power supply. VCC = 5 V ±5%
VFRO 3 O Analog output of the receive channel power amplifier
VFXI+ 16 I Noninverting input of the transmit input amplifier
VFXI– 15 I Inverting input of the transmit input amplifier

TP3056B
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER

SLWS072A – MAY 1998 – REVISED AUGUST 1998

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†

Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Supply voltage, VBB (see Note 1) –7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range at any analog input or output VCC +0.3 V to VBB –0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range at any digital input or output VCC +0.3 V to ANLG GND –0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous total dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range: TP3056B 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: DW or N package 260°C. . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltages are with respect to GND.

DISSIPATION RATING TABLE

PACKAGE

TA ≤ 25°C

POWER RATING

DERATING FACTOR

ABOVE TA = 25°C

TA = 70°C

POWER RATING

TA = 85°C

POWER RATING

DW 1025 mW 8.2 mW/°C 656 mW 533 mW

N 1150 mW 9.2 mW/°C 736 mW 598 mW

recommended operating conditions (see Note 2)

MIN NOM MAX UNIT

Supply voltage, V

CC

4.75 5 5.25 V

Supply voltage, V

BB

–4.75 –5 –5.25 V

High-level input voltage, V

IH

2.2 V

Low-level input voltage, V

IL

0.6 V

Common-mode input voltage range, V

ICR

‡

±2.5 V

Load resistance, GSX, R

L

10 kΩ

Load capacitance, GSX, C

L

50 pF

Operating free-air temperature, T

A

0 70 °C

‡

Measured with CMRR > 60 dB

NOTE 2: T o avoid possible damage to these CMOS devices and resulting reliability problems, the power-up procedure described in the device

power-up sequence paragraphs later in this document should be followed.

electrical characteristics over recommended ranges of supply voltage operating free-air
temperature range, in A-law and µ-law modes (unless otherwise noted)

supply current

TP3056B

PARAMETER

TEST CONDITIONS

MIN TYP§MAX

UNIT

pp

Power down

0.5 1

ICCSupply current from V

CC

Operating

No load

6 9

mA

pp

Power down

0.5 1

IBBSupply current from V

BB

Operating

No load

6 9

mA

§

All typical values are at VCC = 5 V, VBB = –5 V , and TA = 25

°C.

TP3056B

MONOLITHIC SERIAL INTERFACE

COMBINED PCM CODEC AND FILTER

SLWS072A – MAY 1998 – REVISED AUGUST 1998

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics at VCC = 5 V ±5%, V

BB

= – 5 V ±5%, GND at 0 V, TA = 25°C (unless

otherwise noted)

digital interface

PARAMETER TEST CONDITIONS MIN MAX UNIT

V

OH

High-level output voltage DX IH = -3.2 mA 2.4 V

p

DX IL = 3.2 mA 0.4

VOLLow-level output voltage

TSX IL = 3.2 mA, Drain open 0.4

V

I

IH

High-level input current VI = VIH to V

CC

±10 µA

I

IL

Low-level input current All digital inputs VI = GND to V

IL

±10 µA

I

OZ

Output current in high-impedance state DX VO = GND to V

CC

±10 µA

analog interface with transmit amplifier input

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

V

ICR

‡

Common-mode input voltage range ±2.5 V

I

I

Input current VFXI+ or VFXI – VI = –2.5 V to 2.5 V ±200 nA

r

i

Input resistance VFXI+ or VFXI – VI = –2.5 V to 2.5 V 10 MΩ

A

V

Open-loop voltage amplification VFXI+ to GSX 5000

B

I

Unity-gain bandwidth GSX 1 2 MHz

V

IO

Input offset voltage VFXI+ or VFXI – ±20 mV
CMRR Common-mode rejection ratio 60 dB
K

SVR

Supply-voltage rejection ratio 60 dB

†

All typical values are at VCC = 5 V, VBB = –5 V , and TA = 25°C.

‡

Measured with CMRR > 60 dB.

analog interface with receive amplifier output

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

Receive output drive voltage RL = 10 kΩ ±2.5 V
Output resistance VFRO 1 3 Ω
Load resistance VFRO = ±2.5 V 600 Ω
Load capacitance VFRO to GND 500 pF
Output dc offset voltage VFRO to GND ±200 mV

†

All typical values are at VCC = 5 V, VBB = –5 V , and TA = 25°C.

TP3056B
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER

SLWS072A – MAY 1998 – REVISED AUGUST 1998

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

operating characteristics, over operating free-air temperature range, V

CC

= 5 V ±5%,

V

BB

= –5 V±5%, GND at 0 V , V

I

= 1.2276 V, f = 1.02 kHz, transmit input amplifier connected for unity

gain, noninverting, in A-law and µ-law modes, (unless otherwise noted)

filter gains and tracking errors

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

Maximum peak transmit

µ-law 3.17 dBm0 2.501

overload level

A-law 3.14 dBm0 2.492

V

Transmit filter gain, absolute‡ (at 0 dBm0) TA = 25°C – 0.15 0.15 dB

f = 16 Hz –40
f = 50 Hz –30
f = 60 Hz –26
f = 200 Hz –1.8 –0.1
f = 300 Hz to 3000 Hz –0.15 0.15

Transmit filter gain, relative to absolute

‡

f = 3300 Hz –0.35 0.05

dB

f = 3400 Hz –0.8 0
f = 4000 Hz –14
f ≥ 4600 Hz

(measure response from 0 Hz to 4000 Hz)

–32

Absolute‡ transmit gain variation with
temperature and supply voltage relative to
absolute transmit gain

–0.1 0.1 dB

3 dBm0 ≥ input level

≥ –40 dBm0

±0.2

Transmit gain tracking error with level

Sinusoidal test method,
Reference level = –10 dBm0

–40 dBm0 > input
level ≥ –50 dBm0

±0.4

dB

–50 dBm0 > input
level ≥ –55 dBm0

±0.8

Receive filter gain, absolute‡ (at 0 dBm0)

Input is digital code sequence for 0-dBm0 signal,
TA = 25°C

–0.15 0.15 dB

f = 0 Hz to 3000 Hz, TA = 25°c –0.15 0.15
f = 3300 Hz –0.35 0.05

Receive filter gain, relative to absolute

‡

f = 3400 Hz –0.8 0

dB

f = 4000 Hz –14

Absolute‡ receive gain variation with temperature
and supply voltage

TA = full range, See Note 3 –0.1 0.1 dB

Sinusoidal test method;

3 dBm0 ≥ input level
≥ –40 dBm0

±0.2

Receive gain tracking error with level

reference input PCM code
corresponds to an ideally

–40 dBm0 > input
level ≥ –50 dBm0

±0.4

dB

encoded –10 dBm0 signal

–50 dBm0 > input
level ≥ –55 dBm0

±0.8

Pseudo-noise test method;

3 dBm0 ≥ input level

≥ –40 dBm0

±0.25

Transmit and receive gain tracking error with
level (A-law, CCITT G 712)

Pseudo noise test method

reference input PCM code
corresponds to an ideally

–40 dBm0 > input
level ≥ –50 dBm0

±0.3

dB

encoded –10 dBm0 signal

–50 dBm0 > input
level ≥ –55 dBm0

±0.45

†

All typical values are at VCC = 5 V, VBB = –5 V , and TA = 25°C.

‡

Absolute rms signal levels are defined as follows: VI = 1.2276 V = 0 dBm0 = 4 dBm at f = 1.02 kHz with RL = 600 Ω.

NOTE 3: Full range for the TP3056B is 0°C to 70°C.