Texas instruments TMS320VC5401 Data Manual

TMS320VC5401 Fixed-Point

Digital Signal Processor

Data Manual

Literature Number: SPRS153D

December 2000 − Revised October 2008

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Revision History

REVISION HISTORY

This data sheet revision history highlights the technical changes made to the SPRS153C device-specific data sheet to make it an SPRS153D revision.

Scope: This document has been reviewed for technical accuracy; the technical content is up-to-date as of the specified release date with the following changes.

PAGE(S)

NO.

15 Table 2−2, Signal Descriptions:

− Updated DESCRIPTION of TRST

− Added footnote about TRST

80 Section 6, Mechanical Data:

− Moved “Package Thermal Resistance Characteristics” section (Section 5.4 in SPRS153C) to this section

− Added Section 6.2, Packaging Information

− Mechanical drawings will be appended to this document via an automated process

ADDITIONS/CHANGES/DELETIONS

December 2000 − Revised October 2008 SPRS153D

Revision History

December 2000 − Revised October 2008SPRS153D

Contents

Section Page

1 TMS320VC5401 Features 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Introduction 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 Description 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 Pin Assignments 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.1 Terminal Assignments for the GGU Package 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.2 Pin Assignments for the PGE Package 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3 Signal Descriptions 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 Functional Overview 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1 Memory 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.1 On-Chip ROM With Bootloader 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.2 On-Chip RAM 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.3 On-Chip Memory Security 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2 Memory Map 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.1 Relocatable Interrupt Vector Table 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.2 Extended Program Memory 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3 On-Chip Peripherals 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3.1 Software-Programmable Wait-State Generator 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3.2 Programmable Bank-Switching 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4 Parallel I/O Ports 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4.1 Enhanced 8-Bit Host-Port Interface (HPI8) 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5 Multichannel Buffered Serial Ports (McBSPs) 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5.1 Programmable McBSP Functions 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5.2 Enhanced McBSPs 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.6 Hardware Timer 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.7 Clock Generator 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.8 DMA Controller 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.8.1 Features 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.8.2 DMA Memory Map 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.8.3 DMA Priority Level 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.8.4 DMA Source/Destination Address Modification 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.8.5 DMA in Autoinitialization Mode 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.8.6 DMA Transfer Counting 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.8.7 DMA Transfer in Doubleword Mode 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.8.8 DMA Channel Index Registers 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.8.9 DMA Interrupts 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.8.10 DMA Controller Synchronization Events 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.8.11 DMA Channel Interrupt Selection 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.9 Memory-Mapped Registers 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.10 McBSP Control Registers and Subaddresses 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.11 DMA Subbank Addressed Registers 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.12 Interrupts 42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 Documentation Support 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1 Device and Development Tool Support Nomenclature 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

December 2000 − Revised October 2008 SPRS153D

Contents

Section Page

5 Electrical Specifications 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.1 Absolute Maximum Ratings 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2 Recommended Operating Conditions 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3 Electrical Characteristics 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.4 Timing Parameter Symbology 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.5 Internal Oscillator With External Crystal 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.6 Clock Options 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.6.1 Divide-By-Two Clock Option (PLL Disabled) 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.6.2 Multiply-By-N Clock Option (PLL Enabled) 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.7 Memory and Parallel I/O Interface Timing 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.7.1 Memory Read 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.7.2 Memory Write 54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.7.3 I/O Read 56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.7.4 I/O Write 57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.8 Ready Timing for Externally Generated Wait States 58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.9 HOLD

and HOLDA Timings 62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.10 Reset, BIO, Interrupt, and MP/MC Timings 63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.11 Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Timings 65. . . . . . . . . . . . . . . . .

5.12 External Flag (XF) and TOUT Timings 66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.13 Multichannel Buffered Serial Port (McBSP) Timing 67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.13.1 McBSP Transmit and Receive Timings 67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.13.2 McBSP General-Purpose I/O Timing 69. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.13.3 McBSP Transmit and Receive Timing Using CLKR/X as a Clock Source Input

to the Sample Rate Generator (SRGR) 70. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.13.4 McBSP as SPI Master or Slave Timing 72. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.14 Host-Port Interface (HPI8) Timing 76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6 Mechanical Data 80. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.1 Package Thermal Resistance Characteristics 80. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2 Packaging Information 80. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

December 2000 − Revised October 2008SPRS153D

Figures

List of Figures

Figure Page

2−1 144-Ball GGU MicroStar BGA (Bottom View) 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−2 144-Pin PGE Low-Profile Quad Flatpack (Top View) 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−1 TMS320VC5401 Functional Block Diagram 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−2 Memory Map 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−3 Processor Mode Status (PMST) Register 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−4 Extended Program Memory 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−5 Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h] 26. . .

3−6 Software Wait-State Control Register (SWCR) [MMR Address 002Bh] 27. . . . . . . . . . . . . . . . . . . . . . .

3−7 Bank-Switching Control Register (BSCR), MMR Address 0029h 27. . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−8 HPI8 Memory Map 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−9 Pin Control Register (PCR) 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−10 DMA Memory Map 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−11 IFR and IMR Registers 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−1 3.3-V Test Load Circuit 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−2 Internal Oscillator With External Crystal 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−3 External Divide-by-Two Clock Timing 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−4 External Multiply-by-One Clock Timing 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−5 Memory Read (MSTRB = 0) 53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−6 Memory Write (MSTRB = 0) 55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−7 Parallel I/O Port Read (IOSTRB = 0) 56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−8 Parallel I/O Port Write (IOSTRB = 0) 57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−9 Memory Read With Externally Generated Wait States 58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−10 Memory Write With Externally Generated Wait States 59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−11 I/O Read With Externally Generated Wait States 60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−12 I/O Write With Externally Generated Wait States 61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−13 HOLD and HOLDA Timings (HM = 1) 62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−14 Reset and BIO Timings 63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−15 Interrupt Timing 64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−16 MP/MC Timing 64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−17 IAQ and IACK Timings 65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−18 XF Timing 66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−19 TOUT Timing 66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−20 McBSP Receive Timings 68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−21 McBSP Transmit Timings 68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−22 McBSP General-Purpose I/O Timings 69. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−23 McBSP Sample Rate Generator Timings 71. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

December 2000 − Revised October 2008 SPRS153D

Figures

Figure Page

5−24 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 72. . . . . . . . . . . . . . . . . . . . . . . .

5−25 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 73. . . . . . . . . . . . . . . . . . . . . . . .

5−26 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 74. . . . . . . . . . . . . . . . . . . . . . . .

5−27 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 75. . . . . . . . . . . . . . . . . . . . . . . .

5−28 Using HDS

to Control Accesses (HCS Always Low) 78. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−29 Using HCS to Control Accesses 79. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−30 HINT Timing 79. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−31 GPIOx Timings 79. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

December 2000 − Revised October 2008SPRS153D

Tables

List of Tables

Table Page

2−1 Terminal Assignments for the TMS320VC5401GGU (144-Pin BGA Package) 13. . . . . . . . . . . . . . . .

2−2 Signal Descriptions 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−1 Standard On-Chip ROM Layout 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−2 Processor Mode Status (PMST) Register Bit Fields 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−3 Software Wait-State Register (SWWSR) Bit Fields 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−4 Software Wait-State Control Register (SWCR) Bit Fields 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−5 Bank-Switching Control Register (BSCR) Fields 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−6 Sample Rate Generator Clock Source Selection 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−7 Clock Mode Settings at Reset 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−8 DMA Interrupts 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−9 DMA Synchronization Events 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−10 DMA Channel Interrupt Selection 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−11 CPU Memory-Mapped Registers 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−12 Peripheral Memory-Mapped Registers 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−13 McBSP Control Registers and Subaddresses 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−14 DMA Subbank Addressed Registers 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−15 Interrupt Locations and Priorities 42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−16 IFR and IMR Register Bit Fields 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−1 Input Clock Frequency Characteristics 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−2 Divide-By-2 Clock Option Timing Requirements 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−3 Divide-By-2 Clock Option Switching Characteristics 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−4 Multiply-By-N Clock Option Timing Requirements 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−5 Multiply-By-N Clock Option Switching Characteristics 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−6 Memory Read Timing Requirements 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−7 Memory Read Switching Characteristics 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−8 Memory Write Switching Characteristics 54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−9 I/O Read Timing Requirements 56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−10 I/O Read Switching Characteristics 56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−11 I/O Write Switching Characteristics 57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−12 Ready Timing Requirements for Externally Generated Wait States 58. . . . . . . . . . . . . . . . . . . . . . . . .

5−13 Ready Switching Characteristics for Externally Generated Wait States 58. . . . . . . . . . . . . . . . . . . . . .

5−14 HOLD and HOLDA Timing Requirements 62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−15 HOLD and HOLDA Switching Characteristics 62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−16 Reset, BIO, Interrupt, and MP/MC Timing Requirements 63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−17 Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Switching Characteristics 65. . . .

5−18 External Flag (XF) and TOUT Switching Characteristics 66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−19 McBSP Transmit and Receive Timing Requirements 67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−20 McBSP Transmit and Receive Switching Characteristics 67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−21 McBSP General-Purpose I/O Timing Requirements 69. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−22 McBSP General-Purpose I/O Switching Characteristics 69. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−23 McBSP Sample Rate Generator Timing Requirements 70. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−24 McBSP Sample Rate Generator Switching Characteristics 70. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

December 2000 − Revised October 2008 SPRS153D

Tables

Table Page

5−25 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) 72. . . . . . . . . .

5−26 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0) 72. . . . . .

5−27 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) 73. . . . . . . . . .

5−28 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0) 73. . . . . . .

5−29 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) 74. . . . . . . . . .

5−30 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1) 74. . . . . .

5−31 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) 75. . . . . . . . . .

5−32 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) 75. . . . . . .

5−33 HPI8 Timing Requirements 76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−34 HPI8 Switching Characteristics 77. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6−1 Thermal Resistance Characteristics 80. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

December 2000 − Revised October 2008SPRS153D

1 TMS320VC5401 Features

Features

D Advanced Multibus Architecture With

Three Separate 16-Bit Data Memory Buses and One Program Memory Bus

D 40-Bit Arithmetic Logic Unit (ALU),

Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators

D 17- × 17-Bit Parallel Multiplier Coupled to a

40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation

D Compare, Select, and Store Unit (CSSU) for

the Add/Compare Selection of the Viterbi Operator

D Exponent Encoder to Compute an

Exponent Value of a 40-Bit Accumulator Value in a Single Cycle

D Two Address Generators With Eight

Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)

D Data Bus With a Bus-Holder Feature D Extended Addressing Mode for 1M × 16-Bit

Maximum Addressable External Program Space

D 4K x 16-Bit On-Chip ROM D 8K x 16-Bit Dual-Access On-Chip RAM D Single-Instruction-Repeat and

Block-Repeat Operations for Program Code

D Block-Memory-Move Instructions for

Efficient Program and Data Management

D Instructions With a 32-Bit Long Word

Operand

D Instructions With Two- or Three-Operand

Reads

D Arithmetic Instructions With Parallel Store

and Parallel Load

D Conditional Store Instructions D Fast Return From Interrupt D On-Chip Peripherals

− Software-Programmable Wait-State Generator and Programmable Bank Switching

− On-Chip Phase-Locked Loop (PLL) Clock Generator With Internal Oscillator or External Clock Source

− Two Multichannel Buffered Serial Ports (McBSPs)

− Enhanced 8-Bit Parallel Host-Port Interface (HPI8)

− Two 16-Bit Timers

− Six-Channel Direct Memory Access (DMA) Controller

D Power Consumption Control With IDLE1,

IDLE2, and IDLE3 Instructions With Power-Down Modes

D CLKOUT Off Control to Disable CLKOUT D On-Chip Scan-Based Emulation Logic,

IEEE Std 1149.1† (JTAG) Boundary Scan Logic

D 20-ns Single-Cycle Fixed-Point Instruction

Execution Time (50 MIPS) for 3.3-V Power Supply (1.8-V Core)

D 144-Pin Plastic Low-Profile Quad Flatpack

(LQFP) (PGE Suffix)

D 144-Ball MicroStar BGA (GGU Suffix)

†

IEEE Standard 1149.1-1990 Standard Test-Access Port and Boundary Scan Architecture. TMS320C54x and MicroStar BGA are trademarks of Texas Instruments. All trademarks are the property of their respective owners.

December 2000 − Revised October 2008 SPRS153D

Introduction

2 Introduction

This section describes the main features of the TMS320VC5401, lists the pin assignments, and describes the function of each pin. This data manual also provides a detailed description section, electrical specifications, parameter measurement information, and mechanical data about the available packaging.

NOTE: This data manual is designed to be used in conjunction with the TMS320C54x DSP Functional Overview (literature number SPRU307).

2.1 Description

The TMS320VC5401 fixed-point, digital signal processor (DSP) (hereafter referred to as the 5401 unless otherwise specified) is based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis of the operational flexibility and speed of this DSP is a highly specialized instruction set.

Separate program and data spaces allow simultaneous access to program instructions and data, providing the high degree of parallelism. Two read operations and one write operation can be performed in a single cycle. Instructions with parallel store and application-specific instructions can fully utilize this architecture. In addition, data can be transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can be performed in a single machine cycle. In addition, the 5401 includes the control mechanisms to manage interrupts, repeated operations, and function calls.

2.2 Pin Assignments

Figure 2−1 illustrates the ball locations for the 144-pin ball grid array (BGA) package and is used in conjunction with Table 2−1 to locate signal names and ball grid numbers. Figure 2−2 provides the pin assignments for the 144-pin low-profile quad flatpack (LQFP) package.

2.2.1 Terminal Assignments for the GGU Package

Table 2−1 lists each signal name and BGA ball number for the 144-pin TMS320VC5401GGU package. Table 2−2 lists each terminal name, terminal function, and operating modes for the TMS320VC5401.

123456781012 1113 9

A B C D E F G H J K L M N

Figure 2−1. 144-Ball GGU MicroStar BGA (Bottom View)

December 2000 − Revised October 2008SPRS153D

Introduction

Table 2−1. Terminal Assignments for the TMS320VC5401GGU (144-Pin BGA Package)

SIGNAL

NAME

NC A1 NC N13 NC N1 A19 A13 NC B1 NC M13 NC N2 NC A12

A10 D4 CLKMD1 K10 BCLKR0 K4 D6 D10

HD7 D3 CLKMD2 K11 BCLKR1 L4 D7 C10

A11 D2 CLKMD3 K12 BFSR0 M4 D8 B10 A12 D1 NC K13 BFSR1 N4 D9 A10 A13 E4 HD2 J10 BDR0 K5 D10 D9 A14 E3 TOUT0 J11 HCNTL1 L5 D11 C9 A15 E2 EMU0 J12 BDR1 M5 D12 B9

NC E1 EMU1/OFF J13 BCLKX0 N5 HD4 A9 HAS F4 TDO H10 BCLKX1 K6 D13 D8 V

NC F2 TRST H12 HINT/TOUT1 M6 D15 B8

HCS G2 TMS G12 BFSX0 M7 CV

HR/W G1 NC G13 BFSX1 N7 NC A7

READY G3 CV

PS G4 HPIENA G10 DV

DS H1 V

IS H2 CLKOUT F12 HD0 M8 DV

R/W H3 HD3 F11 BDX0 L8 A0 C6

MSTRB H4 X1 F10 BDX1 K8 A1 D6

IOSTRB J1 X2/CLKIN E13 IACK N9 A2 A5

MSC J2 RS E12 HBIL M9 A3 B5

XF J3 D0 E11 NMI L9 HD6 C5

HOLDA J4 D1 E10 INT0 K9 A4 D5

IAQ K1 D2 D13 INT1 N10 A5 A4

HOLD K2 D3 D12 INT2 M10 A6 B4

BIO K3 D4 D11 INT3 L10 A7 C4

MP/MC L1 D5 C13 CV

NC M1 A17 B13 NC N12 NC A2

NC M2 A18 B12 NC M12 NC B2

†

DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU. VSS is the ground for both the I/O pins and the core CPU.

‡

NC = No internal connection

BGA BALL #

C2 DV C1 V

F3 TDI H11 V

F1 TCK H13 CV

L2 A16 C12 HD1 M11 A9 B3 L3 V

SIGNAL

NAME

BGA BALL #

L12 HCNTL0 M3 V L13 V

G11 HRDY L7 HDS1 C7

F13 V

C11 V

SIGNAL

NAME

BGA BALL #

N3 DV

L6 D14 C8

N6 HD5 A8

K7 V N8 HDS2 A6

N11 A8 A3

L11 CV

SIGNAL

NAME

†‡

BGA BALL #

B11 A11

December 2000 − Revised October 2008 SPRS153D

Introduction

2.2.2 Pin Assignments for the PGE Package

The TMS320VC5401PGE 144-pin low-profile quad flatpack (LQFP) is footprint- and pin-compatible with the

5402.

NC NC

A10

HD7

A11 A12 A13 A14 A15

NC HAS V

HCS

HR/W

READY

R/W

MSTRB

IOSTRB

MSC

HOLDA

IAQ

HOLD

BIO

MP/MC

DD V

115D7114

D6113

A19

111

112

110

109

108

A18

107

A17

106

105

A16

104

103

D4 D3

102 101

100

RS X2/CLKIN

97 96

X1 HD3

95 94

CLKOUT V

HPIENA

92 91

TMS

TCK

TRST

TDI

TDO

EMU1/OFF

EMU0

TOUT0

HD2

CLKMD3

CLKMD2

CLKMD1

707172

144

143

142

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

23 24 25 26 27 28 29 30 31 32 33 34 35 36

373839404142434445464748495051525354555657585960616263646566676869

141A8140A7139

A6138

137

A4136

HD6135

134

A2133

A1132

131DV130

HDS2SSV

129

128

HDS1

127

126

125

HD5124

D15

123

D14122

D13121

HD4

120

D12119

D11

D9116

D10

118

117

HCNTL0SSBCLKR0

BFSR0

BCLKR1

BDR0

BFSR1

BDR1

BCLKX0

HCNTL1

BCLKX1

BFSX0

HRDY

BFSX1

HD0

BDX0

IACK

BDX1

HBIL

NMI

INT0

INT1

INT2

INT3

HINT/TOUT1

Figure 2−2. 144-Pin PGE Low-Profile Quad Flatpack (Top View)

December 2000 − Revised October 2008SPRS153D

HD1

Introduction

TERMINAL

TYPE

†

DESCRIPTION

2.3 Signal Descriptions

Table 2−2 lists each signal, function, and operating mode(s) grouped by function. See Section 2.2 for exact pin locations based on package type.

Table 2−2. Signal Descriptions

TERMINAL

NAME

DATA SIGNALS

A19 (MSB) A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 (LSB)

D15 (MSB) D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (LSB)

†

I = input, O = output, Z = high impedance, S = supply

‡

All revisions of the 5401 can be operated with an external clock source, provided that the proper voltage levels be driven on the X2/CLKIN pin. It should be noted that the X2/CLKIN pin is referenced to the device 1.8-V power supply (CVDD), rather than the 3-V I/O supply (DVDD). Refer to the recommended operating conditions section of this document for the allowable voltage levels of the X2/CLKIN pin.

Although this pin includes an internal pulldown resistor, a 470-Ω external pulldown is required. If the TRST pin is connected to multiple DSPs, a buffer is recommended to ensure the VIL and VIH specifications are met.

O/Z Parallel address bus A19 [most significant bit (MSB)] through A0 [least significant bit (LSB)]. The lower sixteen

address pins (A0 to A15) are multiplexed to address all external memory (program, data) or I/O, while the upper four address pins (A16 to A19) are only used to address external program space. These pins are placed in the high-impedance state when the hold mode is enabled, or when OFF is low.

I/O/Z Parallel data bus D15 (MSB) through D0 (LSB). The sixteen data pins (D0 to D15) are multiplexed to transfer data

between the core CPU and external data/program memory or I/O devices. The data bus is placed in the high-impedance state when not outputting or when RS or HOLD is asserted. The data bus also goes into the high-impedance state when OFF is low.

The data bus has bus holders to reduce the static power dissipation caused by floating, unused pins. These bus holders also eliminate the need for external bias resistors on unused pins. When the data bus is not being driven by the 5401, the bus holders keep the pins at the previous logic level. The data bus holders on the 5401 are disabled at reset and can be enabled/disabled via the BH bit of the bank-switching control register (BSCR).

December 2000 − Revised October 2008 SPRS153D

Introduction

Table 2−2. Signal Descriptions (Continued)

TERMINAL

NAME

IACK

INT0 INT1 INT2 INT3

NMI

MP/MC I

BIO I

XF O/Z

DS PS IS

MSTRB O/Z

READY I

R/W O/Z

IOSTRB O/Z

HOLD I †

I = input, O = output, Z = high impedance, S = supply

‡

†

INITIALIZATION, INTERRUPT, AND RESET OPERATIONS

Interrupt acknowledge signal. IACK Indicates receipt of an interrupt and that the program counter is fetching the

O/Z

interrupt vector location designated by A15−A0. IACK also goes into the high-impedance state when OFF is low.

External user interrupts. INT0−INT3 are prioritized and are maskable by the interrupt mask register (IMR) and the

interrupt mode bit. INT0 −INT3 can be polled and reset by way of the interrupt flag register (IFR).

Nonmaskable interrupt. NMI is an external interrupt that cannot be masked by way of the INTM or the IMR. When

NMI is activated, the processor traps to the appropriate vector location. Reset. R S causes the digital signal processor (DSP) to terminate execution and causes a reinitialization of the CPU

and peripherals. When RS is brought to a high level, execution begins at location 0FF80h of program memory. RS

affects various registers and status bits. Microprocessor/microcomputer mode select. If active low at reset, microcomputer mode is selected, and the

internal program ROM is mapped into the upper 4K words of program memory space. If the pin is driven high during reset, microprocessor mode is selected, and the on-chip ROM is removed from program space. This pin is only sampled at reset, and the MP/MC bit of the processor mode status (PMST) register can override the mode that is selected at reset.

MULTIPROCESSING SIGNALS

Branch control. A branch can be conditionally executed when BIO is active. If low, the processor executes the conditional instruction. For the XC instruction, the BIO condition is sampled during the decode phase of the pipeline; all other instructions sample BIO during the read phase of the pipeline.

External flag output (latched software-programmable signal). XF is set high by the SSBX XF instruction, set low by the RSBX XF instruction or by loading ST1. XF is used for signaling other processors in multiprocessor configurations or used as a general-purpose output pin. XF goes into the high-impedance state when OFF is low, and is set high at reset.

MEMORY CONTROL SIGNALS

Data, program, and I/O space select signals. DS, PS, and IS are always high unless driven low for accessing a particular external memory space. Active period corresponds to valid address information. DS, PS, and IS are

O/Z

placed into the high-impedance state in the hold mode; the signals also go into the high-impedance state when OFF is low.

Memory strobe signal. MSTRB is always high unless low-level asserted to indicate an external bus access to data or program memory. MSTRB is placed in the high-impedance state in the hold mode; it also goes into the high-impedance state when OFF is low.

Data ready. READY indicates that an external device is prepared for a bus transaction to be completed. If the device is not ready (READY is low), the processor waits one cycle and checks READY again. Note that the processor performs ready detection if at least two software wait states are programmed. The READY signal is not sampled until the completion of the software wait states.

Read/write signal. R/W indicates transfer direction during communication to an external device. R/W is normally in the read mode (high), unless it is asserted low when the DSP performs a write operation. R/W is placed in the high-impedance state in hold mode; it also goes into the high-impedance state when OFF is low.

I/O strobe signal. IOSTRB is always high unless low-level asserted to indicate an external bus access to an I/O device. IOSTRB is placed in the high-impedance state in the hold mode; it also goes into the high-impedance state when OFF is low.

Hold. HOLD is asserted to request control of the address, data, and control lines. When acknowledged by the C54x DSP, these lines go into the high-impedance state.

DESCRIPTIONTYPE

December 2000 − Revised October 2008SPRS153D

Introduction

Table 2−2. Signal Descriptions (Continued)

TERMINAL

NAME

HOLDA O/Z

MSC O/Z

IAQ O/Z

CLKOUT O/Z

CLKMD1 CLKMD2 CLKMD3

X2/CLKIN I

X1 O

TOUT0 O/Z

TOUT1 O/Z

BCLKR0 BCLKR1

BDR0 BDR1

BFSR0 BFSR1

BCLKX0 BCLKX1

BDX0 BDX1

BFSX0 BFSX1

†

I = input, O = output, Z = high impedance, S = supply

‡

†

MEMORY CONTROL SIGNALS (CONTINUED)

Hold acknowledge. HOLDA indicates that the 5401 is in a hold state and that the address, data, and control lines are in the high-impedance state, allowing the external memory interface to be accessed by other devices. HOLDA also goes into the high-impedance state when OFF is low. This pin is driven high during reset.

Microstate complete. MSC indicates completion of all software wait states. When two or more software wait states are enabled, the MSC p i n g o e s a c t i v e a t t h e b e g i n ni n g o f t h e first software wait state and goes inactive high at the beginning of the last software wait state. If connected to the READY input, MSC forces one external wait state after the last internal wait state is completed. MSC also goes into the high-impedance state when OFF is low.

Instruction acquisition signal. IAQ is asserted (active low) when there is an instruction address on the address bus. IAQ goes into the high-impedance state when OFF is low.

Master clock output signal. CLKOUT cycles at the machine-cycle rate of the CPU. The internal machine cycle is bounded by rising edges of this signal. CLKOUT also goes into the high-impedance state when OFF is low.

Clock mode select signals. These inputs select the mode that the clock generator is initialized to after reset. The logic levels of CLKMD1–CLKMD3 are latched when the reset pin is low, and the clock mode register is initialized

to the selected mode. After reset, the clock mode can be changed through software, but the clock mode select signals have no effect until the device is reset again.

Oscillator input. This is the input to the on-chip oscillator.

If the internal oscillator is not used, X2/CLKIN functions as the clock input, and can be driven by an external clock

‡

source. Output pin from the internal oscillator for the crystal.

If the internal oscillator is not used, X1 should be left unconnected. X1 does not go into the high-impedance state when OFF is low.

Timer0 output. TOUT0 signals a pulse when the on-chip timer 0 counts down past zero. The pulse is a CLKOUT cycle wide. TOUT0 also goes into the high-impedance state when OFF is low.

Timer1 output. TOUT1 signals a pulse when the on-chip timer1 counts down past zero. The pulse is one CLKOUT cycle wide. The TOUT1 output is multiplexed with the HINT pin of the HPI and is only available when the HPI is disabled. TOUT1 also goes into the high-impedance state when OFF is low.

I/O/Z

Receive clock input. BCLKR can be configured as an input or an output; it is configured as an input following reset. BCLKR serves as the serial shift clock for the buffered serial port receiver.

I Serial data receive input

Frame synchronization pulse for receive input. BFSR can be configured as an input or an output; it is configured as an input following reset. The BFSR pulse initiates the receive data process over BDR.

Transmit clock. BCLKX serves as the serial shift clock for the McBSP transmitter. BCLKX can be configured as an input or an output; it is configured as an input following reset. BCLKX enters the high-impedance state when OFF goes low.

Serial data transmit output. BDX is placed in the high-impedance state when not transmitting, when RS is asserted,

O/Z

or when OFF is low. Frame synchronization pulse for transmit input/output. The BFSX pulse initiates the transmit data process. BFSX

can be configured as an input or an output; it is configured as an input following reset. BFSX goes into the high-impedance state when OFF is low.

‡

MULTICHANNEL BUFFERED SERIAL PORT SIGNALS

DESCRIPTIONTYPE

OSCILLATOR/TIMER SIGNALS

C54x is a trademark of Texas Instruments.

December 2000 − Revised October 2008 SPRS153D

Introduction

Table 2−2. Signal Descriptions (Continued)

TERMINAL

NAME

NC No connection

HD0−HD7 I/O/Z

HCNTL0 HCNTL1

HBIL I

HCS I

HDS1 HDS2

HAS I

HR/W I

HRDY O/Z

HINT O/Z

HPIENA I

TCK I

TDI I

TDO O/Z

†

I = input, O = output, Z = high impedance, S = supply

‡

†

MISCELLANEOUS SIGNAL

HOST-PORT INTERFACE SIGNALS

Parallel bidirectional data bus. The HPI data bus is used by a host device bus to exchange information with the HPI registers. These pins can also be used as general-purpose I/O pins. HD0−HD7 is placed in the high-impedance state when not outputting data or when OFF is low. The HPI data bus includes bus holders to reduce the static power dissipation caused by floating, unused pins. When the HPI data bus is not being driven by the 5401, the bus holders keep the pins at the previous logic level. The HPI data bus holders are disabled at reset and can be enabled/disabled via the HBH bit of the BSCR.

Control. HCNTL0 and HCNTL1 select a host access to one of the three HPI registers. The control inputs have

internal pullup resistors that are only enabled when HPIENA = 0. Byte identification. HBIL identifies the first or second byte of transfer . The HBIL input has an internal pullup resistor

that is only enabled when HPIENA = 0. Chip select. HCS is the select input for the HPI and must be driven low during accesses. The chip-select input has

an internal pullup resistor that is only enabled when HPIENA = 0. Data strobe. HDS1 and HDS2 are driven by the host read and write strobes to control transfers. The strobe inputs

have internal pullup resistors that are only enabled when HPIENA = 0. Address strobe. Hosts with multiplexed address and data pins require HAS to latch the address in the HPIA

register. HAS has an internal pullup resistor that is only enabled when HPIENA = 0. Read/write. HR/W controls the direction of an HPI transfer . R/W has an internal pullup resistor that is only enabled

when HPIENA = 0. Ready. The ready output informs the host when the HPI is ready for the next transfer. HRDY goes into the

high-impedance state when OFF is low. Host interrupt. This output is used to interrupt the host. When the DSP is in reset, HINT is driven high. HINT can

also be configured as the timer 1 output (TOUT1), when the HPI is disabled. The signal goes into the high-impedance state when OFF is low.

HPI module select. HPIENA must be driven high during reset to enable the HPI. An internal pulldown resistor is always active and the HPIENA pin is sampled on the rising edge of RS. If HPIENA is left open or is driven low during reset, the HPI module is disabled. Once the HPI is disabled, the HPIENA pin has no effect until the 5401 is reset.

SUPPLY PNS

S +VDD. Dedicated 1.8-V power supply for the core CPU S +VDD. Dedicated 3.3-V power supply for the I/O pins S Ground

TEST PINS

IEEE standard 1149.1 test clock. TCK is normally a free-running clock signal with a 50% duty cycle. The changes on the test access port (TAP) of input signals TMS and TDI are clocked into the T AP controller, instruction register, or selected test data register on the rising edge of TCK. Changes at the TAP output signal (TDO) occur on the falling edge of TCK.

IEEE standard 1149.1 test data input pin with internal pullup device. TDI is clocked into the selected register (instruction o r data) on a rising edge of TCK.

IEEE standard 1149.1 test data output. The contents of the selected register (instruction or data) are shifted ou t of TDO on the falling edge of TCK. TDO is in the high-impedance state except when the scanning of data is in progress. TDO also goes into the high-impedance state when OFF is low.

DESCRIPTIONTYPE

December 2000 − Revised October 2008SPRS153D

Introduction

Table 2−2. Signal Descriptions (Continued)

TERMINAL

NAME

TMS I

TRST

EMU0 I/O/Z

EMU1/OFF I/O/Z

†

I = input, O = output, Z = high impedance, S = supply

‡

†

TEST PINS (CONTINUED)

IEEE standard 1149.1 test mode select. Pin with internal pullup device. This serial control input is clocked into the TAP controller on the rising edge of TCK.

IEEE standard 1149.1 test reset. TRST, when high, gives the IEEE standard 1149.1 scan system control of the

operations of the device. If TRST is driven low, the device operates in its functional mode, and the IEEE standard

1149.1 signals are ignored. Pin with internal pulldown device. Emulator 0 pin. When TRST is driven low, EMU0 must be high for activation of the OFF condition. When TRST

is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined as input/output by way of the IEEE standard 1149.1 scan system.

Emulator 1 pin/disable all outputs. When TRST is driven high, EMU1/OFF is used as an interrupt to or from the emulator system and is defined as input/output by way of the IEEE standard 1149.1 scan system. When TRST is driven low, EMU1/OFF is configured as OFF. The EMU1/OFF signal, when active low, puts all output drivers into the high-impedance state. Note that OFF is used exclusively for testing and emulation purposes (not for multiprocessing applications). The OFF feature is selected by the following pin combinations: TRST = low EMU0 = high EMU1/OFF = low

DESCRIPTIONTYPE

December 2000 − Revised October 2008 SPRS153D

Functional Overview

3 Functional Overview

The following functional overview is based on the block diagram in Figure 3−1.

Cbus

Pbus

54X cLEAD

TI BUS

P, C, D, E Buses and Control Signals

Dbus

Ebus

RHEA

Bridge

RHEA Bus

Cbus

Pbus

Dbus

8K RAM

Dual Access

Program/Data

MBus

Ebus

Pbus

4K Program

ROM

GPIO

McBSP1

XIO

HPI

Enhanced XIO

HPI

Figure 3−1. TMS320VC5401 Functional Block Diagram

3.1 Memory

The 5401 device provides both on-chip ROM and RAM memories to aid in system performance and integration.

3.1.1 On-Chip ROM With Bootloader

The 5401 features a 4K-word × 16-bit on-chip maskable ROM. Customers can arrange to have the ROM of the 5401 programmed with contents unique to any particular application. A security option is available to protect a custom ROM. This security option is described in the TMS320C54x DSP Reference Set, Volume 1: CPU and Peripherals (literature number SPRU131). Note that only the ROM security option, and not the ROM/RAM option, is available on the 5401.

DMA logic

RHEAbus

RHEA bus

MBus

Clocks

McBSP2

TIMER

APLL

JTAG

A bootloader is available in the standard 5401 on-chip ROM. This bootloader can be used to automatically transfer user code from an external source to anywhere in the program memory at power up. If the MP/MC pin is sampled low during a hardware reset, execution begins at location FF80h of the on-chip ROM. This location contains a branch instruction to the start of the bootloader program. The standard 5401 bootloader provides different ways to download the code to accommodate various system requirements:

• Parallel from 8-bit or 16-bit-wide EPROM

• Parallel from I/O space 8-bit or 16-bit mode

• Serial boot from serial ports 8-bit or 16-bit mode

• Host-port interface boot

December 2000 − Revised October 2008SPRS153D

The standard on-chip ROM layout is shown in Table 3−1.

ADDRESS RANGE DESCRIPTION

F000h − F7FFh Reserved F800h − FBFFh Bootloader FC00h − FCFFh µ-law expansion table FD00h − FDFFh A-law expansion table FE00h − FEFFh Sine look-up table

FF00h − FF7Fh Reserved FF80h − FFFFh Interrupt vector table

†

In the 5401 ROM, 128 words are reserved for factory device-testing purposes. Application code to be implemented in on-chip ROM must reserve these 128 words at addresses FF00h–FF7Fh in program space.

3.1.2 On-Chip RAM

The 5401 device contains 8K × 16-bit of on-chip dual-access RAM (DARAM). The DARAM is composed of two blocks of 4K words each. Each DARAM block can support two reads in one cycle, or a read and a write in one cycle. This allows code to be executed out of one block while two data values are read out of the other block without incurring a cycle penalty. The first DARAM block occupies two address ranges: 0060h−007Fh and 1000h−1FFFh in data space. The second DARAM block occupies 2000h−2FFFh in data space. In program space, each block occupies the same address ranges with the exception of 0060h−007Fh, which are not available.

Table 3−1. Standard On-Chip ROM Layout

Functional Overview

†

3.1.3 On-Chip Memory Security

The 5401 features a 16K-word × 16-bit on-chip maskable ROM. Customers can arrange to have the ROM of the 5401 programmed with contents unique to any particular

application. A security option is available to protect a custom ROM. The ROM and ROM/RAM security options are available on the 5401. These security options are described in the TMS320C54x DSP Reference Set, Volume 1: CPU and Peripherals (literature number SPRU131). When the security options are enabled, JTAG emulation is inhibited or nonfunctional.

December 2000 − Revised October 2008 SPRS153D

Functional Overview

3.2 Memory Map

Page 0 Program

Hex

0000

0FFF 1000

On-Chip DARAM

1FFF

2000

On-Chip DARAM

2FFF

3000

3FFF

4000

FF7F

FF80

Reserved

(OVLY = 1)

External

(OVLY = 0)

(OVLY = 1)

External

(OVLY = 0)

(OVLY = 1)

External

(OVLY = 0)

Reserved

(OVL Y = 1)

External

(OVLY = 0)

External

Interrupts (External)

Hex

0000

0FFF

1000

On-Chip DARAM

1FFF

2000

On-Chip DARAM

2FFF

3000

3FFF

4000

EFFF

F000

FEFF

FF00 FF7F

FF80

Page 0 Program

Reserved

(OVLY = 1)

External

(OVLY = 0)

(OVL Y = 1)

External

(OVLY = 0)

(OVL Y = 1)

External

(OVLY = 0)

Reserved

(OVL Y = 1)

External

(OVLY = 0)

External

On-Chip ROM

(4K x 16-bit)

Reserved

Interrupts

(On-Chip)

Hex

0000

005F

0060

007F

0080

0FFF

1000

1FFF

2000

2FFF

3000

3FFF

4000

EFFF

F000

FEFF

FF00

Data

Memory Mapped

Registers

Scratch-Pad

†

RAM

Reserved

On-Chip DARAM

(4K x 16-bit)

On-Chip DARAM

(4K x 16-bit)

Reserved

External

ROM (DROM=1)

or External

(DROM=0)

Reserved

(DROM=1)

or External

(DROM=0)

FFFF

MP/MC= 1

(Microprocessor Mode)

†

The scratch-pad RAM area is physically a part of the DARAM block starting at address 1000h. Physical location can affect multiple access performance. (See Section 3.1.2.)

FFFF

(Microcomputer Mode)

Figure 3−2. Memory Map

3.2.1 Relocatable Interrupt Vector Table

The reset, interrupt, and trap vectors are addressed in program space. These vectors are soft — meaning that the processor, when taking the trap, loads the program counter (PC) with the trap address and executes the code at the vector location. Four words are reserved at each vector location to accommodate a delayed branch instruction, either two 1-word instructions or one 2-word instruction, which allows branching to the appropriate interrupt service routine with minimal overhead.

At device reset, the reset, interrupt, and trap vectors are mapped to address FF80h in program space. However, these vectors can be remapped to the beginning of any 128-word page in program space after device reset. This is done by loading the interrupt vector pointer (IPTR) bits in the PMST register (see Figure 3−3) with the appropriate 128-word page boundary address. After loading IPTR, any user interrupt or trap vector is mapped to the new 128-word page.

FFFF

MP/MC= 0

December 2000 − Revised October 2008SPRS153D

Functional Overview

RESET

FUNCTION

NOTE: The hardware reset (RS) vector cannot be remapped because a hardware reset loads the IPTR with 1s. Therefore, the reset vector is always fetched at location FF80h in program space.

IPTR

R/W

IPTR MP/MC OVLY AVIS DROM CLKOFF SMUL SST

R/W R/W R/W R R R R/W R/W

LEGEND: R = Read, W = Write, n = value present after reset

6543210

Figure 3−3. Processor Mode Status (PMST) Register

Table 3−2. Processor Mode Status (PMST) Register Bit Fields

BIT

NO. NAME

15−7 IPTR 1FFh

6 MP/MC

5 OVLY 0

4 AVIS 0

3 DROM 0

2 CLKOFF 0

1 SMUL 0

0 SST 0

VALUE

MP/MC

Interrupt vector pointer. The 9-bit IPTR field points to the 128-word program page where the interrupt vectors reside. The interrupt vectors can be remapped to RAM for boot-loaded operations. At reset, these bits are all set to 1; the reset vector always resides at address FF80h in program memory space. The RESET instruction does not affect this field.

Microprocessor/microcomputer mode. MP/MC enables/disables the on-chip ROM to be addressable in program memory space.

- MP/MC = 0: The on-chip ROM is enabled and addressable.

- MP/MC = 1: The on-chip ROM is not available.

MP/MC is set to the value corresponding to the logic level on the MP/MC pin when sampled at reset. This pin is not sampled again until the next reset. The RESET instruction does not affect this bit. This bit can also be set or cleared by software.

RAM overlay. OVLY enables on-chip dual-access data RAM blocks to be mapped into program space. The values for the OVLY bit are:

- OVLY = 0: The on-chip RAM is addressable in data space but not in program space.

- OVLY = 1: The on-chip RAM is mapped into program space and data space. Data page 0 (addresses

0h to 7Fh), however, is not mapped into program space.

Address visibility mode. AVIS enables/disables the internal program address to be visible at the address pins.

- AVIS = 0: The external address lines do not change with the internal program address. Control and data lines are not af fected and the address bus is driven with the last address on the bus.

- A VIS = 1: This mode allows the internal program address to appear at the pins of the 5410A so that the internal program address can be traced. Also, it allows the interrupt vector to be decoded in conjunction with IACK when the interrupt vectors reside on on-chip memory.

Data ROM. DROM enables on-chip ROM to be mapped into data space. The values for the DROM bit are:

- DROM = 0: The on-chip ROM is not mapped into data space.

- DROM = 1: A portion of the on-chip RAM is mapped into data space.

CLOCKOUT off. When the CLKOFF bit is 1, the output of CLKOUT is disabled and remains at a high level.

Saturation on multiplication. When SMUL = 1, saturation of a multiplication result occurs before performing the accumulation in a MAC of MAS instruction. The SMUL bit applies only when OVM = 1 and FRCT = 1.

Saturation on store. When SST = 1, saturation of the data from the accumulator is enabled before storing in memory. The saturation is performed after the shift operation.

December 2000 − Revised October 2008 SPRS153D

Functional Overview

3.2.2 Extended Program Memory

The 5401 uses a paged extended memory scheme in program space to allow access of up to 1024K program memory locations. In order to implement this scheme, the 5401 includes several features that are also present on the 548/549 devices:

• Twenty address lines, instead of sixteen

• An extra memory-mapped register, the XPC register, defines the page selection. This register is

memory-mapped into data space to address 001Eh. At a hardware reset, the XPC is initialized to 0.

• Six extra instructions for addressing extended program space. These six instructions affect the XPC.

− FB[D] pmad (20 bits) − Far branch

− FBACC[D] Accu[19:0] − Far branch to the location specified by the value in accumulator A or accumulator B

− FCALL[D] pmad (20 bits) − Far call

− FCALA[D] Accu[19:0] − Far call to the location specified by the value in accumulator A or accumulator B

− FRET[D] − Far return

− FRETE[D] − Far return with interrupts enabled

• In addition to these new instructions, two 54x instructions are extended to use 20 bits in the 5401:

− READA data_memory (using 20-bit accumulator address)

− WRITA data_memory (using 20-bit accumulator address)

All other instructions, software interrupts and hardware interrupts do not modify the XPC register and access only memory within the current page.

Program memory in the 5401 is organized into 16 pages that are each 64K in length, as shown in Figure 3−4.

December 2000 − Revised October 2008SPRS153D

Functional Overview

0 0000

Page 0

64K

Words{

0 FFFF

†

See Figure 3−2.

‡

The lower 16K words of pages 1 through 15 are available only when the OVLY bit is cleared to 0. If the OVLY bit is set to 1, the on-chip RAM and reserved addresses are mapped to the lower 16K words of all program space pages.

1 0000

1 3FFF

1 4000

1 FFFF

Page 1

Lower

16K}

External

Page 1

Upper

48K

External

2 0000

2 3FFF

2 4000

2 FFFF

Page 2

Lower

16K}

External

Page 2

Upper

48K

External

. . . . . . . . .

. . .

F 0000

F 3FFF

F 4000

F FFFF

Page 15

Lower

16K}

External

Page 15

Upper

48K

External

Figure 3−4. Extended Program Memory

3.3 On-Chip Peripherals

The 5401 device has the following peripherals:

• Software-programmable wait-state generator with programmable bank-switching wait states

• An enhanced 8-bit host-port interface (HPI8)

• Two multichannel buffered serial ports (McBSPs)

• Two hardware timers

• A clock generator with a phase-locked loop (PLL)

• A direct memory access (DMA) controller

3.3.1 Software-Programmable Wait-State Generator

The software wait-state generator of the 5401 can extend external bus cycles by up to fourteen machine cycles. Devices that require more than fourteen wait states can be interfaced using the hardware READY line. When all external accesses are configured for zero wait states, the internal clocks to the wait-state generator are automatically disabled. Disabling the wait-state generator clocks reduces the power consumption of the

5401. The software wait-state register (SWWSR) controls the operation of the wait-state generator. The 14 LSBs

of the SWWSR specify the number of wait states (0 to 7) to be inserted for external memory accesses to five separate address ranges. This allows a different number of wait states for each of the five address ranges. Additionally, the software wait-state multiplier (SWSM) bit of the software wait-state control register (SWCR) defines a multiplication factor of 1 or 2 for the number of wait states. At reset, the wait-state generator is initialized to provide seven wait states on all external memory accesses. The SWWSR bit fields are shown in Figure 3−5 and described in Table 3−3.

December 2000 − Revised October 2008 SPRS153D

Functional Overview

RESET

FUNCTION

XPA I/O DATA DATA

R/W-0 R/W-111 R/W-111 R/W-111

DATA PROGRAM PROGRAM

R/W-111 R/W-111 R/W-111

LEGEND: R = Read, W = Write, n = value present after reset

14 12 11 9 8

65 32 0

Figure 3−5. Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h]

Table 3−3. Software Wait-State Register (SWWSR) Bit Fields

BIT

NO. NAME

15 XPA 0

14−12 I/O 1

11−9 Data 1

8−6 Data 1

5−3 Program 1

2−0 Program 1

VALUE

Extended program address control bit. XPA is used in conjunction with the program space fields (bits 0 through 5) to select the address range for program space wait states.

I/O space. The field value (0−7) corresponds to the base number of wait states for I/O space accesses within addresses 0000−FFFFh. The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.

Upper data space. The field value (0−7) corresponds to the base number of wait states for external data space accesses within addresses 8000−FFFFh. The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.

Lower data space. The field value (0−7) corresponds to the base number of wait states for external data space accesses within addresses 0000−7FFFh. The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.

Upper program space. The field value (0−7) corresponds to the base number of wait states for external program space accesses within the following addresses:

- XPA = 0: x8000 − xFFFFh

- XPA = 1: The upper program space bit field has no effect on wait states.

The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states. Program space. The field value (0−7) corresponds to the base number of wait states for external

program space accesses within the following addresses:

- XPA = 0: x0000−x7FFFh

- XPA = 1: 00000−FFFFFh

The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.

December 2000 − Revised October 2008SPRS153D

+ 59 hidden pages

Texas instruments TMS320VC5401 Data Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Revision History

Contents

List of Figures

List of Tables

1 TMS320VC5401 Features

2 Introduction

2.1 Description

2.2 Pin Assignments

2.2.1 Terminal Assignments for the GGU Package

2.2.2 Pin Assignments for the PGE Package

2.3 Signal Descriptions

3 Functional Overview

3.1 Memory

3.1.1 On-Chip ROM With Bootloader

3.1.2 On-Chip RAM

3.1.3 On-Chip Memory Security

3.2 Memory Map

3.2.1 Relocatable Interrupt Vector Table

3.2.2 Extended Program Memory

3.3 On-Chip Peripherals

3.3.1 Software-Programmable Wait-State Generator