Texas Instruments TMS320DM36X User Manual 2

TMS320DM36x DMSoC Analog to Digital
Converter (ADC) Interface

User's Guide

Literature Number: SPRUFI7

March 2009

2 SPRUFI7 – March 2009

Submit Documentation Feedback

Contents

Preface ........................................................................................................................................ 5

1 Features .............................................................................................................................. 8

1.1 Block Diagram ............................................................................................................. 8

1.2 Industry Compliance Statement ......................................................................................... 9

2 Peripheral Architecture ......................................................................................................... 9

2.1 Clock Control .............................................................................................................. 9

2.2 Signal Descriptions ....................................................................................................... 9

2.3 Functional Operation ..................................................................................................... 9

2.4 Reset Considerations ................................................................................................... 10

2.5 Interrupt Support ......................................................................................................... 10

2.6 EDMA Event Support ................................................................................................... 11

2.7 Power Management ..................................................................................................... 11

2.8 Emulation Considerations .............................................................................................. 11

3 Registers ........................................................................................................................... 11

3.1 ADCTL ................................................................................................................... 12

3.2 CMPTGT .................................................................................................................. 13

3.3 CMPLDAT ................................................................................................................ 13

3.4 CMPUDAT ................................................................................................................ 14

3.5 SETDIV ................................................................................................................... 14

3.6 CHSEL .................................................................................................................... 14

3.7 AD0DAT .................................................................................................................. 15

3.8 AD1DAT .................................................................................................................. 15

3.9 AD2DAT .................................................................................................................. 16

3.10 AD3DAT .................................................................................................................. 16

3.11 AD4DAT .................................................................................................................. 16

3.12 AD5DAT .................................................................................................................. 17

3.13 EMUCTRL ................................................................................................................ 17

SPRUFI7 – March 2009 Table of Contents 3

Submit Documentation Feedback

www.ti.com

List of Figures

1 ADC IF Block Diagram ...................................................................................................... 8

2 ADC Control (ADCTL) Register .......................................................................................... 12

3 Comparator Target Channel (CMPTGT) Register ..................................................................... 13

4 Comparison A/D Lower Data (CMPLDAT) Register ................................................................... 13

5 Comparison A/D Upper Data (CMPUDAT) Register .................................................................. 14

6 Setup Divide Value for Start A/D (SETDIV) Register .................................................................. 14

7 Analog Input Channel Select (CHSEL) Register ....................................................................... 15

8 A/D Conversion Data 0 (AD0DAT) Register ............................................................................ 15

9 A/D Conversion Data 1 (AD1DAT) Register ............................................................................ 15

10 A/D Conversion Data 2 (AD2DAT) Register ............................................................................ 16

11 A/D Conversion Data 3 (AD3DAT) Register ............................................................................ 16

12 A/D Conversion Data 4 (AD4DAT) Register ............................................................................ 16

13 A/D Conversion Data 5 (AD5DAT) Register ............................................................................ 17

14 Emulation Control (EMUCTRL) Register ................................................................................ 17

List of Tables

1 ADC interface Memory Map Registers .................................................................................. 11

2 ADC Control (ADCTL) Field Descriptions ............................................................................... 12

3 Comparator Target Channel (CMPTGT) Field Descriptions .......................................................... 13

4 Comparison A/D Lower Data (CMPLDAT) Field Descriptions ....................................................... 13

5 Comparison A/D Upper Data (CMPUDAT) Field Descriptions ....................................................... 14

6 Setup Divide Value for Start A/D (SETDIV) Field Descriptions ...................................................... 14

7 CHSEL setting for Channel selection .................................................................................... 15

8 Analog Input Channel Select (CHSEL) Field Descriptions ........................................................... 15

9 A/D Conversion Data 0 (AD0DAT) Field Descriptions ................................................................ 15

10 A/D Conversion Data 1 (AD1DAT) Field Descriptions ................................................................ 16

11 A/D Conversion Data 2 (AD2DAT) Field Descriptions ................................................................ 16

12 A/D Conversion Data 3 (AD3DAT) Field Descriptions ................................................................ 16

13 A/D Conversion Data 4 (AD4DAT) Field Descriptions ................................................................ 17

14 A/D Conversion Data 5 (AD5DAT) Field Descriptions ................................................................ 17

15 Emulation Control (EMUCTRL) Field Descriptions .................................................................... 17

List of Figures4 SPRUFI7 – March 2009

Submit Documentation Feedback

About This Manual

This document describes the analog-to-digital converter (ADC) interface peripheral in the TMS320DM36x
Digital Media System-on-Chip (DMSoC).

Notational Conventions

This document uses the following conventions.

• Hexadecimal numbers are shown with the suffix h. For example, the following number is 40
hexadecimal (decimal 64): 40h.

• Registers in this document are shown in figures and described in tables.
– Each register figure shows a rectangle divided into fields that represent the fields of the register.

Each field is labeled with its bit name, its beginning and ending bit numbers above, and its
read/write properties below. A legend explains the notation used for the properties.

– Reserved bits in a register figure designate a bit that is used for future device expansion.

Related Documentation From Texas Instruments

The following documents describe the TMS320DM36x Digital Media System-on-Chip (DMSoC). Copies of
these documents are available on the internet at www.ti.com .

SPRUFG5 — TMS320DM36x Digital Media System-on-Chip (DMSoC) ARM Subsystem Users Guide

This document describes the ARM Subsystem in the TMS320DM36x Digital Media System-on-Chip
(DMSoC). The ARM subsystem is designed to give the ARM926EJ-S (ARM9) master control of the
device. In general, the ARM is responsible for configuration and control of the device; including the
components of the ARM Subsystem, the peripherals, and the external memories.

Preface

SPRUFI7 – March 2009

Read This First

SPRUFG8 — TMS320DM36x Digital Media System-on-Chip (DMSoC) Video Processing Front End

(VPFE) Users Guide This document describes the Video Processing Front End (VPFE) in the

TMS320DM36x Digital Media System-on-Chip (DMSoC).

SPRUFG9 — TMS320DM36x Digital Media System-on-Chip (DMSoC) Video Processing Back End

(VPBE) Users Guide This document describes the Video Processing Back End (VPBE) in the

TMS320DM36x Digital Media System-on-Chip (DMSoC).

SPRUFH0 — TMS320DM36x Digital Media System-on-Chip (DMSoC) 64-bit Timer Users Guide This

document describes the operation of the software-programmable 64-bit timers in the
TMS320DM36x Digital Media System-on-Chip (DMSoC). Timer 0, Timer 1, and Timer 3 are used
as general-purpose (GP) timers and can be programmed in 64-bit mode, dual 32-bit unchained
mode, or dual 32-bit chained mode; Timer 2 is used only as a watchdog timer. The GP timer modes
can be used to generate periodic interrupts or enhanced direct memory access (EDMA)
synchronization events and Real Time Output (RTO) events (Timer 3 only). The watchdog timer
mode is used to provide a recovery mechanism for the device in the event of a fault condition, such
as a non-exiting code loop.

SPRUFH1 — TMS320DM36x Digital Media System-on-Chip (DMSoC) Serial Peripheral Interface (SPI)

Users Guide This document describes the serial peripheral interface (SPI) in the TMS320DM36x

Digital Media System-on-Chip (DMSoC). The SPI is a high-speed synchronous serial input/output
port that allows a serial bit stream of programmed length (1 to 16 bits) to be shifted into and out of
the device at a programmed bit-transfer rate. The SPI is normally used for communication between
the DMSoC and external peripherals. Typical applications include an interface to external I/O or
peripheral expansion via devices such as shift registers, display drivers, SPI EPROMs and
analog-to-digital converters.

SPRUFI7 – March 2009 Preface 5

Submit Documentation Feedback

Related Documentation From Texas Instruments

SPRUFH2 — TMS320DM36x Digital Media System-on-Chip (DMSoC) Universal Asynchronous

Receiver/Transmitter (UART) Users Guide This document describes the universal asynchronous

receiver/transmitter (UART) peripheral in the TMS320DM36x Digital Media System-on-Chip
(DMSoC). The UART peripheral performs serial-to-parallel conversion on data received from a
peripheral device, and parallel-to-serial conversion on data received from the CPU.

SPRUFH3 — TMS320DM36x Digital Media System-on-Chip (DMSoC) Inter-Integrated Circuit (I2C)

Peripheral Users Guide This document describes the inter-integrated circuit (I2C) peripheral in the

TMS320DM36x Digital Media System-on-Chip (DMSoC). The I2C peripheral provides an interface
between the DMSoC and other devices compliant with the I2C-bus specification and connected by
way of an I2C-bus. External components attached to this 2-wire serial bus can transmit and receive
up to 8-bit wide data to and from the DMSoC through the I2C peripheral. This document assumes
the reader is familiar with the I2C-bus specification.

SPRUFH4 — TMS320DM36x Digital Media System-on-Chip (DMSoC) Memory Stick Controller Users

Guide This document This document describes the memory stick controller in the TMS320DM36x
Digital Media System-on-Chip (DMSoC). Memory Stick cards are used in a number of applications
to provide removable data storage. The memory stick controller provides an interface to external
Memory Stick cards. The communication between the controller and the cards is performed by the
Memory Stick protocol.

SPRUFH5 — TMS320DM36x Digital Media System-on-Chip (DMSoC) Multimedia Card (MMC)/Secure

Digital (SD) Card Controller Users Guide This document describes the multimedia card

(MMC)/secure digital (SD) card controller in the TMS320DM36x Digital Media System-on-Chip
(DMSoC). The MMC/SD card is used in a number of applications to provide removable data
storage. The MMC/SD controller provides an interface to external MMC and SD cards. The
communication between the MMC/SD controller and MMC/SD card(s) is performed by the MMC/SD
protocol.

www.ti.com

SPRUFH6 — TMS320DM36x Digital Media System-on-Chip (DMSoC) Pulse-Width Modulator (PWM)

Users Guide This document describes the pulse-width modulator (PWM) peripheral in the

TMS320DM36x Digital Media System-on-Chip (DMSoC).

SPRUFH7 — TMS320DM36x Digital Media System-on-Chip (DMSoC) Real-Time Out (RTO) Controller

Users Guide This document describes the Real Time Out (RTO) controller in the TMS320DM36x

Digital Media System-on-Chip (DMSoC).

SPRUFH8 — TMS320DM36x Digital Media System-on-Chip (DMSoC) General-Purpose Input/Output

(GPIO) Users Guide This document describes the general-purpose input/output (GPIO) peripheral

in the TMS320DM36x Digital Media System-on-Chip (DMSoC). The GPIO peripheral provides
dedicated general-purpose pins that can be configured as either inputs or outputs. When configured
as an input, you can detect the state of the input by reading the state of an internal register. When
configured as an output, you can write to an internal register to control the state driven on the
output pin.

SPRUFH9 — TMS320DM36x Digital Media System-on-Chip (DMSoC) Universal Serial Bus (USB)

Controller Users Guide This document describes the universal serial bus (USB) controller in the

TMS320DM36x Digital Media System-on-Chip (DMSoC). The USB controller supports data
throughput rates up to 480 Mbps. It provides a mechanism for data transfer between USB devices
and also supports host negotiation.

SPRUFI0 — TMS320DM36x Digital Media System-on-Chip (DMSoC) Enhanced Direct Memory

Access (EDMA) Controller Users Guide This document describes the operation of the enhanced

direct memory access (EDMA3) controller in the TMS320DM36x Digital Media System-on-Chip
(DMSoC). The EDMA controller's primary purpose is to service user-programmed data transfers
between two memory-mapped slave endpoints on the DMSoC.

SPRUFI1 — TMS320DM36x Digital Media System-on-Chip (DMSoC) Asynchronous External Memory

Interface (EMIF) Users Guide This document describes the asynchronous external memory

interface (EMIF) in the TMS320DM36x Digital Media System-on-Chip (DMSoC). The EMIF supports
a glueless interface to a variety of external devices.

6 Read This First SPRUFI7 – March 2009

Submit Documentation Feedback