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TMS320DM335
Data Manual
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Texas instruments TMS320DM335 Data Manual

TMS320DM335
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SPRS528C–JULY 2008–REVISED JUNE 2010
TMS320DM335
Digital Media System-on-Chip (DMSoC)
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1 Digital Media System-on-Chip (DMSoC)

1.1 TMS320DM335 Features

• Highlights – High-Performance Digital Media
System-On-Chip (DMSoC) – Up to 216-MHz ARM926EJ-S™ Clock Rate – Digital HDTV (720p/1080i) output for
connection to external encoder – 32K-Byte RAM – Video Processing Subsystem – 8K-Byte ROM
• Hardware IPIPE for Real-Time Image – Little Endian Processing
• Up to 14-bit CCD/CMOS Digital Interface
• Histogram Module
• Resize Image 1/16x to 8x Processing
• Hardware On-Screen Display • Up to 14-bit CCD/CMOS Digital Interface
• Up to 75-MHz Pixel Clock • 16-/8-bit Generic YcBcR-4:2 Interface
• Composite NTSC/PAL video encoder output • 10-/8-bit CCIR6565/BT655 Interface
– Peripherals include DDR and mDDR SDRAM, • Up to 75-MHz Pixel Clock
2 MMC/SD/SDIO and SmartMedia Flash Card
Interfaces, USB 2.0, 3 UARTs and 3 SPIs – Enhanced Direct-Memory-Access (EDMA) – Configurable Power-Saving Modes – On-Chip ARM ROM Bootloader (RBL) to Boot
From NAND Flash, MMC/SD, or UART – 3.3-V and 1.8-V I/O, 1.3-V Core – Debug Interface Support – Up to 104 General-Purpose I/O (GPIO) Pins – 337-Pin Ball Grid Array at 65 nm Process
Technology
• High-Performance Digital Media System-on-Chip (DMSoC)
– 135-, 216-MHz ARM926EJ-S™ Clock Rate – Fully Software-Compatible With ARM™ – Extended Temperature 135- and 216-MHz
Devices are Available
• ARM926EJ-S Core – Support for 32-Bit and 16-Bit (Thumb Mode)
Instruction Sets
– DSP Instruction Extensions and Single Cycle
MAC
– ARM® Jazelle® Technology
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2Windows is a trademark of Microsoft. 3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
– EmbeddedICE-RT™ Logic for Real-Time
Debug
• ARM9 Memory Architecture – 16K-Byte Instruction Cache – 8K-Byte Data Cache
• Video Processing Subsystem – Front End Provides:
• Hardware IPIPE for Real-Time Image
(BT.601)
• Histogram Module
• Resize Engine – Resize Images From 1/16x to 8x – Separate Horizontal/Vertical Control – Two Simultaneous Output Paths
– Back End Provides:
• Hardware On-Screen Display (OSD)
• Composite NTSC/PAL video encoder output
• 8-/16-bit YCC and Up to 18-Bit RGB666 Digital Output
• BT.601/BT.656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface
• Digital HDTV (720p/1080i) output for connection to external encoder
• External Memory Interfaces (EMIFs) – DDR2 and mDDR SDRAM 16-bit wide EMIF
With 256 MByte Address Space (1.8-V I/O)
– Asynchronous16-/8-bit Wide EMIF (AEMIF)
• Flash Memory Interfaces – NAND (8-/16-bit Wide Data) – OneNAND(16-bit Wide Data)
• Flash Card Interfaces
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TMS320DM335
SPRS528C–JULY 2008–REVISED JUNE 2010
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– Two Multimedia Card (MMC) / Secure Digital • Four Pulse Width Modulator (PWM) Outputs
(SD/SDIO)
– SmartMedia
• Four RTO (Real Time Out) Outputs
• Up to 104 General-Purpose I/O (GPIO) Pins
• Enhanced Direct-Memory-Access (EDMA) (Multiplexed with Other Device Functions) Controller (64 Independent Channels)
• On-Chip ARM ROM Bootloader (RBL) to Boot
• USB Port with Integrated 2.0 High-Speed PHY from NAND Flash (with SPI EEPROM Boot that Supports option), MMC/SD, or UART
– USB 2.0 Full and High-Speed Device • Configurable Power-Saving Modes – USB 2.0 Low, Full, and High-Speed Host • Crystal or External Clock Input (typically
• Three 64-Bit General-Purpose Timers (each
24 MHz or 36 MHz)
configurable as two 32-bit timers) • Flexible PLL Clock Generators
• One 64-Bit Watch Dog Timer • Debug Interface Support
• Three UARTs (One fast UART with RTS and – IEEE-1149.1 (JTAG) CTS Flow Control) Boundary-Scan-Compatible
• Three Serial Port Interfaces (SPI) each with two – ETB™ (Embedded Trace Buffer™) with Chip-Selects 4K-Bytes Trace Buffer memory
• One Master/Slave Inter-Integrated Circuit (I2C) – Device Revision ID Readable by ARM Bus®
• 337-Pin Ball Grid Array (BGA) Package
• Two Audio Serial Port (ASP) (ZCE Suffix), 0.65-mm Ball Pitch – I2S and TDM I2S • 90nm Process Technology – AC97 Audio Codec Interface • 3.3-V and 1.8-V I/O, 1.3-V Internal – S/PDIF via Software • Community Resources – Standard Voice Codec Interface (AIC12) – TI E2E Community – SPI Protocol (Master Mode Only) – TI Embedded Processors Wiki
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1.2 Description

The DM335 processor is a low-cost, low-power processor providing advanced graphical user interface for display applications that do not require video compression and decompression. Coupled with a video processing subsystem (VPSS) that provides 720p display, the DM335 processor is powered by a 135/216-MHz ARM926EJ-S core so developers can create feature-rich graphical user interfaces allowing customers to interact with their portable, electronic devices such as video-enabled universal remote controls, Internet radio, e-books, video doorbells, and digital telescopes. The new DM335 is packed with the same peripherals as its predecessor, the TMS320DM355 device, including high-speed USB 2.0 on-the-go, external memory interface (EMIF), mobile DDR/DDR2, two SDIO ports, three UART Ports, two Audio Serial Ports, three SPI Ports, and SLC/MCL NAND Flash memory support. These peripherals help customers create DM335 processor-based designs that add video and audio excitement to a wide range of today's static user-interface applications while keeping silicon costs and power consumption low. The new digital media processor is completely scalable with the DM355 processor and Digital Video Evaluation Board (DVEVM), allowing customers to utilize their same code for their new DM335 processor focused designs.
The new DM335 device delivers a sophisticated suite of capabilities allowing for flexible image capture and display. Through its user interface technology, such as a four-level on-screen display, developers are able to create picture-within-picture and video-within-video as well as innovative graphic user interfaces. This is especially important for portable products that require the use of button or touch screen, such as portable karaoke, video surveillance and electronic gaming applications. Additional advanced capture and imaging technologies include support for CCD/CMOS image sensors, resize capability and video stabilization. The 1280-by-960-pixel digital LCD connection runs on a 75-MHz pixel clock and supports TV composite output for increased expandability. This highly integrated device is packaged in a 13 x 13 mm, 337 pin , 0.65 mm pitch BGA package.
SPRS528C–JULY 2008–REVISED JUNE 2010
The DM335 processor core is an ARM926EJ-S RISC processor. The ARM926EJ-S is a 32-bit processor core that performs 32-bit and 16-bit instructions and processes 32-bit, 16-bit, and 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously. The ARM core incorporates:
• A coprocessor 15 (CP15) and protection module
• Data and program Memory Management Units (MMUs) with table look-aside buffers.
• Separate 16K-byte instruction and 8K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT).
The DM335 device has a Video Processing Subsystem (VPSS) with two configurable video/imaging peripherals:
• A Video Processing Front-End (VPFE)
• A Video Processing Back-End (VPBE)
The VPFE port provides an interface for CCD/CMOS imager modules and video decoders. The VPBE provides hardware On Screen Display (OSD) support and composite NTSC/PAL and digital LCD output.
The DM335 peripheral set includes:
• An inter-integrated circuit (I2C) Bus interface
• Two audio serial ports (ASP)
• Three 64-bit general-purpose timers each configurable as two independent 32-bit timers
• A 64-bit watchdog timer
• Up to 104-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals
• Three UARTs with hardware handshaking support on one UART
• Three serial port Interfaces (SPI)
• Four pulse width modulator (PWM) peripherals
• Four real time out (RTO) outputs
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Peripherals
64bitDMA/DataBus
JTAG
24MHz
or36MHz
27MHz
(optional)
CCD/
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PLL
CLOCKctrl
PLLs
JTA
JTAG
I/F
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16 K
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16KB
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32 K
B
RAM
32KB
B
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8K
D-cache
8KB
RO
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8 K
ROM
8KB
CCD
C
3A
H3A
DMA / Dataandconfigurationbus
DMA/Dataandconfigurationbus
DDR
MH
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DDR
controller
DL
DLL/ PHY
16bit
32bitConfigurationBus
CCDC
IPIPE
VPBE
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Video
Encoder
10b
DAC
OS
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ARMINTC
Enhanced
channels 3PCC /TC
(100 MHz
EnhancedDMA
64channels
Compositevideo
DigitalRGB/YUV
Nand /
Nand/SM/
Async/OneNand
(AEMIF)
USB 2 .0
USB2.0PHY
Speaker microphone
ASP (2x)
BufferLogic
VPSS
MMC/SD(x2)
SPII/F(x3)
UART (x3)
I2C
Timer/
WDT (x4-64)
GIO
PWM(x4)
RTO
VPFE
TMS320DM335
SPRS528C–JULY 2008–REVISED JUNE 2010
• Two Multi-Media Card / Secure Digital (MMC/SD/SDIO) interfaces
• Wireless interfaces (Bluetooth, WLAN, WUSB) through SDIO
• A USB 2.0 full and high-speed device and host interface
• Two external memory interfaces: – An asynchronous external memory interface (AEMIF) for slower memories/peripherals such as
NAND and OneNAND,
– A high speed synchronous memory interface for DDR2/mDDR.
For software development support the DM335 has a complete set of ARM development tools which include: C compilers, assembly optimizers to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

1.3 Functional Block Diagram

The below figure shows the functional block diagram of the DM335 device.
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4 Digital Media System-on-Chip (DMSoC) Copyright © 2008–2010, Texas Instruments Incorporated
Figure 1-1. Functional Block Diagram
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1 Digital Media System-on-Chip (DMSoC) ............ 1
1.1 TMS320DM335 Features ............................ 1 3.9 Pin Multiplexing ..................................... 79
1.2 Description ........................................... 3 3.10 Device Reset ....................................... 80
1.3 Functional Block Diagram ............................ 4
Revision History .............................................. 6
2 Device Overview ........................................ 7
2.1 Device Characteristics ............................... 7
2.2 Memory Map Summary .............................. 8
2.3 Pin Assignments .................................... 10
2.4 Pin Functions ....................................... 14
2.5 Image Data Output - Video Processing Back End
(VPBE) .............................................. 16
2.6 Asynchronous External Memory Interface (AEMIF)
...................................................... 19
2.7 DDR Memory Interface ............................. 21
2.8 GPIO ................................................ 23
2.9 Multi-Media Card/Secure Digital (MMC/SD)
Interfaces ........................................... 28
2.10 Universal Serial Bus (USB) Interface ............... 29
2.11 Audio Interfaces .................................... 30
2.12 UART Interface ..................................... 31
2
2.13 I
C Interface ........................................ 32
2.14 Serial Interface ..................................... 32
2.15 Clock Interface ...................................... 33
2.16 Real Time Output (RTO) Interface ................. 34
2.17 Pulse Width Modulator (PWM) Interface ........... 34
2.18 System Configuration Interface ..................... 35
2.19 Emulation ........................................... 36
2.20 Pin List .............................................. 37
2.21 Device Support ..................................... 56
3 Detailed Device Description ......................... 61
3.1 ARM Subsystem Overview ......................... 61
3.2 ARM926EJ-S RISC CPU ........................... 62
3.3 Memory Mapping ................................... 64
3.4 ARM Interrupt Controller (AINTC) .................. 65
3.5 Device Clocking .................................... 67
3.6 PLL Controller (PLLC) .............................. 74
3.7 Power and Sleep Controller (PSC) ................. 78
3.8 System Control Module ............................. 78
3.11 Default Device Configurations ...................... 81
3.12 Device Boot Modes ................................. 85
3.13 Power Management ................................ 89
3.14 64-Bit Crossbar Architecture ....................... 91
4 Device Operating Conditions ....................... 95
4.1 Absolute Maximum Ratings Over Operating Case Temperature Range
(Unless Otherwise Noted) ................................. 95
4.2 Recommended Operating Conditions .............. 96
4.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case
Temperature (Unless Otherwise Noted) ............ 97
5 DM335 Peripheral Information and Electrical
Specifications .......................................... 98
5.1 Parameter Information Device-Specific Information
...................................................... 98
5.2 Recommended Clock and Control Signal Transition
Behavior ............................................ 99
5.3 Power Supplies ..................................... 99
5.4 Reset .............................................. 101
5.5 Oscillators and Clocks ............................ 102
5.6 General-Purpose Input/Output (GPIO) ............ 107
5.7 External Memory Interface (EMIF) ................ 109
5.8 MMC/SD ........................................... 117
5.9 Video Processing Sub-System (VPSS) Overview
..................................................... 119
5.10 USB 2.0 ........................................... 131
5.11 Universal Asynchronous Receiver/Transmitter
(UART) ............................................ 133
5.12 Serial Port Interface (SPI) ......................... 135
5.13 Inter-Integrated Circuit (I2C) ...................... 138
5.14 Audio Serial Port (ASP) ........................... 141
5.15 Timer .............................................. 149
5.16 Pulse Width Modulator (PWM) .................... 150
5.17 Real Time Out (RTO) ............................. 152
5.18 IEEE 1149.1 JTAG ................................ 153
6 Mechanical Data ...................................... 156
6.1 Thermal Data for ZCE ............................. 156
6.2 Packaging Information ............................ 156
SPRS528C–JULY 2008–REVISED JUNE 2010
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NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
This data sheet revision history highlights the technical changes made to the SPRS528B device-specific data sheet to make it an SPRS528C revision.
Scope: Applicable updates to the DM335 device family, specifically relating to the DM335 device, have been incorporated. The A135 and A216 DM335 devices both support extended temperature.
Global Added SPI EEPROM Boot option to NAND.
Section 1.1 Changed Feature bullet from NAND Flash to NAND Flash (with SPI EEPROM Boot option). Section 2.4 Table 2-9 and Table 2-11:
Section 2.20 Updated Table 2-23, changed Reset State values. Section 2.21.2 Updated Figure 2-5 Device Nomenclature. Section 3.2.4 Changed NAND to NAND (with SPI EEPROM Boot option). Section 3.5 Table 3-4:
Table 3-15 Updated BTSEL Function and NAND configuration in table. Table 3-16 Updated table:
Section 3.12 Added Section 3.12.2, "RBL NAND Boot Process" and associated Standard and Compatibility
Section 3.12.1 Added ARM ROM Boot - SPI boot in NAND Mode bullet and sub-bullets. Figure 3-6 Added SPI Flash to Diagram. Section 4.2 Added last row to table including table note. Section 4.3 Updated/Changed the following values in Section 4.3:
Table 5-5 Changed parameter 4 on table and added table note. Table 5-6 Changed parameter 4 on table and added table note. Table 5-45 Changed parameter 4 on table and added table note. Section 5.7.1.3 Added note to Table 5-14.
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Revision History

Revision C Updates
ADDS/CHANGES/DELETES
• Added "Used to drive boot status LED signal (active low) in ROM boot modes." to pin number P16.
• Deleted "Used to drive boot status LED signal (active low) in ROM boot modes." from pin number V19.
• Updated/Changed "(/2 or /1 programmable)" to "POSTDIV" and added "(/2 or /1 programmable)" to 2nd row.
• Changed BTSEL[1:0] = 00 – Enable (NAND) to BTSEL[1:0] = 00 – Enable (NAND, SPI)
Changed SPI0 Module State from SyncRst to:
• BTSEL[1:0] = 00 – Enable (NAND, SPI)
• BTSEL[1:0] = 01 – SyncRst (OneNAND)
• BTSEL[1:0] = 10 – Enable (MMC/SD)
• BTSEL[1:0] = 11 – Enable (UART)
mode references throughout the document.
• IOHMAX value from "-100 mA" to "-4000 mA"
• IOZTYP (IPU disabled) value from "±10 µA" to "±20 µA"
• IOZTYP (IPU enabled) added value of ±100 µA"
Added "Test Conditions" for IOHand IOLparameters
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2 Device Overview

2.1 Device Characteristics

Table 2-1 provides an overview of the DMSoC. The table shows significant features of the device,
including the peripherals, capacity of on-chip RAM, ARM operating frequency, the package type with pin count, etc.
Table 2-1. Characteristics of the Processor
HARDWARE FEATURES DM335
DDR2 / mDDR Memory Controller DDR2 / mDDR (16-bit bus width) Asynchronous EMIF (AEMIF)
Flash Card Interfaces
EDMA
Peripherals Not all peripherals pins are
available at the same time (For more detail, see the Device Configuration section).
On-Chip CPU Memory Organization 16-KB I-cache, 8-KB D-cache,
JTAG BSDL_ID JTAGID register (address location: 0x01C4 0028) 0x0B73B01F CPU Frequency (Maximum) MHz ARM 135, 216 MHz
Voltage
PLL Options BGA Package 13 x 13 mm 337-Pin BGA (ZCE)
Process Technology 90 nm
Product Status
(1) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
(1)
Timers
UART
SPI I2C One (Master/Slave)
Audio Serial Port [ASP] Two ASP General-Purpose Input/Output Port Up to 104 Pulse width modulator (PWM) Four outputs
Configurable Video Ports
USB 2.0
Core (V) 1.3 V I/O (V) 3.3 V, 1.8 V Reference frequency options 24 MHz (typical), 36 MHz
Configurable PLL controller PLL bypass, programmable PLL
Product Preview (PP), Advance Information (AI), PD or Production Data (PD)
Asynchronous (8/16-bit bus width)
RAM, Flash (NAND, OneNAND)
Two MMC/SD
One SmartMedia/xD
64 independent DMA channels
Eight EDMA channels
Three 64-Bit General Purpose (each
configurable as two separate 32-bit
timers)
One 64-Bit Watch Dog
Three (one with RTS and CTS flow
control)
Three (each supports two slave
devices)
One Input (VPFE)
One Output (VPBE)
High, Full Speed Device
High, Full, Low Speed Host
ARM
32-KB RAM, 8-KB ROM
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2.2 Memory Map Summary

Table 2-3 shows the memory map address ranges of the device. Table 2-3 depicts the expanded map of
the Configuration Space (0x01C0 0000 through 0x01FF FFFF). The device has multiple on-chip memories associated with its processor and various subsystems. To help simplify software development a unified memory map is used where possible to maintain a consistent view of device resources across all bus masters. The bus masters are the ARM, EDMA, USB, and VPSS.
Table 2-2. DM335 Memory Map
Start Address End Address Size (Bytes) ARM EDMA USB VPSS
0x0000 0000 0x0000 3FFF 16K ARM RAM0
0x0000 4000 0x0000 7FFF 16K ARM RAM1
0x0000 8000 0x0000 FFFF 32K ARM ROM
0x0001 0000 0x0001 3FFF 16K ARM RAM0 (Data) ARM RAM0 ARM RAM0 0x0001 4000 0x0001 7FFF 16K ARM RAM1 (Data) ARM RAM1 ARM RAM1 0x0001 8000 0x0001 FFFF 32K ARM ROM (Data) ARM ROM ARM ROM
0x0002 0000 0x000F FFFF 896K Reserved
0x0010 0000 0x01BB FFFF 26M 0x01BC 0000 0x01BC 0FFF 4K ARM ETB Mem 0x01BC 1000 0x01BC 17FF 2K ARM ETB Reg Reserved 0x01BC 1800 0x01BC 18FF 256 ARM IceCrusher Reserved 0x01BC 1900 0x01BC FFFF 59136 Reserved 0x01BD 0000 0x01BF FFFF 192K 0x01C0 0000 0x01FF FFFF 4M CFG Bus CFG Bus
0x0200 0000 0x09FF FFFF 128M ASYNC EMIF (Data) ASYNC EMIF (Data)
0x0A00 0000 0x11EF FFFF 127M - 16K
0x11F0 0000 0x11F1 FFFF 128K Reserved Reserved
0x11F2 0000 0x1FFF FFFF 141M-64K
0x2000 0000 0x2000 7FFF 32K DDR EMIF Control DDR EMIF Control
0x2000 8000 0x41FF FFFF 544M-32K Reserved
0x4200 0000 0x49FF FFFF 128M Reserved Reserved
0x4A00 0000 0x7FFF FFFF 864M Reserved
0x8000 0000 0x8FFF FFFF 256M DDR EMIF DDR EMIF DDR EMIF DDR EMIF
0x9000 0000 0xFFFF FFFF 1792M Reserved Reserved Reserved Reserved
Mem Map Mem Map Mem Map Mem Map
(Instruction)
(Instruction)
(Instruction)
- only 8K used
- only 8K used
Peripherals Peripherals
Regs Regs
Reserved Reserved
Reserved
Table 2-3. DM335 ARM Configuration Bus Access to Peripherals
Address Accessibility
Region Start End Size ARM EDMA
EDMA CC 0x01C0 0000 0x01C0 FFFF 64K √ √ EDMA TC0 0x01C1 0000 0x01C1 03FF 1K √ √ EDMA TC1 0x01C1 0400 0x01C1 07FF 1K √ √
Reserved 0x01C1 0800 0x01C1 9FFF 38K √ √ Reserved 0x01C1 A000 0x01C1 FFFF 24K √ √
UART0 0x01C2 0000 0x01C2 03FF 1K √ √
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Table 2-3. DM335 ARM Configuration Bus Access to Peripherals (continued)
Address Accessibility
UART1 0x01C2 0400 0x01C2 07FF 1K √ √
Timer4/5 0x01C2 0800 0x01C2 0BFF 1K √ √
Real-time out 0x01C2 0C00 0x01C2 0FFF 1K √ √
I2C 0x01C2 1000 0x01C2 13FF 1K √ √ Timer0/1 0x01C2 1400 0x01C2 17FF 1K √ √ Timer2/3 0x01C2 1800 0x01C2 1BFF 1K √ √
WatchDog Timer 0x01C2 1C00 0x01C2 1FFF 1K √ √
PWM0 0x01C2 2000 0x01C2 23FF 1K √ √ PWM1 0x01C2 2400 0x01C2 27FF 1K √ √ PWM2 0x01C2 2800 0x01C2 2BFF 1K √ √ PWM3 0x01C2 2C00 0x01C2 2FFF 1K √ √
System Module 0x01C4 0000 0x01C4 07FF 2K √ √ PLL Controller 0 0x01C4 0800 0x01C4 0BFF 1K √ √ PLL Controller 1 0x01C4 0C00 0x01C4 0FFF 1K √ √
Power/Sleep Controller 0x01C4 1000 0x01C4 1FFF 4K √ √
Reserved 0x01C4 2000 0x01C4 7FFF 24K √ √
ARM Interrupt Controller 0x01C4 8000 0x01C4 83FF 1K √ √
Reserved 0x01C4 8400 0x01C6 3FFF 111K √ √
USB OTG 2.0 Regs / RAM 0x01C6 4000 0x01C6 5FFF 8K √ √
SPI0 0x01C6 6000 0x01C6 67FF 2K √ √ SPI1 0x01C6 6800 0x01C6 6FFF 2K √ √
GPIO 0x01C6 7000 0x01C6 77FF 2K √ √
SPI2 0x01C6 7800 0x01C6 FFFF 2K √ √
VPSS Subsystem 0x01C7 0000 0x01C7 FFFF 64K √ √
VPSS Clock Control 0x01C7 0000 0x01C7 007F 128 √ √
Hardware 3A 0x01C7 0080 0x01C7 00FF 128 √ √
Image Pipe (IPIPE) Interface 0x01C7 0100 0x01C7 01FF 256 √ √
On Screen Display 0x01C7 0200 0x01C7 02FF 256 √ √
Reserved 0x01C7 0300 0x01C7 03FF 256 √ √
Video Encoder 0x01C7 0400 0x01C7 05FF 512 √ √
CCD Controller 0x01C7 0600 0x01C7 07FF 256 √ √
VPSS Buffer Logic 0x01C7 0800 0x01C7 08FF 256 √ √
Reserved 0x01C7 0900 0x01C7 09FF 256 √ √
Image Pipe (IPIPE) 0x01C7 1000 0x01C7 3FFF 12K √ √
Reserved 0x01C7 4000 0x01CD FFFF 432K √ √
Multimedia / SD 1 0x01E0 0000 0x01E0 1FFF 8K √ √
ASP0 0x01E0 2000 0x01E0 3FFF 8K √ √ ASP1 0x01E0 4000 0x01E0 5FFF 8K √ √
UART2 0x01E0 6000 0x01E0 63FF 1K √ √
Reserved 0x01E0 6400 0x01E0 FFFF 39K √ √
ASYNC EMIF Control 0x01E1 0000 0x01E1 0FFF 4K √ √
Multimedia / SD 0 0x01E1 1000 0x01E1 FFFF 60K √ √
Reserved 0x01E2 0000 0x01FF FFFF 1792K √ √ ASYNC EMIF Data (CE0) 0x0200 0000 0x03FF FFFF 32M √ √ ASYNC EMIF Data (CE1) 0x0400 0000 0x05FF FFFF 32M √ √
Reserved 0x0600 0000 0x09FF FFFF 64M √ √
Reserved 0x0A00 0000 0x0BFF FFFF 32M √ √
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SSA_PLL2
7
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DDA33_USB
6
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G
V
DDA13_USB
V
SS
F
E
D
CIN2
C
B
A
VREF
CIN3CIN0
V
DDA_PLL2
V
SS
LCD_OE
FIELDVCLK
V
SS
V
SS
CV
DD
VSYNCEXTCLKVFB
V
DD_VOUT
V
DD_VOUT
V
DD_VOUT
HSYNCCOUT0COUT1TVOUT
TDOEMU0EMU1
V
SS_USB
USB_VBUS
COUT2COUT3IOUT
TDITMS
V
SS_USB
USB_IDCOUT4
V
SS
TRST
V
SS_USB_REF
USB_R1
V
DDD13_USB
USB_DRV
VBUS
CV
DD
YOUT7COUT5
MXO1
V
SS
V
SS_USB
V
DDA33_USB_
PLL
V
SS
YOUT5YOUT4YOUT0
MXI1
V
SS
USB_DPUSB_DM
V
SS
YOUT6YOUT2
CV
DD
2
V
SS
V
SS
V
SS
IBIAS
V
SS
COUT6
COUT7
YOUT3
YOUT1
RSV01
V
DD
V
DD
NC
TMS320DM335
SPRS528C–JULY 2008–REVISED JUNE 2010
Table 2-3. DM335 ARM Configuration Bus Access to Peripherals (continued)
Reserved 0x0C00 0000 0x0FFF FFFF 64M √ √

2.3 Pin Assignments

Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in the smallest possible package. Pin multiplexing is controlled using a combination of hardware configuration at device reset and software programmable register settings.

2.3.1 Pin Map (Bottom View)

Figure 2-1 through Figure 2-4 show the pin assignments in four quadrants (A, B, C, and D). Note that
micro-vias are not required. Contact your TI representative for routing recommendations.
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Address Accessibility
Figure 2-1. Pin Map [Quadrant A]
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W
9
DDR_CLK
8
DDR_CLK
7654
DDR_A05
32
DDR_A02
1
V
DDR_A07DDR_A04DDR_A00
U
V
SS
T
PCLK
R
P
N
M
L
K
DDR_A11DDR_A09DDR_A08
V
SS
DDR_CAS
DDR_BA[2]
DDR_A12DDR_A10DDR_A01
V
SS
DDR_BA[0]DDR_BA[1]
DDR_A13DDR_A06
DDR_A03
V
SS
V
SS
V
SS
V
SS
DDR_ZNDDR_CSDDR_RAS
V
SS
V
SS
MXO2
V
DD_DDR
CV
DD
CV
DD
V
SS
CAM_WEN_
FIELD
CAM_VDYIN3
V
SS
MXI2
V
DD_DDR
V
DD_VIN
YIN0YIN2YIN4YIN1V
SS_MX2
V
SS
V
SS
CV
DD
CAM_HDCIN7
RSV05
V
SS
V
DD_DDR
V
SS
V
SS
V
SS
YIN5
YIN6CIN5
RSV06
RSV04
V
SS
V
SS_DAC
V
DDA18V_DAC
V
DD
YIN7CIN4CIN1
V
SS
RSV03
V
SS
V
DD
CV
DD
CIN6
V
SS
RSV07RSV02
V
DD_VIN
V
DD_VIN
TMS320DM335
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SPRS528C–JULY 2008–REVISED JUNE 2010
Figure 2-2. Pin Map [Quadrant B]
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CV
DD
19
W
18
DDR_
DQGATE0
17
DDR_DQ15
16
DDR_DQ13
15
DDR_DQ11
14
DDR_DQ10
13
DDR_DQ07
12
DDR_DQ05
11
DDR_DQ01
10
DDR_WE
EM_A13
V
V
SS
DDR_
DQGATE1
DDR_DQ14DDR_DQS[1]
DDR_DQ09DDR_DQ06
DDR_DQS[0]DDR_DQ00
DDR_CKE
EM_A12
U
UART0_RXD
V
SS
DDR_DQ12DDR_DQM[1]
V
SS
DDR_DQ08DDR_DQ04DDR_DQ02
DDR_VREF
EM_A08
T
UART0_TXD
CV
DD
V
SS
V
DD_DDR
DDR_DQM[0]
DDR_DQ03
EM_A05
R
EM_A10
UART1_TXD
EM_A11
UART1_RXD
I2C_SCLI2C_SDA
V
DD_DDR
V
SSA_DLL
V
DDA33_DDRDLL
EM_BA1
P
EM_A06
EM_A09EM_A07EM_A04
V
DD_DDR
EM_BA0
N
EM_A03EM_A01EM_A02
V
SS
V
DD
V
DD
EM_D14
M
EM_D15
V
SS
EM_A00EM_D13
V
SS
V
DD
EM_D10
L
EM_D12EM_D11EM_D08EM_D04
CV
DD
V
SS
EM_D07
K
EM_D09EM_D06
V
DD_DDR
V
DD_DDR
V
DD_DDR
V
DD_DDR
V
DD
V
DD
V
DD
CV
DD
V
DD
V
SS
CV
DD
CV
DD
V
SS
V
SS
V
DD
TMS320DM335
SPRS528C–JULY 2008–REVISED JUNE 2010
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Figure 2-3. Pin Map [Quadrant C]
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19181716151413121110
EM_D05
J
EM_D02
H
EM_CE1
G
F
E
D
C
V
DD
B
A
EM_D03EM_D01EM_CE0EM_WE
V
SS
EM_D00
EM_ADV
ASP0_DX
V
SSA_PLL1
CV
DD
EM_WAIT
ASP0_FSX
GIO003
V
DDA_PLL1
EM_OE
ASP0_CLKXASP0_CLKRASP0_FSR
GIO002
EM_CLK
ASP0_DRASP1_FSRASP1_FSX
GIO001
SPI1_
SDENA[0]
SPI1_SDORTCKTCK
ASP1_CLKXASP1_CLKRASP1_CLKS
GIO005
MMCSD0_
DATA1
CLKOUT1RESET
ASP1_DRASP1_DX
GIO007GIO000
MMCSD1_CLK
MMCSD0_CMDSPI1_SCLKSPI0_SCLK
CLKOUT3
V
SS_MX1
GIO006
MMCSD1_
DATA0
MMCSD1_
DATA3
MMCSD1_
DATA2
GIO004
MMCSD1_
CMD
MMCSD1_
DATA1
MMCSD0_
CLK
MMCSD0_
DATA0
MMCSD0_
DATA3
MMCSD0_
DATA2
SPI1_SDI
SPI0_
SDENA[0]
SPI0_SDI
SPI0_SDO
CLKOUT2
V
SS
CV
DD
CV
DD
CV
DD
V
SS
CV
DD
V
SS
CV
DD
CV
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
CV
DD
V
SS
V
SS
CV
DD
TMS320DM335
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SPRS528C–JULY 2008–REVISED JUNE 2010
Figure 2-4. Pin Map [Quadrant D]
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2.4 Pin Functions

The pin functions tables (Table 2-4 through Table 2-22) identify the external signal names, the associated pin (ball) numbers along with the mechanical package designator, the pin type, whether the pin has any internal pullup or pulldown resistors, and a functional pin description. For more detailed information on device configuration, peripheral selection, multiplexed/shared pins, and debugging considerations, see
Section 3. For the list of all pin in chronological order see Section 2.20

2.4.1 Image Data Input - Video Processing Front End

The CCD Controller module in the Video Processing Front End has an external signal interface for image data input. It supports YUV (YC) inputs as well as Bayer RGB and complementary input signals (I.e., image data input).
The definition of the CCD controller data input signals depend on the input mode selected.
• In 16-bit YCbCr mode, the Cb and Cr signals are multiplexed on the Cl signals and the order is configurable (i.e., Cb first or Cr first).
• In 8-bit YCbCr mode, the Y, Cb, and Cr signals are multiplexed and not only is the order selectable, but also the half of the bus used.
Table 2-4. CCD Controller Signals for Each Input Mode
PIN NAME CCD 16-BIT YCbCr 8-BIT YCbCr
Cl7 Cb7,Cr7 Y7,Cb7,Cr7 Cl6 Cb6,Cr6 Y6,Cb6,Cr6 Cl5 CCD13 Cb5,Cr5 Y5,Cb5,Cr5 Cl4 CCD12 Cb4,Cr4 Y4,Cb4,Cr4 Cl3 CCD11 Cb3,Cr3 Y3,Cb3,Cr3 Cl2 CCD10 Cb2,Cr2 Y2,Cb2,Cr2 Cl1 CCD9 Cb1,Cr1 Y1,Cb1,Cr1 Cl0 CCD8 Cb0,Cr0 Y0,Cb0,Cr0 Yl7 CCD7 Y7 Y7,Cb7,Cr7 Yl6 CCD6 Y6 Y6,Cb6,Cr6 Yl5 CCD5 Y5 Y5,Cb5,Cr5 Yl4 CCD4 Y4 Y4,Cb4,Cr4 Yl3 CCD3 Y3 Y3,Cb3,Cr3 Yl2 CCD2 Y2 Y2,Cb2,Cr2 Yl1 CCD1 Y1 Y1,Cb1,Cr1 Yl0 CCD0 Y0 Y0,Cb0,Cr0
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Table 2-5. CCD Controller/Video Input Terminal Functions
TERMINAL
NAME NO.
CIN7/ GIO101/ N3 I/O/Z SPI2_SCLK
CIN6/ GIO100/ K5 I/O/Z SPI2_SDO
CIN5/ • YCC 16-bit: Time multiplexed between chroma: CB/SR[05] GIO099/ PD SPI2_SDEN V
M3 I/O/Z
A[0]
CIN4/ • YCC 16-bit: Time multiplexed between chroma: CB/SR[04] GIO098/ PD SPI2_SDEN V
L4 I/O/Z
A[1]
CIN3/ PD GIO097/ V
CIN2/ PD GIO096/ V
CIN1/ PD GIO095/ V
CIN0/ PD GIO094/ V
YIN7/ PD GIO093 V
YIN6/ PD GIO092 V
J4 I/O/Z
J5 I/O/Z
L3 I/O/Z
J3 I/O/Z
L5 I/O/Z
M4 I/O/Z
TYPE
(1)
OTHER
(2) (3)
DESCRIPTION
Standard CCD/CMOS input: NOT USED
• YCC 16-bit: Time multiplexed between chroma: CB/SR[07]
PD
V
DD_VIN
• YCC 8-bit (which allows for two simultaneous decoder inputs), it is time multiplexed between luma and chroma of the upper channel. Y/CB/CR[07]
SPI: SPI2 Clock GIO: GIO[101]
Standard CCD/CMOS input: NOT USED
• YCC 16-bit: Time multiplexed between chroma: CB/SR[06]
PD
V
DD_VIN
• YCC 8-bit (which allows for two simultaneous decoder inputs), it is time multiplexed between luma and chroma of the upper channel. Y/CB/CR[06]
SPI: SPI2 Data Out GIO: GIO[100]
Standard CCD/CMOS input: Raw[13]
• YCC 8-bit (which allows for two simultaneous decoder inputs), it is time
DD_VIN
multiplexed between luma and chroma of the upper channel. Y/CB/CR[05]
SPI: SPI2 Chip Select GIO: GIO[099]
Standard CCD/CMOS input: Raw[12]
• YCC 8-bit (which allows for two simultaneous decoder inputs), it is time
DD_VIN
multiplexed between luma and chroma of the upper channel. Y/CB/CR[04]
SPI: SPI2 Data In GIO: GIO[098]
Standard CCD/CMOS input(AFE): Raw[11]
• YCC 16-bit: Time multiplexed between chroma: CB/SR[03]
DD_VIN
• YCC 8-bit (which allows for two simultaneous decoder inputs), it is time multiplexed between luma and chroma of the upper channel. Y/CB/CR[03]
GIO: GIO[097] Standard CCD/CMOS input: Raw[10]
• YCC 16-bit: Time multiplexed between chroma: CB/SR[02]
DD_VIN
• YCC 8-bit (which allows for two simultaneous decoder inputs), it is time multiplexed between luma and chroma of the upper channel. Y/CB/CR[02]
GIO: GIO[097] Standard CCD/CMOS input: Raw[09]
• YCC 16-bit: Time multiplexed between chroma: CB/SR[01]
DD_VIN
• YCC 8-bit (which allows for two simultaneous decoder inputs), it is time multiplexed between luma and chroma of the upper channel. Y/CB/CR[01]
GIO: GIO[095] Standard CCD/CMOS input: Raw[08]
• YCC 16-bit: Time multiplexed between chroma: CB/SR[00]
DD_VIN
• YCC 8-bit (which allows for two simultaneous decoder inputs), it is time multiplexed between luma and chroma of the upper channel. Y/CB/CR[00]
GIO: GIO[094] Standard CCD/CMOS input: Raw[07]
• YCC 16-bit: Time multiplexed between chroma: Y[07]
DD_VIN
• YCC 8-bit (which allows for two simultaneous decoder inputs), it is time multiplexed between luma and chroma of the upper channel. Y/CB/CR[07]
GIO: GIO[093] Standard CCD/CMOS input: Raw[06]
• YCC 16-bit: Time multiplexed between chroma: Y[06]
DD_VIN
• YCC 8-bit (which allows for two simultaneous decoder inputs), it is time multiplexed between luma and chroma of the upper channel. Y/CB/CR[06]
GIO: GIO[092]
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal. (2) PD = internal pull-down, PU = internal pull-up. (To pull up a signal to the opposite supply rail, a 1 kΩ resistor should be used.) (3) Specifies the operating I/O supply voltage for each signal. See Section 5.3 , Power Supplies for more detail.
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Table 2-5. CCD Controller/Video Input Terminal Functions (continued)
TERMINAL
NAME NO.
YIN5/ PD GIO091 V
YIN4/ PD GIO090 V
YIN3/ PD GIO089 V
YIN2/ PD GIO088 V
YIN1/ PD GIO087 V
YIN0/ PD GIO086 V
CAM_HD/ PD GIO085 V
CAM_VD PD GIO084 V
M5 I/O/Z
P3 I/O/Z
R3 I/O/Z
P4 I/O/Z
P2 I/O/Z
P5 I/O/Z
N5 I/O/Z output (master mode). Tells the CCDC when a new line starts.
R4 I/O/Z (master mode). Tells the CCDC when a new frame starts.
CAM_WEN _FIELD\ R5 I/O/Z GIO083
PCLK/ PD Pixel clock input (strobe for lines C17 through Y10) GIO082 V
T3 I/O/Z
TYPE
(1)
OTHER
(2) (3)
DESCRIPTION
Standard CCD/CMOS input: Raw[05]
• YCC 16-bit: Time multiplexed between chroma: Y[05]
DD_VIN
• YCC 8-bit (which allows for two simultaneous decoder inputs), it is time multiplexed between luma and chroma of the upper channel. Y/CB/CR[05]
GIO: GIO[091] Standard CCD/CMOS input: Raw[04]
• YCC 16-bit: Time multiplexed between chroma: Y[04]
DD_VIN
• YCC 8-bit (which allows for two simultaneous decoder inputs), it is time multiplexed between luma and chroma of the upper channel. Y/CB/CR[04]
GIO: GIO[090] Standard CCD/CMOS input: Raw[03]
• YCC 16-bit: Time multiplexed between chroma: Y[03]
DD_VIN
• YCC 8-bit (which allows for two simultaneous decoder inputs), it is time multiplexed between luma and chroma of the upper channel. Y/CB/CR[03]
GIO: GIO[089] Standard CCD/CMOS input: Raw[02]
• YCC 16-bit: Time multiplexed between chroma: Y[02]
DD_VIN
• YCC 8-bit (which allows for two simultaneous decoder inputs), it is time multiplexed between luma and chroma of the upper channel. Y/CB/CR[02]
GIO: GIO[088] Standard CCD/CMOS input: Raw[01]
• YCC 16-bit: Time multiplexed between chroma: Y[01]
DD_VIN
• YCC 8-bit (which allows for two simultaneous decoder inputs), it is time multiplexed between luma and chroma of the upper channel. Y/CB/CR[01]
GIO: GIO[087] Standard CCD/CMOS input: Raw[00]
• YCC 16-bit: Time multiplexed between chroma: Y[00]
DD_VIN
• YCC 8-bit (which allows for two simultaneous decoder inputs), it is time multiplexed between luma and chroma of the upper channel. Y/CB/CR[00]
GIO: GIO[086] Horizontal synchronization signal that can be either an input (slave mode) or an
DD_VIN
GIO: GIO[085] Vertical synchronization signal that can be either an input (slave mode) or an output
DD_VIN
GIO: GIO[084] Write enable input signal is used by external device (AFE/TG) to gate the DDR
output of the CCDC module. Alternately, the field identification input signal is used
PD by external device (AFE/TG) to indicate which of two frames is input to the CCDC
V
DD_VIN
module for sensors with interlaced output. CCDC handles 1- or 2-field sensors in hardware. GIO: GIO[083]
DD_VIN
GIO: GIO[0082]
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2.5 Image Data Output - Video Processing Back End (VPBE)

The Video Encoder/Digital LCD interface module in the video processing back end has an external signal interface for digital image data output as described in Table 2-7 and Table 2-8.
The digital image data output signals support multiple functions / interfaces, depending on the display mode selected. The following table describes these modes. Parallel RGB mode with more than RGB565 signals requires enabling pin multiplexing to support (i.e., for RGB666 mode).
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Table 2-6. Signals for VPBE Display Modes
PIN NAME YCC16 YCC8/ PRGB SRGB
HSYNC HSYNC HSYNC HSYNC HSYNC GIO073
VSYNC VSYNC VSYNC VSYNC VSYNC GIO072
LCD_OE As needed As needed As needed As needed
GIO071
FIELD As needed As needed As needed As needed
GIO070
R2
PWM3C EXTCLK As needed As needed As needed As needed
GIO069
B2
PWM3D
VCLK VCLK VCLK VCLK VCLK
GIO068
YOUT7 Y7 Y7,Cb7,Cr7 R7 Data7 YOUT6 Y6 Y6,Cb6,Cr6 R6 Data6 YOUT5 Y5 Y5,Cb5,Cr5 R5 Data5 YOUT4 Y4 Y4,Cb4,Cr4 R4 Data4 YOUT3 Y3 Y3,Cb3,Cr3 R3 Data3 YOUT2 Y2 Y2,Cb2,Cr2 G7 Data2 YOUT1 Y1 Y1,Cb1,Cr1 G6 Data1 YOUT0 Y0 Y0,Cb0,Cr0 G5 Data0
COUT7 C7 LCD_AC G4 LCD_AC GIO081
PWM0
COUT6 C6 LCD_OE G3 LCD_OE GIO080
PWM1
COUT5 C5 BRIGHT G2 BRIGHT GIO079
PWM2A
RTO0
COUT4 C4 PWM B7 PWM GIO078
PWM2B
RTO1
COUT3 C3 CSYNC B6 CSYNC GIO077
PWM2C
RTO2
COUT2 C2 - B5 ­GIO076
PWM2D
RTO3
COUT1 C1 - B4 ­GIO075
PWM3A
COUT0 C0 - B3 ­GIO074
PWM3B
REC656
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Table 2-7. Digital Video Terminal Functions
TERMINAL
NAME NO.
YOUT7-R7 C3 I/O/Z V YOUT6-R6 A4 I/O/Z V YOUT5-R5 B4 I/O/Z V YOUT4-R4 B3 I/O/Z V YOUT3-R3 B2 I/O/Z V YOUT2-G7 A3 I/O/Z V YOUT1-G6 A2 I/O/Z V YOUT0-G5 B1 I/O/Z V COUT7-
G4/GIO081 C2 I/O/Z V /PWM0
COUT6-G3 /GIO080 D2 I/O/Z V /PWM1
COUT5-G2 / GIO079 / PWM2A /
C1 I/O/Z V RTO0 COUT4-B7 /
GIO078 / PWM2B /
D3 I/O/Z V RTO1 COUT3-B6 /
GIO077 / PWM2C /
E3 I/O/Z V RTO2 COUT2-B5 /
GIO076 / PWM2D /
E4 I/O/Z V RTO3 COUT1-B4 / Digital Video Out: VENC settings determine function
GIO075 / F3 I/O/Z V PWM3A PWM3A
COUT0-B3 / Digital Video Out: VENC settings determine function GIO074 / F4 I/O/Z V PWM3B PWM3B
HSYNC / PD Video Encoder: Horizontal Sync GIO073 V
VSYNC / PD Video Encoder: Vertical Sync GIO072 V
F5 I/O/Z
G5 I/O/Z FIELD / Video Encoder: Field identifier for interlaced display formats
GIO070 / GIO: GIO[070] R2 / Digital Video Out: R2
H4 I/O/Z V PWM3C PWM3C
EXTCLK / GIO069 / PD B2 / V
G3 I/O/Z GIO: GIO[069] PWM3D
VCLK / Video Encoder: Video Output Clock GIO068 GIO: GIO[068]
H3 I/O/Z V
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal. (2) Specifies the operating I/O supply voltage for each signal. See Section 5.3 , Power Supplies for more detail. (3) PD = pull-down, PU = pull-up. (To pull up a signal to the opposite supply rail, a 1 kΩ resistor should be used.) (4) To reduce EMI and reflections, depending on the trace length, approximately 22 Ω to 50 Ω damping resistors are recommend on the
following outputs placed near the DM335: YOUT(0-7),COUT(0-7), HSYNC,VSYNC,LCD_OE,FIELD,EXTCLK,VCLK. The trace lengths should be minimized.
TYPE
(1)
OTHER
DD_VOUT DD_VOUT DD_VOUT DD_VOUT DD_VOUT DD_VOUT DD_VOUT DD_VOUT
DD_VOUT
DD_VOUT
DD_VOUT
DD_VOUT
DD_VOUT
DD_VOUT
DD_VOUT
DD_VOUT
DD_VOUT
DD_VOUT
DD_VOUT
(2) (3)
DESCRIPTION
(4)
Digital Video Out: VENC settings determine function Digital Video Out: VENC settings determine function Digital Video Out: VENC settings determine function Digital Video Out: VENC settings determine function Digital Video Out: VENC settings determine function Digital Video Out: VENC settings determine function Digital Video Out: VENC settings determine function Digital Video Out: VENC settings determine function
Digital Video Out: VENC settings determine function GIO: GIO[081] PWM0
Digital Video Out: VENC settings determine function GIO: GIO[080] PWM1
Digital Video Out: VENC settings determine function GIO: GIO[079] PWM2A RTO0
Digital Video Out: VENC settings determine function GIO: GIO[078] PWM2B RTO1
Digital Video Out: VENC settings determine function GIO: GIO[077] PWM2C RTO2
Digital Video Out: VENC settings determine function GIO: GIO[076] PWM2D RTO3
GIO: GIO[075]
GIO: GIO[074]
GIO: GIO[073]
GIO: GIO[072]
Video Encoder: External clock input, used if clock rates > 27 MHz are needed, e.g.
74.25 MHz for HDTV digital output
DD_VOUT
Digital Video Out: B2 PWM3D
DD_VOUT
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Table 2-8. Analog Video Terminal Functions
TERMINAL
NAME NO.
VREF J7 A I/O/Z
IOUT E1 A I/O/Z
IBIAS F2 A I/O/Z configuration. When the DAC is not used, the IBIAS signal should be connected to
VFB G1 A I/O/Z
TVOUT F1 A I/O/Z V circuit connection). When the DAC is not used, the TVOUT signal should be left as a
V
DDA18_DAC
V
SSA_DAC
L7 PWR
L8 GND
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal. Specifies the operating I/O supply
voltage for each signal. See Section 5.3 , Power Supplies for more detail.
(2) PD = pull-down, PU = pull-up. (To pull up a signal to the opposite supply rail, a 1 kΩ resistor should be used.)
TYPE
(1)
OTHER
(2)
DESCRIPTION
Video DAC: Reference voltage output (0.45V, 0.1uF to GND). When the DAC is not used, the VREF signal should be connected to VSS.
Video DAC: Pre video buffer DAC output (1000 ohm to VFB). When the DAC is not used, the IOUT signal should be connected to VSS.
Video DAC: External resistor (2550 Ohms to GND) connection for current bias VSS.
Video DAC: Pre video buffer DAC output (1000 Ohms to IOUT, 1070 Ohms to TVOUT). When the DAC is not used, the VFB signal should be connected to VSS.
Video DAC: Analog Composite NTSC/PAL output (SeeFigure 5-31 andFigure 5-32 for No Connect or connected to VSS.
Video DAC: Analog 1.8V power. When the DAC is not used, the V should be connected to VSS.
Video DAC: Analog 1.8V ground. When the DAC is not used, the V should be connected to VSS.
DDA18_DAC
SSA_DAC
signal
signal

2.6 Asynchronous External Memory Interface (AEMIF)

The Asynchronous External Memory Interface (AEMIF) signals support AEMIF, NAND, and OneNAND.
Table 2-9. Asynchronous EMIF/NAND/OneNAND Terminal Functions
TERMINAL
NAME NO.
EM_A13/ Async EMIF: Address bus bit[13] GIO067/ V19 I/O/Z GIO: GIO[67] BTSEL[1] System: BTSEL[1:0] sampled at power-on-reset to determine boot method.
EM_A12/ Async EMIF: Address bus bit[12] GIO066/ U19 I/O/Z GIO: GIO[66] BTSEL[0] System: BTSEL[1:0] sampled at power-on-reset to determine boot method.
EM_A11/ GIO065/ R16 I/O/Z AECFG[3]
EM_A10/ GIO: GIO[64] GIO064/ R18 I/O/Z AECFG[3:0] sampled at power-on-reset to AECFG configuration. AECFG[2:1] AECFG[2] sets default for PinMux2_EM_BA0: AEMIF EM_BA0 definition (EM_BA0,
EM_A09/ GIO: GIO[63] GIO063/ P17 I/O/Z AECFG[3:0] sampled at power-on-reset to AECFG configuration. AECFG[2:1] AECFG[1] sets default for PinMux2_EM_BA0: AEMIF EM_BA0 definition (EM_BA0,
EM_A08/ GIO062/ T19 I/O/Z AECFG[0] • PinMux2_EM_A0_BA1: AEMIF address width (OneNAND or NAND)
EM_A07/ GIO061
P16 I/O/Z V
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal. (2) Specifies the operating I/O supply voltage for each signal. See Section 5.3 , Power Supplies for more detail. (3) PD = pull-down, PU = pull-up. (To pull up a signal to the opposite supply rail, a 1 kΩ resistor should be used.)
TYPE
(1)
OTHER
(2) (3)
DESCRIPTION
PD
V
DD
PD
V
DD
Async EMIF: Address bus bit[11]
PU GIO: GIO[65]
V
DD
AECFG[3:0] sampled at power-on-reset to AECFG configuration. AECFG[3] sets default for PinMux2_EM_D15_8: AEMIF default bus width (16 or 8 bits)
Async EMIF: Address bus bit[10]
PU
V
DD
EM_A14, GIO[054], rsvd) Async EMIF: Address bus bit[09]
PD
V
DD
EM_A14, GIO[054], rsvd) Async EMIF: Address bus bit[08]
GIO: GIO[62] AECFG[0] sets default for:
V
PD
DD
• PinMux2_EM_A13_3: AEMIF address width (OneNAND or NAND) Async EMIF: Address bus bit[07]
DD
GIO: GIO[61] Used to drive boot status LED signal (active low) in ROM boot modes.
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Table 2-9. Asynchronous EMIF/NAND/OneNAND Terminal Functions (continued)
TERMINAL
NAME NO.
EM_A06/ Async EMIF: Address bus bit[06] GIO060 GIO: GIO[60]
EM_A05/ Async EMIF: Address bus bit[05] GIO059 GIO: GIO[59]
EM_A04/ Async EMIF: Address bus bit[04] GIO058 GIO: GIO[58]
EM_A03/ Async EMIF: Address bus bit[03] GIO057 GIO: GIO[57]
P18 I/O/Z V
R19 I/O/Z V
P15 I/O/Z V
N18 I/O/Z V
EM_A02/ N15 I/O/Z V
EM_A01/ N17 I/O/Z V EM_A00/ Async EMIF: Address bus bit[00]
GIO056 GIO: GIO[56]
EM_BA1/ • In 16-bit mode, lowest address bit. GIO055
M16 I/O/Z V
P19 I/O/Z V
EM_BA0/ GIO054 N19 I/O/Z V EM_A14
EM_D15/ Async EMIF: Data bus bit 15 GIO053 GIO: GIO[053]
EM_D14/ Async EMIF: Data bus bit 14 GIO052 GIO: GIO[052]
EM_D13/ Async EMIF: Data bus bit 13 GIO051 GIO: GIO[051]
EM_D12/ Async EMIF: Data bus bit 12 GIO050 GIO: GIO[050]
EM_D11/ Async EMIF: Data bus bit 11 GIO049 GIO: GIO[049]
EM_D10/ Async EMIF: Data bus bit 10 GIO048 GIO: GIO[048]
EM_D09/ Async EMIF: Data bus bit 09 GIO047 GIO: GIO[047]
EM_D08/ Async EMIF: Data bus bit 08 GIO046 GIO: GIO[046]
EM_D07/ Async EMIF: Data bus bit 07 GIO045 GIO: GIO[045]
EM_D06/ Async EMIF: Data bus bit 06 GIO044 GIO: GIO[044]
EM_D05/ Async EMIF: Data bus bit 05 GIO043 GIO: GIO[043]
EM_D04/ Async EMIF: Data bus bit 04 GIO042 GIO: GIO[042]
EM_D03/ Async EMIF: Data bus bit 03 GIO041 GIO: GIO[041]
EM_D02/ Async EMIF: Data bus bit 02 GIO040 GIO: GIO[040]
EM_D01/ Async EMIF: Data bus bit 01 GIO039 GIO: GIO[039]
EM_D00/ Async EMIF: Data bus bit 00 GIO038 GIO: GIO[038]
M18 I/O/Z V
M19 I/O/Z V
M15 I/O/Z V
L18 I/O/Z V
L17 I/O/Z V
L19 I/O/Z V
K18 I/O/Z V
L16 I/O/Z V
K19 I/O/Z V
K17 I/O/Z V
J19 I/O/Z V
L15 I/O/Z V
J18 I/O/Z V
H19 I/O/Z V
J17 I/O/Z V
H18 I/O/Z V
TYPE
(1)
OTHER
DD
DD
DD
DD
DD
DD
DD
(2) (3)
DESCRIPTION
Async EMIF: Address bus bit[02] NAND/SM/xD: CLE - Command latch enable output
Async EMIF: Address bus bit[01] NAND/SM/xD: ALE - Address latch enable output
Async EMIF: Bank address 1 signal - 16-bit address:
DD
• In 8-bit mode, second lowest address bit. GIO: GIO[055]
Async EMIF: Bank address 0 signal - 8-bit address:
DD
• In 8-bit mode, lowest address bit. or can be used as an extra address line (bit14) when using 16-bit memories.
GIO: GIO[054]
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
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SPRS528C–JULY 2008–REVISED JUNE 2010
Table 2-9. Asynchronous EMIF/NAND/OneNAND Terminal Functions (continued)
TERMINAL
NAME NO.
EM_CE0/ standard asynchronous memories (example: flash), OneNAND, or NAND GIO037 memory. Used for the default boot and ROM boot modes.
EM_CE1/ GIO036
EM_WE/ GIO035
EM_OE/ GIO034
EM_WAIT/ GIO033
EM_ADV/ OneNAND: Address valid detect for OneNAND interface GIO032 GIO: GIO[032]
EM_CLK/ OneNAND: Clock for OneNAND flash interface GIO031 GIO: GIO[031]
J16 I/O/Z V
G19 I/O/Z V
J15 I/O/Z V
F19 I/O/Z V
G18 I/O/Z V
H16 I/O/Z V
E19 I/O/Z V
TYPE
(1)
OTHER
(2) (3)
DESCRIPTION
Async EMIF: Lowest numbered chip select. Can be programmed to be used for
DD
GIO: GIO[037] Async EMIF: Second chip select. Can be programmed to be used for standard
DD
asynchronous memories(example: flash), OneNAND, or NAND memory. GIO: GIO[036]
Async EMIF: Write Enable
DD
NAND/SM/xD: WE (Write Enable) output GIO: GIO[035]
Async EMIF: Output Enable
DD
NAND/SM/xD: RE (Read Enable) output GIO: GIO[034]
Async EMIF: Async WAIT
DD
DD
DD
NAND/SM/xD: RDY/ BSY input GIO: GIO[033]

2.7 DDR Memory Interface

The DDR EMIF supports DDR2 and mobile DDR.
Table 2-10. DDR Terminal Functions
TERMINAL
NAME NO.
DDR_CLK W9 I/O/Z V DDR_CLK W8 I/O/Z V DDR_RAS T6 I/O/Z V DDR_CAS V9 I/O/Z V DDR_WE W10 I/O/Z V DDR_CS T8 I/O/Z V DDR_CKE V10 I/O/Z V DDR_DQM[1] U15 I/O/Z V
DDR_DQM[0] T12 I/O/Z V DDR_DQS[1] V15 I/O/Z V
DDR_DQS[0] V12 I/O/Z V
DDR_BA[2] V8 I/O/Z V DDR_BA[1] U7 I/O/Z V DDR_BA[0] U8 I/O/Z V DDR_A13 U6 I/O/Z V DDR_A12 V7 I/O/Z V DDR_A11 W7 I/O/Z V DDR_A10 V6 I/O/Z V
TYPE
(1)
OTHER
DD_DDR DD_DDR DD_DDR DD_DDR DD_DDR DD_DDR DD_DDR DD_DDR
DD_DDR
DD_DDR
DD_DDR
DD_DDR DD_DDR DD_DDR DD_DDR DD_DDR DD_DDR DD_DDR
(2) (3)
DESCRIPTION
DDR Data Clock DDR Complementary Data Clock DDR Row Address Strobe DDR Column Address Strobe DDR Write Enable DDR Chip Select DDR Clock Enable Data mask outputs:
• DDR_DQM[1] - For DDR_DQ[15:8]
• DDR_DQM[0] - For DDR_DQ[7:0] Data strobe input/outputs for each byte of the 16-bit data bus used to
synchronize the data transfers. Output to DDR when writing and inputs when reading.
• DDR_DQS[1] - For DDR_DQ[15:8]
• DDR_DQS[0] - For DDR_DQ[7:0] Bank select outputs. Two are required for 1Gb DDR2 memories. Bank select outputs. Two are required for 1Gb DDR2 memories. Bank select outputs. Two are required for 1Gb DDR2 memories. DDR Address Bus bit 13 DDR Address Bus bit 12 DDR Address Bus bit 11 DDR Address Bus bit 10
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal. (2) Specifies the operating I/O supply voltage for each signal. See Section 5.3 , Power Supplies for more detail. (3) PD = pull-down, PU = pull-up. (To pull up a signal to the opposite supply rail, a 1 kΩ resistor should be used.)
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Table 2-10. DDR Terminal Functions (continued)
TERMINAL
NAME NO.
DDR_A09 W6 I/O/Z V DDR_A08 W5 I/O/Z V DDR_A07 V5 I/O/Z V DDR_A06 U5 I/O/Z V DDR_A05 W4 I/O/Z V DDR_A04 V4 I/O/Z V DDR_A03 W3 I/O/Z V DDR_A02 W2 I/O/Z V DDR_A01 V3 I/O/Z V DDR_A00 V2 I/O/Z V DDR_DQ15 W17 I/O/Z V DDR_DQ14 V16 I/O/Z V DDR_DQ13 W16 I/O/Z V DDR_DQ12 U16 I/O/Z V DDR_DQ11 W15 I/O/Z V DDR_DQ10 W14 I/O/Z V DDR_DQ09 V14 I/O/Z V DDR_DQ08 U13 I/O/Z V DDR_DQ07 W13 I/O/Z V DDR_DQ06 V13 I/O/Z V DDR_DQ05 W12 I/O/Z V DDR_DQ04 U12 I/O/Z V DDR_DQ03 T11 I/O/Z V DDR_DQ02 U11 I/O/Z V DDR_DQ01 W11 I/O/Z V DDR_DQ00 V11 I/O/Z V DDR_ DDR: Loopback signal for external DQS gating. Route to DDR and back to
DQGATE0 DDR_DQGATE1 with same constraints as used for DDR clock and data. DDR_ DDR: Loopback signal for external DQS gating. Route to DDR and back to
DQGATE1 DDR_DQGATE0 with same constraints as used for DDR clock and data.
W18 I/O/Z V
V17 I/O/Z V
DDR_VREF U10 I/O/Z V V
SSA_DLL
V
DDA33_DDRDL
L
R11 I/O/Z V R10 I/O/Z V
DDR_ZN T9 I/O/Z V
TYPE
(1)
OTHER
DD_DDR DD_DDR DD_DDR DD_DDR DD_DDR DD_DDR DD_DDR DD_DDR DD_DDR DD_DDR DD_DDR DD_DDR DD_DDR DD_DDR DD_DDR DD_DDR DD_DDR DD_DDR DD_DDR DD_DDR DD_DDR DD_DDR DD_DDR DD_DDR DD_DDR DD_DDR
DD_DDR
DD_DDR
DD_DDR
DD_DDR
DD_DDR
DD_DDR
(2) (3)
DESCRIPTION
DDR Address Bus bit 09 DDR Address Bus bit 08 DDR Address Bus bit 07 DDR Address Bus bit 06 DDR Address Bus bit 05 DDR Address Bus bit 04 DDR Address Bus bit 03 DDR Address Bus bit 02 DDR Address Bus bit 01 DDR Address Bus bit 00 DDR Data Bus bit 15 DDR Data Bus bit 14 DDR Data Bus bit 13 DDR Data Bus bit 12 DDR Data Bus bit 11 DDR Data Bus bit 10 DDR Data Bus bit 09 DDR Data Bus bit 08 DDR Data Bus bit 07 DDR Data Bus bit 06 DDR Data Bus bit 05 DDR Data Bus bit 04 DDR Data Bus bit 03 DDR Data Bus bit 02 DDR Data Bus bit 01 DDR Data Bus bit 00
DDR: Voltage input for the SSTL_18 I/O buffers. Note even in the case of mDDR an external resistor divider connected to this pin is necessary.
DDR: Ground for the DDR DLL DDR: Power (3.3 V) for the DDR DLL DDR: Reference output for drive strength calibration of N and P channel
outputs. Tie to ground via 50 ohm resistor @ 0.5% tolerance.
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2.8 GPIO

The General Purpose I/O signals provide generic I/O to external devices. Most of the GIO signals are multiplexed with other functions.
Table 2-11. GPIO Terminal Functions
TERMINAL
NAME NO.
GIO000 C16 I/O/Z V
GIO001 E14 I/O/Z V GIO002 F15 I/O/Z V GIO003 G15 I/O/Z V GIO004 B17 I/O/Z V GIO005 D15 I/O/Z V GIO006 B18 I/O/Z V GIO007 /
SPI0_SDE C17 I/O/Z V NA[1]
SPI1_SD O / E12 I/O/Z V GIO008
SPI1_SDI / GIO009 / SPI1_SDE
A13 I/O/Z V NA[1] SPI1_SCL
K / C13 I/O/Z V GIO010
SPI1_SDE NA[0] / E13 I/O/Z V GIO011
UART1_T XD / R17 I/O/Z V GIO012
UART1_R XD / R15 I/O/Z V GIO013
I2C_SCL / I2C: Serial Clock GIO: GIO014 GIO[014]
I2C_SDA / I2C: Serial Data GIO015 GIO: GIO[015]
CLKOUT3 CLKOUT: Output Clock 3 / GIO016 GIO: GIO[016]
CLKOUT2 CLKOUT: Output Clock 2 / GIO017 GIO: GIO[017]
CLKOUT1 CLKOUT: Output Clock 1 / GIO018 GIO: GIO[018]
R14 I/O/Z V
R13 I/O/Z V
C11 I/O/Z V
A11 I/O/Z V
D12 I/O/Z V MMCSD1
_DATA0 / MMCSD1: DATA0 GIO019 / A18 I/O/Z V UART2_T UART2: Transmit Data XD
TYPE
(1)
OTHER
(2) (3)
DESCRIPTION
GIO:GIO[000] is sampled at reset and stored in the GIO0_RESET bit of the BOOTCFG register.
DD
Active low during MMC/SD boot (can be used as MMC/SD power control). Can be used as external clock input for Timer 3. Note: The GIO000 pin must be held high during NAND boot for the boot process to fuction properly.
DD DD DD DD DD DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
GIO: GIO[001] Can be used as external clock input for Timer 3. GIO: GIO[002] Can be used as external clock input for Timer 3. GIO: GIO[003] Can be used as external clock input for Timer 3. GIO: GIO[004] GIO: GIO[005] GIO: GIO[006]
GIO: GIO[007] SPI0: Chip Select 1
SPI1: Data Out GIO: GIO[008]
SPI1: Data In -OR- SPI1: Chip Select 1 GIO: GIO[009]
SPI1: Clock GIO: GIO[010]
SPI1: Chip Select 0 GIO: GIO[011]
UART1: Transmit Data GIO: GIO[012]
UART1: Receive Data GIO: GIO[013]
GIO: GIO[019]
SPRS528C–JULY 2008–REVISED JUNE 2010
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal. (2) Specifies the operating I/O supply voltage for each signal. See Section 5.3 , Power Supplies for more detail. (3) PD = pull-down, PU = pull-up. (To pull up a signal to the opposite supply rail, a 1 kΩ resistor should be used.)
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Table 2-11. GPIO Terminal Functions (continued)
TERMINAL
NAME NO.
MMCSD1 _DATA1 / MMCSD1: DATA1 GIO020 / B15 I/O/Z V UART2_R UART2: Receive Data XD
MMCSD1 _DATA2 / MMCSD1: DATA2 GIO021 / A16 I/O/Z V UART2_C UART2: CTS TS
MMCSD1 _DATA3 / MMCSD1: DATA3 GIO022 / B16 I/O/Z V UART2_R UART2: RTS TS
MMCSD1 _CMD / A17 I/O/Z V GIO023
MMCSD1 _CLK / C15 I/O/Z V GIO024
ASP0_FS R / F16 I/O/Z V GIO025
ASP0_CL KR / F17 I/O/Z V GIO026
ASP0_DR ASP0: Receive Data / GIO027 GIO: GIO[027]
E18 I/O/Z V ASP0_FS
X / G17 I/O/Z V GIO028
ASP0_CL KX / F18 I/O/Z V GIO029
ASP0_DX ASP0: Transmit Data / GIO030 GIO: GIO[030]
EM_CLK / GIO031
EM_ADV / PD OneNAND: Address Valid Detect for OneNAND interface GIO032 V
EM_WAIT PU Async EMIF: Async WAIT NAND/SM/xD: RDY/_BSY input / GIO033 V
EM_OE / GIO034
EM_WE / GIO035
EM_CE1 / GIO036
EM_CE0 / standard asynchronous memories (example: flash), OneNand or NAND memory. GIO037 Used for the default boot and ROM boot modes.
EM_D00 / Async EMIF: Data Bus bit[00] GIO038 GIO: GIO[038]
H15 I/O/Z V
E19 I/O/Z V
H16 I/O/Z
G18 I/O/Z
F19 I/O/Z V
J15 I/O/Z V
G19 I/O/Z V
J16 I/O/Z V
H18 I/O/Z V
TYPE
(1)
OTHER
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
(2) (3)
DESCRIPTION
GIO: GIO[020]
GIO: GIO[021]
GIO: GIO[022]
MMCSD1: Command GIO: GIO[023]
MMCSD1: Clock GIO: GIO[024]
ASP0: Receive Frame Synch GIO: GIO[025]
ASP0: Receive Clock GIO: GIO[026]
ASP0: Transmit Frame Synch GIO: GIO[028]
ASP0: Transmit Clock GIO: GIO[029]
OneNAND: Clock signal for OneNAND flash interface GIO: GIO[031]
GIO: GIO[032]
GIO: GIO[033] Async EMIF: Output Enable
DD
NAND/SM/xD: RE (Read Enable) output GIO: GIO[034]
Async EMIF: Write Enable
DD
NAND/SM/xD: WE (Write Enable) output GIO: GIO[035]
Async EMIF: Second Chip Select., Can be programmed to be used for standard
DD
asynchronous memories (example: flash), OneNand or NAND memory. GIO: GIO[036]
Async EMIF: Lowest numbered Chip Select. Can be programmed to be used for
DD
GIO: GIO[037]
DD
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Table 2-11. GPIO Terminal Functions (continued)
TERMINAL
NAME NO.
EM_D01 / Async EMIF: Data Bus bit[01] GIO039 GIO: GIO[039]
EM_D02 / Async EMIF: Data Bus bit[02] GIO040 GIO: GIO[040]
EM_D03 / Async EMIF: Data Bus bit[03] GIO041 GIO: GIO[041]
EM_D04 / Async EMIF: Data Bus bit[04] GIO042 GIO: GIO[042]
EM_D05 / Async EMIF: Data Bus bit[05] GIO043 GIO: GIO[043]
EM_D06 / Async EMIF: Data Bus bit[06] GIO044 GIO: GIO[044]
EM_D07 / Async EMIF: Data Bus bit[07] GIO045 GIO: GIO[045]
EM_D08 / Async EMIF: Data Bus bit[08] GIO046 GIO: GIO[046]
EM_D09 / Async EMIF: Data Bus bit[09] GIO047 GIO: GIO[047]
EM_D10 / Async EMIF: Data Bus bit[10] GIO048 GIO: GIO[048]
EM_D11 / Async EMIF: Data Bus bit[11] GIO049 GIO: GIO[049]
EM_D12 / Async EMIF: Data Bus bit[12] GIO050 GIO: GIO[050]
EM_D13 / Async EMIF: Data Bus bit[13] GIO051 GIO: GIO[051]
EM_D14 / Async EMIF: Data Bus bit[14] GIO052 GIO: GIO[052]
EM_D15 / Async EMIF: Data Bus bit[15] GIO053 GIO: GIO[053]
J17 I/O/Z V
H19 I/O/Z V
J18 I/O/Z V
L15 I/O/Z V
J19 I/O/Z V
K17 I/O/Z V
K19 I/O/Z V
L16 I/O/Z V
K18 I/O/Z V
L19 I/O/Z V
L17 I/O/Z V
L18 I/O/Z V
M15 I/O/Z V
M19 I/O/Z V
M18 I/O/Z V
EM_BA0 / GIO054 / N19 I/O/Z V EM_A14
EM_BA1 / GIO055
EM_A00 / GIO056
EM_A03 / Async EMIF: Address Bus bit[03] GIO057 GIO: GIO[057]
EM_A04 / Async EMIF: Address Bus bit[04] GIO058 GIO: GIO[058]
EM_A05 / Async EMIF: Address Bus bit[05] GIO059 GIO: GIO[059]
EM_A06 / Async EMIF: Address Bus bit[06] GIO060 GIO: GIO[060]
EM_A07 / GIO061
P19 I/O/Z V
M16 I/O/Z V
N18 I/O/Z V
P15 I/O/Z V
R19 I/O/Z V
P18 I/O/Z V
P16 I/O/Z V
EM_A08 / GIO062 / T19 I/O/Z AECFG[0]
TYPE
(1)
OTHER
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
(2) (3)
DESCRIPTION
Async EMIF: Bank Address 0 signal = 8-bit address. In 8-bit mode, lowest
DD
address bit. Or, can be used as an extra Address line (bit[14] when using 16-bit memories. GIO: GIO[054]
Async EMIF: Bank Address 1 signal = 16-bit address. In 16-bit mode, lowest
DD
address bit. In 8-bit mode, second lowest address bit GIO: GIO[055]
Async EMIF: Address Bus bit[00] Note that the EM_A0 is always a 32-bit
DD
DD
DD
DD
DD
address GIO: GIO[056]
Async EMIF: Address Bus bit[07]
DD
GIO: GIO[061] - Used to drive Boot Status LED signal (active low) in ROM boot modes
Async EMIF: Address Bus bit[08]
PU GIO: GIO[062] AECFG[0] sets default for - PinMux2.EM_A0_BA1: AEMIF
V
DD
Address Width (OneNAND or NAND) - PinMux2.EM_A13_3: AEMIF Address Width (OneNAND or NAND)
SPRS528C–JULY 2008–REVISED JUNE 2010
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Table 2-11. GPIO Terminal Functions (continued)
TERMINAL
NAME NO.
EM_A09 / GIO063 / P17 I/O/Z AECFG[1]
EM_A10 / GIO064 / R18 I/O/Z AECFG[2]
EM_A11 / GIO065 / R16 I/O/Z AECFG[3]
EM_A12 / Async EMIF: Address Bus bit[12] GIO066 / U19 I/O/Z GIO: GIO[066] System: BTSEL[1:0] sampled at Power-on-Reset to determine BTSEL[0] Boot method
EM_A13 / Async EMIF: Address Bus bit[13] GIO067 / V19 I/O/Z GIO: GIO[067] System: BTSEL[1:0] sampled at Power-on-Reset to determine BTSEL[1] Boot method.
VCLK / Video Encoder: Video Output Clock GIO068 GIO: GIO[068]
H3 I/O/Z V
EXTCLK / GIO069 / PD B2 / V
G3 I/O/Z e.g. 74.25 MHz for HDTV digital output PWM3D FIELD /
GIO070 / Video Encoder: Field identifier for interlaced display formats R2 / GIO: GIO[070] Digital Video Out: R2 PWM3C
H4 I/O/Z V PWM3C VSYNC / PD Video Encoder: Vertical Sync
GIO072 V HSYNC / PD Video Encoder: Horizontal Sync
GIO073 V
G5 I/O/Z
F5 I/O/Z COUT0-
B3 / Digital Video Out: VENC settings determine function GIO: GIO[074] GIO074 / PWM3B
F4 I/O/Z V PWM3B COUT1-
B4 / Digital Video Out: VENC settings determine function GIO: GIO[075] GIO075 / PWM3A
F3 I/O/Z V PWM3A COUT2-
B5 / GIO076 / E4 I/O/Z V PWM2D / RTO3
COUT3­B6 / GIO077 / E3 I/O/Z V PWM2C / RTO2
COUT4­B7 / GIO078 / D3 I/O/Z V PWM2B / RTO1
COUT5­G2 / GIO079 / C1 I/O/Z V PWM2A / RTO0
TYPE
(1)
OTHER
(2) (3)
DESCRIPTION
Async EMIF: Address Bus bit[09]
PD GIO: GIO[063] System: AECFG[3:0] sampled at Power-on-Reset to set AEMIF
V
DD
Configuration AECFG[2:1] sets default for PinMux2.EM_BA0: AEMIF EM_BA0 Definition (EM_BA0, EM_A14, GIO[054], rsvd)
Async EMIF: Address Bus bit[10]
PU GIO: GIO[064] System: AECFG[3:0] sampled at Power-on-Reset to set AEMIF
V
DD
Configuration AECFG[2:1] sets default for PinMux2.EM_BA0: AEMIF EM_BA0 Definition (EM_BA0, EM_A14, GIO[054], rsvd)
Async EMIF: Address Bus bit[11]
PU GIO: GIO[065] System: AECFG[3:0] sampled at Power-on-Reset to set AEMIF
V
DD
Configuration AECFG[3] sets default for PinMux2.EM_D15_8: AEMIF Default Bus Width (16 or 8 bits)
PD
V
DD
PD
V
DD
DD_VOUT
Video Encoder: External clock input, used if clock rates > 27 MHz are needed,
DD_VOUT
DD_VOUT
DD_VOUT
DD_VOUT
DD_VOUT
DD_VOUT
DD_VOUT
DD_VOUT
DD_VOUT
DD_VOUT
GIO: GIO[069] Digital Video Out: B2 PWM3D
GIO: GIO[072]
GIO: GIO[073]
Digital Video Out: VENC settings determine function GIO: GIO[076] PWM2D RTO3
Digital Video Out: VENC settings determine function GIO: GIO[077] PWM2C RTO2
Digital Video Out: VENC settings determine function GIO: GIO[078] PWM2B RTO1
Digital Video Out: VENC settings determine function GIO: GIO[079] PWM2A RTO0
26 Device Overview Copyright © 2008–2010, Texas Instruments Incorporated
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SPRS528C–JULY 2008–REVISED JUNE 2010
Table 2-11. GPIO Terminal Functions (continued)
TERMINAL
NAME NO.
COUT6­G3 / Digital Video Out: VENC settings determine function GIO: GIO[080] GIO080 / PWM1
D2 I/O/Z V PWM1 COUT7-
G4 / Digital Video Out: VENC settings determine function GIO: GIO[081] GIO081 / PWM0
C2 I/O/Z V PWM0 PCLK / PD
GIO082 V
T3 I/O/Z Pixel clock input (strobe for lines CI7 through YI0) GIO: GIO[082]
CAM_WE output of the CCDC module. Alternately, the field identification input signal is N_FIELD / R5 I/O/Z used by external device (AFE/TG) to indicate the which of two frames is input to GIO083 the CCDC module for sensors with interlaced output. CCDC handles 1- or 2-field
CAM_VD / PD GIO084 V
CAM_HD / PD GIO085 V
YIN0 / PD Y[00] YCC 08-bit (which allows for 2 simultaneous decoder inputs), it is time GIO086 V
YIN1 / PD Y[01] YCC 08-bit (which allows for 2 simultaneous decoder inputs), it is time GIO087 V
YIN2 / PD Y[02] YCC 08-bit (which allows for 2 simultaneous decoder inputs), it is time GIO088 V
YIN3 / PD Y[03] YCC 08-bit (which allows for 2 simultaneous decoder inputs), it is time GIO089 V
YIN4 / PD Y[04] YCC 08-bit (which allows for 2 simultaneous decoder inputs), it is time GIO090 V
YIN5 / PD Y[05] YCC 08-bit (which allows for 2 simultaneous decoder inputs), it is time GIO091 V
YIN6 / PD Y[06] YCC 08-bit (which allows for 2 simultaneous decoder inputs), it is time GIO092 V
YIN7 / PD Y[07] YCC 08-bit (which allows for 2 simultaneous decoder inputs), it is time GIO093 V
CIN0 / PD GIO094 V
R4 I/O/Z output (master mode). Tells the CCDC when a new frame starts.
N5 I/O/Z output (master mode). Tells the CCDC when a new line starts.
P5 I/O/Z
P2 I/O/Z
P4 I/O/Z
R3 I/O/Z
P3 I/O/Z
M5 I/O/Z
M4 I/O/Z
L5 I/O/Z
J3 I/O/Z inputs), it is time multiplexed between luma and chroma of the upper channel.
TYPE
(1)
OTHER
DD_VOUT
DD_VOUT
DD_VIN
(2) (3)
DESCRIPTION
Write enable input signal is used by external device (AFE/TG) to gate the DDR
PD
V
DD_VIN
sensors in hardware. GIO: GIO[083] Vertical synchronization signal that can be either an input (slave mode) or an
DD_VIN
GIO: GIO[084] Horizontal synchronization signal that can be either an input (slave mode) or an
DD_VIN
GIO: GIO[085] Standard CCD/CMOS input: raw[00] YCC 16-bit: time multiplexed between luma:
DD_VIN
multiplexed between luma and chroma of the lower channel. Y/CB/CR[00] GIO: GIO[086]
Standard CCD/CMOS input: raw[01] YCC 16-bit: time multiplexed between luma:
DD_VIN
multiplexed between luma and chroma of the lower channel. Y/CB/CR[01] GIO: GIO[087]
Standard CCD/CMOS input: raw[02] YCC 16-bit: time multiplexed between luma:
DD_VIN
multiplexed between luma and chroma of the lower channel. Y/CB/CR[02] GIO: GIO[088]
Standard CCD/CMOS input: raw[03] YCC 16-bit: time multiplexed between luma:
DD_VIN
multiplexed between luma and chroma of the lower channel. Y/CB/CR[03] GIO: GIO[089]
Standard CCD/CMOS input: raw[04] YCC 16-bit: time multiplexed between luma:
DD_VIN
multiplexed between luma and chroma of the lower channel. Y/CB/CR[04] GIO: GIO[090]
Standard CCD/CMOS input: raw[05] YCC 16-bit: time multiplexed between luma:
DD_VIN
multiplexed between luma and chroma of the lower channel. Y/CB/CR[05] GIO: GIO[091]
Standard CCD/CMOS input: raw[06] YCC 16-bit: time multiplexed between luma:
DD_VIN
multiplexed between luma and chroma of the lower channel. Y/CB/CR[06] GIO: GIO[092]
Standard CCD/CMOS input: raw[07] YCC 16-bit: time multiplexed between luma:
DD_VIN
multiplexed between luma and chroma of the lower channel. Y/CB/CR[07] GIO: GIO[093]
Standard CCD/CMOS input: raw[08] YCC 16-bit: time multiplexed between chroma: CB/CR[00] YCC 08-bit (which allows for 2 simultaneous decoder
DD_VIN
Y/CB/CR[00] GIO: GIO[094]
Copyright © 2008–2010, Texas Instruments Incorporated Device Overview 27
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SPRS528C–JULY 2008–REVISED JUNE 2010
Table 2-11. GPIO Terminal Functions (continued)
TERMINAL
NAME NO.
CIN1 / PD GIO095 V
CIN2 / PD GIO096 V
CIN3 / PD GIO097 V
L3 I/O/Z inputs), it is time multiplexed between luma and chroma of the upper channel.
J5 I/O/Z inputs), it is time multiplexed between luma and chroma of the upper channel.
J4 I/O/Z inputs), it is time multiplexed between luma and chroma of the upper channel.
CIN4 / GIO098 / SPI2_SDI PD / V
L4 I/O/Z inputs), it is time multiplexed between luma and chroma of the upper channel.
SPI2_SDE NA[1]
CIN5 / GIO099 / PD SPI2_SDE V
M3 I/O/Z inputs), it is time multiplexed between luma and chroma of the upper channel. NA[0]
CIN6 / GIO100 / PD SPI2_SD V
K5 I/O/Z inputs), it is time multiplexed between luma and chroma of the upper channel. O
CIN7 / GIO101 / PD SPI2_SCL V
N3 I/O/Z inputs), it is time multiplexed between luma and chroma of the upper channel. K
SPI0_SDI SPI0: Data In / GIO102 GIO: GIO[102]
A12 I/O/Z V
SPI0_SDE NA[0] / B12 I/O/Z V GIO103
TYPE
(1)
OTHER
(2) (3)
DESCRIPTION
Standard CCD/CMOS input: raw[09] YCC 16-bit: time multiplexed between chroma: CB/CR[01] YCC 08-bit (which allows for 2 simultaneous decoder
DD_VIN
Y/CB/CR[01] GIO: GIO[095]
Standard CCD/CMOS input: raw[10] YCC 16-bit: time multiplexed between chroma: CB/CR[02] YCC 08-bit (which allows for 2 simultaneous decoder
DD_VIN
Y/CB/CR[02] GIO: GIO[096]
Standard CCD/CMOS input: raw[11] YCC 16-bit: time multiplexed between chroma: CB/CR[03] YCC 08-bit (which allows for 2 simultaneous decoder
DD_VIN
Y/CB/CR[03] GIO: GIO[097]
Standard CCD/CMOS input: raw[12] YCC 16-bit: time multiplexed between chroma: CB/CR[04] YCC 08-bit (which allows for 2 simultaneous decoder
DD_VIN
Y/CB/CR[04] SPI: SPI2 Data In -OR- SPI2 Chip select 1. GIO: GIO[098]
Standard CCD/CMOS input: raw[13] YCC 16-bit: time multiplexed between chroma: CB/CR[05] YCC 08-bit (which allows for 2 simultaneous decoder
DD_VIN
Y/CB/CR[05] SPI: SPI2 Chip Select 0. GIO: GIO[99]
Standard CCD/CMOS input: NOT USED YCC 16-bit: time multiplexed between chroma: CB/CR[06] YCC 08-bit (which allows for 2 simultaneous decoder
DD_VIN
Y/CB/CR[06] SPI: SPI2 Data Out GIO: GIO[100]
Standard CCD/CMOS input: NOT USED YCC 16-bit: time multiplexed between chroma: CB/CR[07] YCC 08-bit (which allows for 2 simultaneous decoder
DD_VIN
Y/CB/CR[07] SPI: SPI2 Clock GIO: GIO[101]
DD
DD
SPI0: Chip Select 0 GIO: GIO[103]
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2.9 Multi-Media Card/Secure Digital (MMC/SD) Interfaces

The DM335 includes two Multi-Media Card/Secure Digital card interfaces that are compatible with the MMC/SD and SDIO protocol.
Table 2-12. MMC/SD Terminal Functions
TERMINAL
NAME NO.
MMCSD0_ CLK
MMCSD0_ CMD
MMCSD0_ DATA0
A15 I/O/Z V
C14 I/O/Z V
B14 I/O/Z V
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal. (2) Specifies the operating I/O supply voltage for each signal. See Section 5.3 , Power Supplies for more detail. (3) PD = pull-down, PU = pull-up. (To pull up a signal to the opposite supply rail, a 1 kΩ resistor should be used.)
28 Device Overview Copyright © 2008–2010, Texas Instruments Incorporated
TYPE
(1)
OTHER
DD
DD
DD
(2) (3)
DESCRIPTION
MMCSD0: Clock
MMCSD0: Command
MMCSD0: DATA0
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Table 2-12. MMC/SD Terminal Functions (continued)
TERMINAL
NAME NO.
MMCSD0_ DATA1
MMCSD0_ DATA2
MMCSD0_ DATA3
D14 I/O/Z V
B13 I/O/Z V
A14 I/O/Z V
MMCSD1_ CLK/ C15 I/O/Z V GIO024
MMCSD1_ CMD/ A17 I/O/Z V GIO023
MMCSD1_ DATA0/ MMCSD1: DATA0 GIO019/ A18 I/O/Z V UART2_T UART2: Transmit data XD
MMCSD1_ DATA1/ MMCSD1: DATA1 GIO020/ B15 I/O/Z V UART2_R UART2: Receive data XD
MMCSD1_ DATA2/ MMCSD1: DATA2 GIO021/ A16 I/O/Z V UART2_C UART2: CTS TS
MMCSD1_ DATA3/ MMCSD1: DATA3 GIO022/ B16 I/O/Z V UART2_R UART2: RTS TS
TYPE
(1)
OTHER
DD
DD
DD
DD
DD
DD
DD
DD
DD
(2) (3)
DESCRIPTION
MMCSD0: DATA1
MMCSD0: DATA2
MMCSD0: DATA3
MMCSD1: Clock GIO: GIO[024]
MMCSD1: Command GIO: GIO[023]
GIO: GIO[019]
GIO: GIO[020]
GIO: GIO[021]
GIO: GIO[022]
SPRS528C–JULY 2008–REVISED JUNE 2010

2.10 Universal Serial Bus (USB) Interface

The Universal Serial Bus (USB) interface supports the USB2.0 High-Speed protocol and includes dual-role Host/Slave support. However, no charge pump is included.
Table 2-13. USB Terminal Functions
TERMINAL
NAME NO.
USB_DP A7 A I/O/Z V
USB_DM A6 A I/O/Z V
USB_R1 C7 A I/O/Z
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal. (2) Specifies the operating I/O supply voltage for each signal. See Section 5.3 , Power Supplies for more detail. (3) PD = pull-down, PU = pull-up. (To pull up a signal to the opposite supply rail, a 1 kΩ resistor should be used.)
Copyright © 2008–2010, Texas Instruments Incorporated Device Overview 29
TYPE
(1)
OTHER
DDA33_USB
DDA33_USB
(2) (3)
DESCRIPTION
USB D+ (differential signal pair). When USB is not used, this signal should be connected to V
USB D- (differential signal pair). When USB is not used, this signal should be connected to V
USB reference current output Connect to V as possible.
SS_USB_REF
via 10K ohm , 1% resistor placed as close to the device
When USB is not used, this signal should be connected to V
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SS_USB
SS_USB
SS_USB
.
.
.
TMS320DM335
SPRS528C–JULY 2008–REVISED JUNE 2010
Table 2-13. USB Terminal Functions (continued)
TERMINAL
NAME NO.
USB_ID D5 A I/O/Z V
USB_VBUS E5 A I/O/Z V
USB_DRVVBUS C5 O/Z V
V
SS_USB_REF
V
DDA33_USB
V
DDA33_USB_PLL
V
DDA13_USB
V
DDD13_USB
C8 GND V
J8 PWR V
B6 PWR V
H7 PWR V
C6 PWR V
TYPE
(1)
OTHER
(2) (3)
DDA33_USB
DD
DD
DD
DD
DD
DD
DD
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DESCRIPTION
USB operating mode identification pin For Device mode operation only, pull up this pin to VDDwith a 1.5K ohm resistor. For Host mode operation only, pull down this pin to ground (VSS) with a 1.5K ohm resistor. If using an OTG or mini-USB connector, this pin will be set properly via the cable/connector configuration. When USB is not used, this signal should be connected to V
SS_USB
.
For host or device mode operation, tie the VBUS/USB power signal to the USB connector. When used in OTG mode operation, tie VBUS to the external charge pump and to the VBUS signal on the USB connector. When the USB is not used, tie VBUS to V
SS_USB
.
Digital output to control external 5 V supply When USB is not used, this signal should be left as a No Connect.
USB Ground Reference Connect directly to ground and to USB_R1 via 10K ohm, 1% resistor placed as close to the device as possible.
Analog 3.3 V power USBPHY When USB is not used, this signal should be connected to V
SS_USB
.
Common mode 3.3 V power for USB PHY (PLL) When USB is not used, this signal should be connected to V
SS_USB
.
Analog 1.3 V power for USB PHY When USB is not used, this signal should be connected to V
SS_USB
.
Digital 1.3 V power for USB PHY When USB is not used, this signal should be connected to V
SS_USB
.

2.11 Audio Interfaces

The DM335 includes two Audio Serial Ports (ASP ports), which are backward compatible with other TI ASP serial ports and provide I2S audio interface. One interface is multiplexed with GIO signals.
TERMINAL
NAME NO.
ASP0_CL KR/ F17 I/O/Z V GIO026
ASP0_CL KX / F18 I/O/Z V GIO029
ASP0_DR / E18 I/O/Z V GIO027
ASP0_DX / H15 I/O/Z V GIO030
ASP0_FS R / F16 I/O/Z V GIO025
ASP0_FS X / G17 I/O/Z V GIO028
ASP1_CL KR
D18 I/O/Z V
TYPE
(1)
OTHER
Table 2-14. ASP Terminal Functions
(2) (3)
DD
DD
DD
DD
DD
DD
DD
DESCRIPTION
ASP0: Receive Clock GIO: GIO[026]
ASP0: Transmit Clock GIO: GIO[029]
ASP0: Receive DataF GIO: GIO[027]
ASP0: Transmit Data GIO: GIO[030]
ASP0: Receive Frame Synch GIO: GIO[025]
ASP0: Transmit Frame SynchGIO: GIO[028]
ASP1: Receive Clock
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal. (2) Specifies the operating I/O supply voltage for each signal. See Section 5.3 , Power Supplies for more detail. (3) PD = pull-down, PU = pull-up. (To pull up a signal to the opposite supply rail, a 1 kΩ resistor should be used.)
30 Device Overview Copyright © 2008–2010, Texas Instruments Incorporated
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