TEXAS INSTRUMENTS TMP512, TMP513 Technical data
GND
GPIO
V
IN+
V
IN-
ALERT
SDA
SCL
ADC
TMP512
TMP513
DXP1
DXN1
DXP2
DXN2
Subregulator
3.3V
V+
Filter C
Two-Wire
Interface
Power Register
Current Register
Voltage Register
ADC
Low-Pass Filter
Internal
Diode
Temperature
Sensor
Mux
A0
DXP3
DXN3
TMP512
TMP513
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SBOS491 –JUNE 2010
Temperature and Power Supply System Monitors
Check for Samples: TMP512, TMP513
1
FEATURES
234
• ±1°C REMOTE DIODE SENSORS
• ±1°C LOCAL TEMPERATURE SENSOR
• SERIES RESISTANCE CANCELLATION
• n-FACTOR CORRECTION
• TEMPERATURE ALERT FUNCTION temperatures, on-chip temperatures, and system
• AVERAGING
• 12-BIT RESOLUTION
• DIODE FAULT DETECTION
• SENSES BUS VOLTAGES FROM 0V TO +26V
• REPORTS CURRENT IN AMPS, VOLTAGE IN Remote accuracy is ±1°C for multiple IC
VOLTS AND POWER IN WATTS
• HIGH ACCURACY: 1% MAX OVER TEMP
• WATCHDOG LIMITS:
– Upper Over-Limit
– Lower Under-Limit
APPLICATIONS
• DESKTOP AND NOTEBOOK COMPUTERS
• SERVERS
• INDUSTRIAL CONTROLLERS
• CENTRAL OFFICE TELECOM EQUIPMENT
• LCD/ DLP®/LCOS PROJECTORS
• STORAGE AREA NETWORKS (SAN)
DESCRIPTION
The TMP512 (dual-channel) and TMP513
(triple-channel) are system monitors that include
remote sensors, a local temperature sensor, and a
high-side current shunt monitor. These system
monitors have the capability of measuring remote
voltage/power/current consumption.
The remote temperature sensor diode-connected
transistors are typically low-cost, NPN- or PNP-type
transistors or diodes that are an integral part of
microcontrollers, microprocessors, or FPGAs.
manufacturers, with no calibration needed. The
two-wire serial interface accepts SMBus™ or
two-wire write and read commands.
The onboard current shunt monitor is a high-side
current shunt and power monitor. It monitors both the
shunt drop and supply voltage. A programmable
calibration value (along with the TMP512/TMP513
internal digital multiplier) enables direct readout in
amps; an additional multiplication calculates power in
watts. The TMP512 and TMP513 both feature two
separate onboard watchdog capabilities: an over-limit
comparator and a lower-limit comparator.
These devices use a single +3V to +26V supply,
drawing a maximum of 1.4mA of supply current, and
they are specified for operation from –40°C to
+125°C.
1
2DLP is a registered trademark of Texas Instruments.
3SMBus is a trademark of Intel Corporation.
4All other trademarks are the property of their respective owners.
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2010, Texas Instruments Incorporated
TMP512
TMP513
SBOS491 –JUNE 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE INFORMATION
(1)
PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR PACKAGE MARKING
TMP512 SO-14 D TMP512A
TMP513
SO-16 D TMP513A
(2)
QFN-16
RSA TMP513A
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
TMP512/TMP513 product folder at www.ti.com.
(2) Product preview device.
ABSOLUTE MAXIMUM RATINGS
(1)
Over operating free-air temperature range (unless otherwise noted).
TMP512, TMP513 UNIT
Supply Voltage, V+ 26 V
Filter C
Analog Inputs, V
IN+
, V
IN–
Open-Drain Digital Outputs GND – 0.3 to +6 V
GPIO, DXP, DXN GND – 0.3 to V+ + 0.3 V
Input Current Into Any Pin 5 mA
Open-Drain Digital Output Current 10 mA
Storage Temperature –65 to +150 °C
Junction Temperature +150 °C
ESD Ratings Charged-Device Model (CDM) 1000 V
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
(2) V
IN+
+26V.
and V
may have a differential voltage of –26V to +26V; however, the voltage at these pins must not exceed the range –0.3V to
IN–
Voltage GND – 0.3 to +6 V
Current 10 mA
Differential (V
IN+
) – (V
IN–
(2)
)
–26 to +26 V
Common-Mode –0.3 to +26 V
Human Body Model (HBM) 2000 V
Machine Model (MM) 150 V
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Product Folder Link(s): TMP512 TMP513
TMP512
TMP513
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SBOS491 –JUNE 2010
THERMAL INFORMATION
TMP512 TMP513AID
THERMAL METRIC
(1)
D (SOIC) D (SOIC) RSA
14 16 16
q
JA
q
JC(top)
q
JB
y
JT
y
JB
q
JC(bottom)
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
(2)
(3)
(4)
(5)
(6)
(7)
91.1 77.6 44.8
10.6 55.0 43.8
40.3 49.9 14.7
49.1 3.5 0.4
47.5 32.2 14.5
n/a n/a 2.6
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, yJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining qJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, yJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining qJA, using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
TMP513AIRSAR
TMP513AIRSAT
UNITS
°C/W
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TMP512
TMP513
SBOS491 –JUNE 2010
www.ti.com
ELECTRICAL CHARACTERISTICS: V+ = +12V
Boldface limits apply over the specified temperature range, TA= –40°C to +125°C.
At TA= +25°C, V+ = 12V, V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT
Current Sense (Input) Voltage Range PGA = ÷ 1 0 ±40 mV
Bus Voltage (Input Voltage) Range
Common-Mode Rejection CMRR V
Offset Voltage, RTI
vs Temperature 0.2 mV/°C
vs Power Supply PSRR
Current Sense Gain Error ±0.04 %
vs Temperature 0.0025 %
Input Impedance Active Mode
V
IN+
V
IN–
Input Leakage Power-Down Mode
V
IN+
V
IN–
DC ACCURACY
ADC Basic Resolution 12 Bits
1 LSB Step Size
Shunt Voltage 10 mV
Bus Voltage 4 mV
Current Measurement Error ±0.2 ±0.5 %
over Temperature ±1 %
Bus Voltage Measurement Error ±0.2 ±0.5 %
over Temperature ±1 %
Differential Nonlinearity ±0.1 LSB
ADC TIMING
ADC Conversion Time 12-Bit 665 733 ms
(1) BRNG is bit 13 of Configuration Register 1.
(2) This parameter only expresses the full-scale range of the ADC scaling. In no event should more than 26V be applied to this device.
(3) Referred-to-input (RTI).
(4) See Subregulator section.
(3)
Pin 20 mA
Pin 20 || 320 mA || kΩ
Pin 0.1 0.5 mA
Pin 0.1 0.5 mA
SENSE
(2)
= (V
IN+
– V
) = 32mV, PGA = ÷ 1, and BRNG
IN–
PGA = ÷ 2 0 ±80 mV
PGA = ÷ 4 0 ±160 mV
PGA = ÷ 8 0 ±320 mV
BRNG = 0 0 16 V
BRNG = 1 0 32 V
= 0V to 26V 100 120 dB
IN+
V
OS
V+ = 3V to 5.5V, Configuration 3
V+ = 4.5V to 26V, subregulator supply 0.1 mV/V
PGA = ÷ 1 ±10 ±100 mV
PGA = ÷ 2 ±20 ±125 mV
PGA = ÷ 4 ±30 ±150 mV
PGA = ÷ 8 ±40 ±200 mV
11-Bit 345 380 ms
10-Bit 185 204 ms
9-Bit 105 117 ms
(1)
= 1, unless otherwise noted.
TMP512, TMP513
(4)
10 mV/V
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Product Folder Link(s): TMP512 TMP513
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TMP513
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SBOS491 –JUNE 2010
ELECTRICAL CHARACTERISTICS: V+ = +12V (continued)
Boldface limits apply over the specified temperature range, TA= –40°C to +125°C.
At TA= +25°C, V+ = 12V, V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TEMPERATURE ERROR
Local Temperature Sensor TE
Remote Temperature Sensor
vs Supply, Local V+ = 3V to 5.5V, Configuration 3
vs Supply, Remote
TEMPERATURE MEASUREMENT
Conversion Time (per channel) 100 115 130 ms
Resolution
Local Temperature Sensor 13 Bits
Remote Temperature Sensor 13 Bits
Remote Sensor Source Currents Series Resistance 3kΩ max
High 120 mA
Medium High 60 mA
Medium Low 12 mA
Low 6 mA
Default Non-Ideality Factor n TMP512/12 Optimized Ideality Factor 1.008
SMBus
Logic Input High Voltage (SCL, SDA, GPIO,
A0)
Logic Input Low Voltage (SCL, SDA, GPIO,
A0)
Hysteresis 500 mV
SMBus Output Low Sink Current 6 mA
SDA Output Low Voltage V
Logic Input Current 0 ≤ VIN≤ 6V –1 1 mA
SMBus Input Capacitance (SCL, SDA, GPIO, A0) 3 pF
SMBus Clock Frequency 3.4 MHz
SMBus Timeout
SCL Falling Edge to SDA Valid Time 1 ms
POWER SUPPLY
Specified Supply Range
Quiescent Current 1 1.4 mA
Quiescent Current, Power-Down Mode 55 100 mA
Power-On Reset Threshold 2 V
TEMPERATURE RANGE
Specified Temperature Range –40 +125 °C
(7)
(5) Tested with one-shot measurements, and with less than 5Ω effective series resistance, and with 100pF differential input capacitance.
(6) See Subregulator section.
(7) SMBus timeout in the TMP512/13 resets the interface any time SCL or SDA is low for over 28ms.
(5)
(6)
SENSE
= (V
– V
IN+
) = 32mV, PGA = ÷ 1, and BRNG
IN–
LOCAL
TE
REMOTE
V
IH
V
IL
OL
V+ +3 +26 V
TA= –40°C to +125°C ±1.25 ±2.5 °C
TA= +15°C to +85°C, V+ = 12V ±0.25 ±1 °C
TA= +15°C to +85°C, TD= –40°C to+
TA= –40°C to +100°C, TD= –40°C to
TA= –40°C to +125°C, TD= –40°C to
V+ = 4.5V to 26V, subregulator supply 0.01 0.05 °C/V
150°C, V+ = 12V
+150°C, V+ = 12V
+150°C
V+ = 3V to 5.5V, Configuration 3
I
= 6mA 0.15 0.4 V
OUT
(1)
= 1, unless otherwise noted.
TMP512, TMP513
±0.25 ±1 °C
(6)
(6)
2.1 V
25 30 35 ms
±1 ±3 °C
±3 ±5 °C
0.2 0.5 °C/V
0.2 0.5 °C/V
0.8 V
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): TMP512 TMP513
1
2
3
4
5
6
7
V
IN-
SDA
SCL
A0
V
IN+
V+
Filter C
DXP2
DXN1
DXP1
GPIO
ALERT
GND
DXN2
14
13
12
11
10
9
8
TMP512
TMP512
TMP513
SBOS491 –JUNE 2010
PIN CONFIGURATIONS
TMP512
space
D PACKAGE
SO-14
(TOP VIEW)
TMP512: PIN DESCRIPTIONS
PIN NO. NAME DESCRIPTION
1 Filter C Subregulator output and filter capacitor pin.
2 V+ Positive supply voltage (3V to 26V) See Figure 20.
3 V
4 V
IN+
IN-
5 SDA Serial bus data line for SMBus, open-drain; requires pull-up resistor.
6 SCL Serial bus clock line for SMBus, open-drain; requires pull-up resistor.
7 A0 Address pin
8 DXP1 Channel 1 positive connection to remote temperature sensor.
9 DXN1 Channel 1 negative connection to remote temperature sensor.
10 DXP2 Channel 2 positive connection to remote temperature sensor.
11 DXN2 Channel 2 negative connection to remote temperature sensor.
12 GPIO
13 ALERT Open-drain SMBus alert output. Controlled in SMBus Alert Mask Register. Default state is disabled.
14 GND Ground
Positive differential shunt voltage. Connect to positive side of shunt resistor.
Negative differential shunt voltage. Connect to negative side of shunt resistor. Bus voltage is measured
from this pin to ground.
General-purpose, user-programmable input/output. Totem-pole output. Connect to ground or supply
through a resistor if not used. Default state is as an input.
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Product Folder Link(s): TMP512 TMP513
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Filter C
V+
V
IN+
V
IN-
SDA
SCL
A0
DXP1
GND
ALERT
GPIO
DXN3
DXP3
DXN2
DXP2
DXN1
TMP513
V
IN+
V
IN-
SDA
SCL
GPIO
DXN3
DXP3
DXN2
12
11
10
9
FilterC
1
2
3
4
5
6
7
8
13
14
15
16
A0
DXP1
DXN1
DXP2
ALERT
GND
V+
TMP513
TMP512
TMP513
www.ti.com
TMP513
space
D PACKAGE
SO-16
(TOP VIEW)
(1) Product preview device.
TMP513: PIN DESCRIPTIONS
D PACKAGE PACKAGE
SO-16 QFN-16 NAME DESCRIPTION
1 15 Filter C Subregulator output and filter capacitor pin.
2 16 V+ Positive supply voltage (3V to 26V) See Figure 20.
3 1 V
4 2 V
5 3 SDA Serial bus data line for SMBus, open-drain; requires pull-up resistor.
6 4 SCL Serial bus clock line for SMBus, open-drain; requires pull-up resistor.
7 5 A0 Address pin
8 6 DXP1 Channel 1 positive connection to remote temperature sensor.
9 7 DXN1 Channel 1 negative connection to remote temperature sensor.
10 8 DXP2 Channel 2 positive connection to remote temperature sensor.
11 9 DXN2 Channel 2 negative connection to remote temperature sensor.
12 10 DXP3 Channel 3 positive connection to remote temperature sensor.
13 11 DXN3 Channel 3 negative connection to remote temperature sensor.
14 12 GPIO
15 13 ALERT
16 14 GND Ground
RSA
IN+
IN-
Positive differential shunt voltage. Connect to positive side of shunt resistor.
Negative differential shunt voltage. Connect to negative side of shunt resistor. Bus voltage is
measured from this pin to ground.
General-purpose, user-programmable input/output. Totem-pole output. Connect to ground or
supply through a resistor if not used. Default state is as an input.
Open-drain SMBus alert output. Controlled in SMBus Alert Mask Register. Default state is
disabled.
RSA PACKAGE
SBOS491 –JUNE 2010
(1)
QFN-16
(TOP VIEW)
Product Folder Link(s): TMP512 TMP513
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 7
-40 -25 0 25 50
75
100 125
6
5
4
3
2
1
0
1
2
3
4
5
6
-
-
-
-
-
-
Remote Temperature Error ( C)?
Ambient Temperature ( C)?
34 Units Shown
10
100
1k
10k 100k
1M
Gain(dB)
InputFrequency(Hz)
0
10
20
30
40
50
60
70
80
90
100
-
-
-
-
-
-
-
-
-
-
-40
-25
0
25 50
75 100
Local Temperature Error ( C)°
Ambient Temperature ( C)°
125
14 Units Shown
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
-
-
-
-
-40
-25
0
25 50
75 100
Offset( V)m
Temperature( C)°
125
15
10
5
0
5
10
15
-
-
-
40mVRange
80mVRange
160mVRange
320mVRange
-40
-25
0
25 50
75 100
GainError(m%)
Temperature( C)°
125
250
200
150
100
50
0
50
100--
320mVRange
160mVRange
80mVRange
40mVRange
-40
-25
0
25 50
75 100
Offset (mV)
Temperature ( C)°
125
32V Range
16V Range
35
30
25
20
15
10
5
0
5
10
15
-
-
-
TMP512
TMP513
SBOS491 –JUNE 2010
At TA= +25°C, V+ = 12V, V
LOCAL TEMPERATURE ERROR vs TEMPERATURE SHUNT OFFSET vs TEMPERATURE
www.ti.com
TYPICAL CHARACTERISTICS: V+ = +12V
= (V
– V
SENSE
IN+
FREQUENCY RESPONSE REMOTE TEMPERATURE ERROR vs TEMPERATURE
Figure 1. Figure 2.
) = 32mV, PGA = ÷ 1, and BRNG = 1, unless otherwise noted.
IN–
8 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
Figure 3. Figure 4.
SHUNT GAIN ERROR vs TEMPERATURE BUS VOLTAGE OFFSET vs TEMPERATURE
Figure 5. Figure 6.
Product Folder Link(s): TMP512 TMP513
20
15
10
5
0
-5
-10
-15
-20
-0.4
-0.3
-0.2
-0.1 0
0.1 0.2 0.3
INL( V)m
InputVoltage(V)
0.4
-40
-25
0
25 50
75 100
Gain Error (m%)
Temperature ( C)°
125
250
200
150
100
50
0
50
100--
32V Range
16V Range
0
5
10
15 20
25
Input Currents (mA)
V Voltage (V)
IN-
30
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
-
-
-
V+ = 5.5V
V+ 5.5V=
V+ = 3V
V+ 3V=
Current into V
IN-
Current into V
IN+
-40
-25
0
25 50
75 100
I (mA)
Q
Temperature ( C)°
125
V+ = 5.5V
V+ = 12V
V+ = 3V
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
TMP512
TMP513
www.ti.com
At TA= +25°C, V+ = 12V, V
BUS GAIN ERROR vs TEMPERATURE INTEGRAL NONLINEARITY vs INPUT VOLTAGE
INPUT CURRENTS WITH LARGE DIFFERENTIAL
(V
IN+
TYPICAL CHARACTERISTICS: V+ = +12V (continued)
= (V
– V
SENSE
IN+
Figure 7. Figure 8.
VOLTAGES
at 12V, Sweep of V
) = 32mV, PGA = ÷ 1, and BRNG = 1, unless otherwise noted.
IN–
) ACTIVE IQvs TEMPERATURE
IN–
SBOS491 –JUNE 2010
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 9
Figure 9. Figure 10.
Product Folder Link(s): TMP512 TMP513
I ( )
Q
mA
V (SV)
4.53.0 3.5 4.0 5.55.02.5
120
100
80
60
40
20
0
Note: Shutdown I vs V is for Subregulator Configuration 3
Q S
-40
-25
0
25
125
I ( A)m
Q
Temperature ( C)°
V+ = 5.5V
V+ = 12V
V+ = 3V
50 75 100
140
120
100
80
60
40
20
0
Note: Shutdown I vs Temperature is
for Subregulator Configurations 1 and 2
Q
1k
10k
100k
1M
10M
I ( A)m
Q
SCL Frequency (Hz)
V+ = 12V
V+ = 3.3V
1100
1050
1000
950
900
850
800
1k
10k
100k
1M
10M
I ( A)m
Q
SCL Frequency (Hz)
250
200
150
100
50
0
V+ = 12V
V+ = 3.3V
TMP512
TMP513
SBOS491 –JUNE 2010
At TA= +25°C, V+ = 12V, V
SHUTDOWN IQvs TEMPERATURE SUPPLY VOLTAGE
ACTIVE IQvs TWO-WIRE CLOCK FREQUENCY SHUTDOWN IQvs TWO-WIRE CLOCK FREQUENCY
TYPICAL CHARACTERISTICS: V+ = +12V (continued)
= (V
– V
SENSE
IN+
Figure 11. Figure 12.
) = 32mV, PGA = ÷ 1, and BRNG = 1, unless otherwise noted.
IN–
SHUTDOWN IQvs
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Figure 13. Figure 14.
Product Folder Link(s): TMP512 TMP513
Remote Temperature Error ( )°C
R ( W )
S
2.0
1.5
1.0
0.5
0
-0.5
-1.0
-1.5
-2.0
0 3500500 1000 1500 2000 2500 3000
Note: For all three subregulator configurations.
Remote Temperature Error ( )°C
R ( W )
S
2.0
1.5
1.0
0.5
0
-0.5
-1.0
-1.5
-2.0
0 3500500 1000 1500 2000 2500 3000
Note: For all three subregulator configurations.
3
2
1
0
-1
-2
-3
Capacitance(nF)
0 0.5 1.0 1.5 2.0 2.5 3.0
RemoteTemperatureError( C)°
TMP512
TMP513
www.ti.com
At TA= +25°C, V+ = 12V, V
REMOTE TEMPERATURE ERROR vs SERIES REMOTE TEMPERATURE ERROR vs SERIES
(Diode-Connected Transistor, 2N3906 PNP) (GND Collector-Connected Transistor, 2N3906 PNP)
TYPICAL CHARACTERISTICS: V+ = +12V (continued)
= (V
– V
SENSE
IN+
RESISTANCE RESISTANCE
Figure 15. Figure 16.
) = 32mV, PGA = ÷ 1, and BRNG = 1, unless otherwise noted.
IN–
REMOTE TEMPERATURE ERROR
vs DIFFERENTIAL CAPACITANCE
SBOS491 –JUNE 2010
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 11
Figure 17.
Product Folder Link(s): TMP512 TMP513
(b) Diode-Connected Transistor
(a) GND Collector-Connected Transistor
DXP
DXN
R
S1
(1)
R
S2
(1)
DXP
DXN
R
S1
(1)
R
S2
(1)
(b) Diode-ConnectedTransistor
(a) GNDCollector-ConnectedTransistor
DXP
DXN
C
DIFF
(1)
DXP
DXN
C
DIFF
(1)
TMP512
TMP513
SBOS491 –JUNE 2010
PARAMETRIC MEASUREMENT INFORMATION
TYPICAL CONNECTIONS
SERIES RESISTANCE CONFIGURATION
(1) RS1+ RS2should be less than 1kΩ; see Filtering section.
DIFFERENTIAL CAPACITANCE CONFIGURATION
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Figure 18.
(1) C
12 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
should be less than 2200pF; see Filtering section.
DIFF
Figure 19.
Product Folder Link(s): TMP512 TMP513
Configuration 1 Configuration 2 Configuration 3
GND
ADC
Subregulator
3.3V
Subregulator
3.3V
V+ = 4.5V to 26V
Filter C
Load
470nF
Bus Voltage Range = 4.5V to 26V
Shunt
R
SHUNT
V
IN+
V
IN-
GND
ADC
V+ = 4.5V to 26V
Load
Filter C
470nF
Bus Voltage Range = 0V to 26V
Shunt
R
SHUNT
V
IN+
V
IN-
GND
ADC
Subregulator
3.3V
V+ = 3V to 5.5V
Load
Filter C
100nF
Bus Voltage Range = 0V to 26V
Shunt
R
SHUNT
V
IN+
V
IN-
TMP512
TMP513
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SBOS491 –JUNE 2010
APPLICATION INFORMATION
between the two systems is being addressed. Two
DESCRIPTION
The TMP512/13 are digital temperature sensors with
a digital current-shunt monitor that combine a local
die temperature measurement channel and remote
junction temperature measurement channels: two for
the TMP512 and three for the TMP513. The
TMP512/13 contain multiple registers for holding The subregulator can be configured to three different
configuration information, temperature, and voltage modes of operation. Each mode has its advantage
measurement results. These devices provide digital and limitation. Figure 20 shows the three
current, voltage, and power readings necessary for configuration arrangements. The minimum
accurate decision-making in precisely-controlled capacitance on the Filter C pin for Configurations 1
systems. Programmable registers allow flexible and 2 is 470nF. The minimum capacitance on the
configuration for setting warning limits, measurement Filter C pin for Configuration 3 is 100nF.
resolution, and continuous-versus-triggered
operation. Detailed register information appears at
the end of this data sheet, beginning with Table 3.
For proper remote temperature sensing operation, the V+ supply range of 4.5V to 26V connected to the
TMP512 requires transistors connected between shunt voltage, the bus voltage range cannot go to
DXP1 and DXN1 and between DXP2 and DXN2, and zero and is limited to 4.5V to 26V.
for the TMP513, between DXP3 and DXN3 as well.
Unused channels on the TMP512/13 must be
connected to GND.
The TMP512/13 offer compatibility with two-wire and is not limited to 4.5V as in Configuration 1.
SMBus interfaces. The two-wire and SMBus
protocols are essentially compatible with each other.
Two-wire is used throughout this data sheet, with
SMBus being specified only when a difference
bi-directional lines, SCL and SDA, connect the
TMP512/13 to the bus. SDA is an open-drain
connection. See Figure 21 for a typical application
circuit.
SUBREGULATOR
Configuration 1 has V+ and V
supplies the subregulator, which in turn supplies the
3.3V to the Filter C pin and the internal die. With the
Configuration 2 has V+ to the subregulator without
any other connections. Under this configuration, the
bus voltage range can go from 0V to 26V, because it
Configuration 3 has the subregulator V+ and Filter C
pins shorted together. V+ is limited to 3V to 5.5V
because the Filter C pin supplies the internal die; it
cannot exceed this voltage range. The bus voltage
range can go from 0V to 26V, because it is not limited
to 4.5V as in Configuration 1.
tied together. V+
IN+
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 13
Figure 20. Typical Subregulator Configurations
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TMP512
TMP513
SBOS491 –JUNE 2010
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SERIES RESISTANCE CANCELLATION Local Temperature Result Register and the Remote
Series resistance in an application circuit that typically
results from printed circuit board (PCB) trace
resistance and remote line length is automatically
cancelled by the TMP512/13, preventing what would
otherwise result in a temperature offset. A total of up
to 3kΩ of series line resistance is cancelled by the
TMP512/13, eliminating the need for additional
characterization and temperature offset correction.
See the Remote Temperature Error vs Series
Resistance typical characteristic curves (Figure 15 )
for details on the effects of series resistance and
power-supply voltage on sensed remote temperature
error.
Temperature Result Registers. Note that byte 1 is the
most significant byte, followed by byte 2, the least
significant byte. The first 13 bits are used to indicate
temperature. The least significant byte does not have
to be read if that information is not needed. The data
format for temperature is summarized in Table 10.
One LSB equals 0.0625°C. Negative numbers are
represented in binary twos complement format.
Following power-up or reset, the Temperature
Register will read 0°C until the first conversion is
complete. Unused bits in the Temperature Register
always read '0'.
REGISTER INFORMATION
DIFFERENTIAL INPUT CAPACITANCE The TMP512/13 contain multiple registers for holding
The TMP512/13 can tolerate differential input
capacitance of up to 2200pF with minimal change in
temperature error. The effect of capacitance on
sensed remote temperature error is illustrated in
Figure 16, Remote Temperature Error vs Differential
Capacitance. See the Filtering section for suggested
component values where filtering unwanted coupled
signals is needed.
configuration information, temperature and voltage
measurement results, and status information. These
registers are described in Table 3.
POINTER REGISTER
The 8-bit Pointer Register is used to address a given
data register. The Pointer Register identifies which of
the data registers should respond to a read or write
command on the two-wire bus. This register is set
TEMPERATURE MEASUREMENT DATA with every write command. A write command must be
Temperature measurement data may be taken over
an operating range of –40°C to +125°C for both local
and remote locations.
The Temperature Register of the TMP512/13 is
configured as a 13-bit, read-only register that stores
the output of the most recent conversion. Two bytes
must be read to obtain data, and are described in the
issued to set the proper value in the Pointer Register
before executing a read command. Table 3 describes
the pointer address of the TMP512/13 registers. The
power-on reset (POR) value of the Pointer Register is
00h (0000 0000b).
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Product Folder Link(s): TMP512 TMP513
V V =-
BE2 BE1
nkT
q
I
I
2
1
(
(
In
n =
eff
1.008 300
(300 N )-
ADJUST
´
N 300
ADJUST
-=
300 1.008
n
eff
´
(
(
´
Power Register
Current Register
Two-Wire
Interface
Voltage Register
ADC
GND
GPIO
DXP1
DXN1
DXP2
DXN2
ADC
Low-Pass Filter
MUX
DXP3
DXN3
V
IN+
V
IN-
Current
Shunt
Load
Filter C
V+
Subregulator
3.3V
Internal
Diode
Temperature
Sensor
A0
ALERT
SDA
SCL
SMBus
Controller
3.3V Supply
TMP512
TMP513
TMP512
TMP513
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SBOS491 –JUNE 2010
n-FACTOR CORRECTION REGISTER twos-complement format, yielding an effective data
The TMP512/13 allow for a different n-factor value to
be used for converting remote channel
measurements to temperature. The remote channel
uses sequential current excitation to extract a
differential VBEvoltage measurement to determine
the temperature of the remote transistor. Equation 1
describes this voltage and temperature.
(1)
The value n in Equation 1 is a characteristic of the
particular transistor used for the remote channel. The
power-on reset value for the TMP512/13 is n = 1.008.
The value in the n-Factor Correction Register may be
used to adjust the effective n-factor according to
Equation 2 and Equation 3.
(2)
(3)
The n-factor value must be stored in Acknowledge and pulling SDA LOW.
range from –128 to +127. The n-factor value may be
written to and read from pointer address 16h for
remote channel 1, pointer address 17h for remote
channel 2, and pointer address 18h for remote
channel 3. The register power-on reset value is 00h,
thus having no effect unless the register is written to.
BUS OVERVIEW
The device that initiates the transfer is called a
master, and the devices controlled by the master are
slaves. The bus must be controlled by a master
device that generates the serial clock (SCL), controls
the bus access, and generates START and STOP
conditions.
To address a specific device, the master initiates a
START condition by pulling the data signal line (SDA)
from a HIGH to a LOW logic level while SCL is HIGH.
All slaves on the bus shift in the slave address byte
on the rising edge of SCL, with the last bit indicating
whether a read or write operation is intended. During
the ninth clock pulse, the slave being addressed
responds to the master by generating an
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 15
Figure 21. Typical Application Circuit
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TMP513
SBOS491 –JUNE 2010
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Data transfer is then initiated and eight bits of data WRITING TO/READING FROM THE
are sent, followed by an Acknowledge bit. During TMP512/13
data transfer, SDA must remain stable while SCL is
HIGH. Any change in SDA while SCL is HIGH is
interpreted as a START or STOP condition.
Accessing a particular register on the TMP512/13 is
accomplished by writing the appropriate value to the
register pointer. Refer to Table 3 for a complete list of
Once all data have been transferred, the master registers and corresponding addresses. The value for
generates a STOP condition, indicated by pulling the register pointer as shown in Figure 24 is the first
SDA from LOW to HIGH while SCL is HIGH. The byte transferred after the slave address byte with the
TMP512/13 includes a 28ms timeout on its interface R/W bit LOW. Every write operation to the
to prevent locking up an SMBus. TMP512/13 requires a value for the register pointer.
SERIAL BUS ADDRESS
To communicate with the TMP512/13, the master
must first address slave devices via a slave address
byte. The slave address byte consists of seven
address bits, and a direction bit indicating the intent
of executing a read or write operation.
The TMP512/13 feature an address pin to allow up to
four devices to be addressed on a single bus. Table 1
describes the pin logic levels used to properly
connect up to four devices. The state of the A0 pin is
sampled on every bus communication and should be
set before any activity on the interface occurs. The
address pin is read at the start of each
communication event.
Writing to a register begins with the first byte
transmitted by the master. This byte is the slave
address, with the R/W bit LOW. The TMP512/13 then
acknowledge receipt of a valid address. The next
byte transmitted by the master is the address of the
register to which data will be written. This register
address value updates the register pointer to the
desired register. The next two bytes are written to the
register addressed by the register pointer. The
TMP512/13 acknowledge receipt of each data byte.
The master may terminate data transfer by
generating a START or STOP condition.
When reading from the TMP512/13, the last value
stored in the register pointer by a write operation
determines which register is read during a read
operation. To change the register pointer for a read
Table 1. TMP512/13 Address Pins and
operation, a new value must be written to the register
Slave Addresses pointer. This write is accomplished by issuing a slave
DEVICE TWO-WIRE
ADDRESS A0 PIN CONNECTION
1011100 Ground
1011101 V+
1011110 SDA
1011111 SCL
address byte with the R/W bit LOW, followed by the
register pointer byte. No additional data are required.
The master then generates a START condition and
sends the slave address byte with the R/W bit HIGH
to initiate the read command. The next byte is
transmitted by the slave and is the most significant
byte of the register indicated by the register pointer.
This byte is followed by an Acknowledge from the
SERIAL INTERFACE
master; then the slave transmits the least significant
byte. The master acknowledges receipt of the data
The TMP512/13 operate only as slave devices on the byte. The master may terminate data transfer by
two-wire bus and SMBus. SCL is an input only, and generating a Not-Acknowledge after receiving any
TMP512/13 cannot drive it. Connections to the bus data byte, or generating a START or STOP condition.
are made via the open-drain I/O lines SDA and SCL. If repeated reads from the same register are desired,
The SDA and SCL pins feature integrated spike it is not necessary to continually send the register
suppression filters and Schmitt triggers to minimize pointer bytes; the TMP512/13 retain the register
the effects of input spikes and bus noise. The pointer value until it is changed by the next write
TMP512/13 support the transmission protocol for fast operation.
(1kHz to 400kHz) and high-speed (1kHz to 3.4MHz)
modes. All data bytes are transmitted MSB first.
Figure 22 and Figure 23 show read and write
operation timing diagrams, respectively. Note that
register bytes are sent most-significant byte first,
followed by the least significant byte. See Figure 25
for an illustration of a typical register pointer
configuration.
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Frame1Two-WireSlaveAddressByte
(1)
Frame2DataMSByte
(2)
1
StartBy
Master
ACKBy
TMP512/TMP513
ACKBy
Master
From
TMP512/TMP513
1 9 1
9
SDA
SCL
0 1 1 R/
W D15 D14 D13 D12 D11 D10 D9 D8
1 A1 A0
Frame3DataLSByte
(2)
StopNoACKBy
(3)
Master
From
TMP512/TMP513
1
9
D7 D6 D5 D4 D3 D2 D1 D0
NOTES:(1)ThevalueoftheSlaveAddressByteisdeterminedbythesettingsoftheA0pin.
RefertoTable1.
(2)Readdataisfromthelastregisterpointerlocation.Ifanewregisterisdesired,theregister
pointermustbeupdated.SeeFigure23.
(3)ACKbyMastercanalsobesent.
Frame1Two-WireSlaveAddressByte
(1)
Frame2RegisterPointerByte
StartBy
Master
ACKBy
TMP512/TMP513
ACKBy
TMP512/TMP513
1 9 1
ACKBy
TMP512/TMP513
1
D15 D14 D13 D12 D11 D10 D9 D8
9
9
SDA
SCL
1 0 1 1 1
A1 A0 R/W P7 P6 P5 P4 P3 P2 P1 P0
NOTE(1):ThevalueoftheSlaveAddressByteisdeterminedbythesettingsoftheA0pin.RefertoTable1.
Frame4DataLSByteFrame3DataMSByte
ACKBy
TMP512/TMP513
StopBy
Master
1
D7 D6 D5 D4 D3 D2 D1 D0
9
TMP512
TMP513
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SBOS491 –JUNE 2010
Figure 22. Timing Diagram for Write Word Format
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): TMP512 TMP513
Figure 23. Timing Diagram for Read Word Format
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