Texas Instruments TLV987CPFB Datasheet
TLV987
3-V 10-BIT 27 MSPS AREA CCD SENSOR
SIGNAL PROCESSOR
SLAS211A – MARCH 1999 – REVISED SEPTEMBER 1999
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
10-Bit, 27 MSPS, A/D Converter
D
Single 3-V Supply Operation
D
Low Power: 200 mW Typical at 3 V, 2 mW
Power-Down Mode
D
Differential Nonlinearity Error: <±0.6 LSB
Typ
D
Integral Nonlinearity Error: <±2 LSB Typ
D
Programmable Gain Amplifier (PGA) With
0-dB to 36-dB Gain Range (0.09 dB/step)
D
Automatic or Programmable Black Level
and Offset Calibration
D
Additional DACs for External Analog
Setting
D
Serial Interface for Register Configuration
D
Internal Reference Voltages
D
48-Pin TQFP Package
applications
D
Digital Still Camera
D
Digital Camcorder
D
Digital Video Camera
description
The TLV987 is a highly integrated monolithic analog signal processor/digitizer designed to interface the area
charge-coupled device (CCD) sensors in digital camera applications. The TLV987 performs all the analog
processing functions necessary to maximize the dynamic range, corrects various errors associated with the
CCD sensor, and then converts the results from analog to digital using the on-chip high-speed analog-to-digital
converter (ADC). The key components of the TL V987 include input clamp circuitry, a correlated double sampler
(CDS), and a programmable gain amplifier (PGA). The PGA has 0-dB to 36-dB gain range. In addition, the
TL V987 has two internal digital-to-analog converters (DACs) for automatic or programmable optical black level
and offset calibration. The TLV987 also has two additional DACs for external system control, and internal
reference voltages. The TL V987 has a parallel data port for easy microprocessor interface and a serial port for
configuring internal control registers.
Designed in advanced CMOS process, the TLV987 operates from a single 3-V power supply with a normal
power consumption of 200 mW and a 2 mW power-down mode.
Very high throughput rate, single 3-V operation, low power consumption, and fully integrated analog processing
circuitry make the TLV987 an ideal CCD sensor interfacing solution for digital camera applications.
The device is available in a 48-pin TQFP package and is characterized for operation over 0°C to 70°C operating
free-air temperature range.
AVAILABLE OPTIONS
PACKAGE
T
A
TQFP (PFB)
0°C to 70°C TLV987CPFB
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
14 15
BLKG
TPP
TPM
AV
DD4
AGND4
OBCLP
STBY
RESET
CS
SDIN
SCLK
ADCCLK
36
35
34
33
32
31
30
29
28
27
26
25
16
1
2
3
4
5
6
7
8
9
10
11
12
DIN
PIN
AV
DD2
AGND2
DGND
DV
DD
D0
D1
D2
D3
D4
D5
17 18 19 20
AV
RPD
RMD
RBD
47 46 45 44 4348 42
CLREF
CLAMPSVSR
AGND1
DACO2
DACT
OE
D8
DIV
DIGND
AV
AGND3
40 39 3841
21 22 23 24
37
13
AGND5
AV
V
D7D6D9
PFB PACKAGE
(TOP VIEW)
SS
DD1
DD5
DD
DD3
DACO1
TI is a trademark of Texas Instruments Incorporated.
TLV987
3-V 10-BIT 27 MSPS AREA CCD SENSOR
SIGNAL PROCESSOR
SLAS211A – MARCH 1999 – REVISED SEPTEMBER 1999
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
Digital
Averager
SV
DIN
Digital Comparator
Fine Offset Control
Σ
DAC
Register
CDS
Three
State
Latch
8-Bit
DAC
Control
Logic
8-Bit
DAC
8-Bit
DAC
10-Bit
ADC
Offset
Register
Offset
Register
PGA
Register
V
b
Register
OB CAL
Register
Internal
Reference
Clamp
Serial
Port
CLAMP
PIN
DACO1
DACO2
OE
D0–D9
RESET
ADCCLK
CLREF TPP TPM RPD RBD RMD
SR
BLKG
OBCLP
STBY
CS
SCLK
SDIN
Σ
PGA
Coarse
Offset
Control
8-Bit
DAC
1.3 V
9
Overflow
DAC
Register
(40)
(47)
(48)
(34)
(39)
(35)
(1)
(2)
(21)
(22)
(24)
(38)
(7-16)
(29)
(25)
(46)
(45)
(36)
(31)
(30)
(28)
(26)
(27)
(23)
DACT
TLV987
3-V 10-BIT 27 MSPS AREA CCD SENSOR
SIGNAL PROCESSOR
SLAS211A – MARCH 1999 – REVISED SEPTEMBER 1999
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NAME NO.
I/O
DESCRIPTION
ADCCLK 25 I ADC clock input.
AGND1 44 Analog ground for internal CDS circuits
AGND2 4 Analog ground for internal PGA circuits
AGND3 20 Analog ground for internal DAC circuits
AGND4 32 Analog ground for internal ADC circuits
AGND5 37 Analog ground for internal REF circuits
AV
DD1
43 Analog supply voltage for internal CDS circuits, 3 V
AV
DD2
3 Analog supply voltage for internal PGA circuits, 3 V
AV
DD3
19 Analog supply voltage for internal DAC circuits, 3 V
AV
DD4
33 Analog supply voltage for internal ADC circuits, 3 V
AV
DD5
41 Analog supply voltage for internal ADC circuits, 3 V
BLKG 36 I Control input. CDS operation is disabled when BLKG is pulled low.
CLAMP 47 I CCD signal clamp control input
CLREF 48 O Clamp reference voltage output.
CS 28 I Chip select. A logic low on this input enables the TLV987.
DACO1 21 O Digital-to-analog converter output1
DACO2 22 O Digital-to-analog converter output2
DACT 23 O MUXed test output for internal offset DACs
DGND 5 Digital ground
DIGND 18 Digital interface circuit ground
DIN 1 I Input signal from CCD
DIV
DD
17 Digital interface circuit supply voltage, 1.8 V to 4.4 V
DV
DD
6 Digital supply voltage, 3 V
D0 – D9 7 – 16 O 10-bit three-state ADC output data or of fset DACs test data
OBCLP 31 I Optical black level and offset calibration control input. Active low.
OE 24 I Output data enable. Active low.
PIN 2 I Input signal from CCD
RBD 38 O Internal bandgap reference for external decoupling
RMD 39 O Ref– output for external decoupling
RPD 40 O Ref+ output for external decoupling
RESET 29 I Hardware reset input, active low. This signal forces a reset of all internal registers.
SCLK 26 I Serial clock input. This clock synchronizes the serial data transfer.
SDIN 27 I Serial data input to configure the internal registers.
SR 45 I CCD reference level sample clock input
STBY 30 I Hardware power-down control input, active low
SV 46 I CCD signal level sample clock input
TPM 34 O MUXed test output: PGA noninverting output or inverted PGA clock
TPP 35 O MUXed test output: PGA inverting output or inverted CDS clock
V
SS
42 Silicon substrate, normally connected to analog ground
TLV987
3-V 10-BIT 27 MSPS AREA CCD SENSOR
SIGNAL PROCESSOR
SLAS211A – MARCH 1999 – REVISED SEPTEMBER 1999
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
†
Supply voltage range, AVDD, DVDD, DIVDD –0.3 V to 6.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog input voltage range –0.3 V to AVDD+0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital input voltage range –0.3 V to DV
DD
+0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature range, T
J
–40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
A
0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
power supplies
MIN NOM MAX UNIT
Analog supply voltage, A V
DD
2.7 3 3.3 V
Digital supply voltage, DV
DD
2.7 3 3.3 V
Digital interface supply voltage, DIV
DD
1.8 4.4 V
digital inputs
MIN NOM MAX UNIT
High-level input voltage, V
IH
DIVDD = 3 V 0.8DIV
DD
V
Low-level input voltage, V
IL
DIVDD = 3 V 0.2DIV
DD
V
Clock frequency, ADCCLK, f
clock1
DVDD = 3 V 27 MHz
Pulse duration, ADCCLK, high, t
w(CLKH)1
DVDD = 3 V 18.5 ns
Pulse duration, ADCCLK, low, t
w(CLKL)1
DVDD = 3 V 18.5 ns
Clock frequency, SCLK, f
clock2
DVDD = 3 V 40 MHz
Pulse duration, SCLK high, t
w(CLKH)2
DVDD = 3 V 12.5 ns
Pulse duration, SCLK low, t
w(CLKL)2
DVDD = 3 V 12.5 ns
TLV987
3-V 10-BIT 27 MSPS AREA CCD SENSOR
SIGNAL PROCESSOR
SLAS211A – MARCH 1999 – REVISED SEPTEMBER 1999
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range,
AV
DD
= DVDD = 3 V, ADCCLK = 27 MHz (unless otherwise noted)
total device
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AI
CC
Analog operating supply current 66 mA
DI
CC
Digital operation supply current 1 mA
Device power consumption 200 mW
Power consumption in power-down mode 2 mW
DNL Full channel differential nonlinearity –1 ±0.6 1.5 LSB
INL Full channel integral nonlinearity ±2 LSB
analog-to-digital converter (ADC)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ADC resolution 10 Bits
Full-scale input span 2 V
PP
Conversion rate 27 MHz
ADC output latency 4.5
CLK
cycles
No missing codes Assured
correlated double sampler (CDS) and programmable gain amplifier (PGA)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CDS and PGA sample rate 27 MHz
CDS full-scale input span Single-ended input 1 V
Input capacitance of CDS 4 pF
Minimum PGA gain 0 1 dB
Maximum PGA gain 35 36 37 dB
PGA gain resolution 0.09 dB
PGA programming code resolution 8-bit monotonic gain control 9 Bits
internal digital-to-analog converters (DAC) for offset correction
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DAC resolution 8 Bits
INL Integral nonlinearity ±0.6 ±1.2 LSB
DNL Differential nonlinearity ±0.5 ±.99 LSB
Output settling time To 1% accuracy 80 ns
user digital-to-analog converters (DAC)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DAC resolution 8 Bits
INL Integral nonlinearity ±0.5 ±1.2 LSB
DNL Differential nonlinearity ±0.5 ±.99 LSB
Output voltage 0 AV
DD
V
Output settling time 10-pF external load, Settle to 1 mV 4 µs
TLV987
3-V 10-BIT 27 MSPS AREA CCD SENSOR
SIGNAL PROCESSOR
SLAS211A – MARCH 1999 – REVISED SEPTEMBER 1999
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range,
AV
DD
= DVDD = 3 V, ADCCLK = 27 MHz (unlessotherwise noted)
reference voltages
TEST CONDITIONS MIN TYP MAX UNIT
Internal bandgap voltage reference 1.43 1.5 1.58 V
T emperature coef ficient 100 ppm/°C
Voltage reference noise 0.5 LSB
Positive reference voltage, ADC Ref+ Externally decoupled 1.8 2 2.2 V
Negative reference voltage, ADC Ref– Externally decoupled 0.8 1 1.2 V
digital specifications
PARAMETER TEST CONDITIONS
MIN TYP MAX UNIT
LOGIC INPUTS
I
IH
High-level input current DIVDD = 3 V –10 10 µA
I
IL
Low-level input current DIVDD = 3 V –10 10 µA
C
i
Input capacitance 5 pF
LOGIC OUTPUTS
V
OH
High-level output voltage IOH = 50 µA, DIVDD = 3 V DIVDD–0.4 V
V
OL
Low-level output voltage IOL = 50 µA, DIVDD = 3 V 0.4 V
I
OZ
High-impedance output current –10 10 µA
C Output capacitance 5 pF
timing requirements
PARAMETER TEST CONDITIONS
MIN TYP MAX UNIT
t
w(SR)
Pulse duration, SR 50% to 50% 10 ns
t
w(SV)
Pulse duration, SV 50% to 50% 10 ns
t
su1
Setup time, OBCLP ↓ before ADCCLK ↑ Minimum 0.25 × ADCCLK clock cycle
t
h2
Hold time, ADCCLK ↓ after OBCLP ↑
t
d
Delay time, ADCCLK ↓ to ADCOUT valid 4 9 ns
t
su2
Setup time, CS ↓ before SCLK ↑ 0 ns
t
h1
Hold time, SCLK ↓ after CS ↑ 5 ns
0
5
10
15
20
25
30
35
40
0 28 56 84 112 140 168 196 224 252 280 308 336 364 392 420 448 476 504
Gain – dB
PGA – Gain Code
Figure 1. TL V987 PGA Gain Code vs Gain
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