Texas Instruments TLV986CPFB Datasheet
TLV986
3-V, 10-BIT, 12.5 MSPS, AREA CCD SENSOR PROCESSOR
SLAS228 – JUL Y 1999
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
10-bit, 12.5 MSPS, A/D Converter
D
Single 3 V Supply Operation
D
Low Power: 140 mW Typical at 3-V, 2 mW
Power-Down Mode
D
Full Channel Differential Nonlinearity Error:
<±0.5 LSB Typical
D
Full Channel Integral Nonlinearity Error:
<±1 LSB Typical
D
Programmable Gain Amplifier (PGA) With
0 dB to 36 dB Gain Range (0.1 dB/Step)
D
Automatic or Programmable Black Level
and Offset Calibration
D
Additional DACs for External Analog
Setting
D
Serial Interface for Register Configuration
D
Internal Reference Voltages
D
48-pin TQFP Package
applications
D
PC Camera
D
Digital Still Camera
D
Digital Video Camera
description
The TLV986 is a highly integrated monolithic analog signal processor/digitizer designed to interface the area
charge-coupled device (CCD) sensors in digital camera applications. The TLV986 performs all the analog
processing functions necessary to maximize the dynamic range, corrects various errors associated with the
CCD sensor, and then digitizes the results with an on-chip high-speed analog-to-digital converter (ADC). The
key components of the TLV986 include: input clamp circuitry and a correlated double sampler (CDS), a
programmable gain amplifier (PGA) with 0 to 36 dB gain range, two internal digital-to-analog converters (DAC)
for automatic or programmable optical black level and offset calibration, a 10-bit, 12.5 MSPS pipeline ADC, a
parallel data port for easy microprocessor interface, a serial port for configuring internal control registers, two
additional DACs for external system control, and internal reference voltages.
Designed in advanced CMOS process, the TLV986 operates from a single 3-V power supply with a normal
power consumption of 140 mW and a 2 mW power-down mode.
Single 3-V operation, low power consumption, and fully integrated analog processing circuitry make the TL V986
an ideal CCD sensor interfacing solution for the digital camera applications.
The part is available in a 48-pin TQFP package and is specified over 0_C to 70_C operating temperature range.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
14 15
BLKG
TPP
TPM
AV
DD4
AGND4
OBCLP
STBY
RESET
CS
SDIN
SCLK
ADCCL
K
36
35
34
33
32
31
30
29
28
27
26
25
16
1
2
3
4
5
6
7
8
9
10
11
12
DIN
PIN
AV
DD2
AGND2
DGND
DV
DD
D0
D1
D2
D3
D4
D5
17 18 19 20
AV
RPD
RMD
RBD
47 46 45 44 4348 42
CLREF
CLAMPSVSR
AGND1
DAC02
DACT
OE
D8
DD
DIGND
DD3
AGND3
DAC01
40 39 3841
21 22 23 24
37
13
AGND5
AV
V
D7D6D9
PFB PACKAGE
(TOP VIEW)
DIV
AV
DD5
SS
DD1
TLV986CPFB
TLV986
3-V, 10-BIT, 12.5 MSPS, AREA CCD SENSOR PROCESSOR
SLAS228 – JUL Y 1999
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
AVAILABLE OPTIONS
PACKAGED DEVICES
T
A
TQFP (PFB)
–0_C to 70_C TLV986CPFB
functional block diagram
CLAMP CLREF AV
DD1–5
TPP TPM RPD RBD RMD
INT. REF.
DV
DD
DIV
DD
CLAMP 1.2 V
CDS
DIN
PIN
∑
PGA
8–BIT
DAC
OFFSET
REG
COARSE
OFFSET
CONTROL
PGA
REG
9
10–BIT
ADC
∑
8–BIT
DAC
OFFSET
REG
DIGITAL COMPARATOR
FINE OFFSET CONTROL
Vb
REG
DIGITAL
AVERAGER
OB CAL
REG
DAC01
DAC02
8–BIT
ADC
DAC
REG
8–BIT
ADC
DAC
REG
OVERFLOW
CONTROL
LOGIC
RESET
CLK
SV
SR
BLKG
OBCLP
STBY
SERIAL
PORT
CS
SCLK
SDIN
THREE
STATE
LATCH
D0
D9
OE
AGND1–5 DACTV
SS
DGND DIGND
TLV986
3-V, 10-BIT, 12.5 MSPS, AREA CCD SENSOR PROCESSOR
SLAS228 – JUL Y 1999
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NAME NO.
I/O
DESCRIPTION
ADCCLK 25 I ADC clock input
AGND1 44 Analog ground for internal CDS circuits
AGND2 4 Analog ground for internal PGA circuits
AGND3 20 Analog ground for internal DAC circuits
AGND4 32 Analog ground for internal ADC circuits
AGND5 37 Analog ground for internal REF circuits
AV
DD1
43 Analog supply voltage for internal CDS circuits, 3 V
AV
DD2
3 Analog supply voltage for internal PGA circuits, 3 V
AV
DD3
19 Analog supply voltage for internal DAC circuits, 3 V
AV
DD4
33 Analog supply voltage for internal ADC circuits, 3 V
AV
DD5
41 Analog supply voltage for internal ADC circuits, 3 V
BLKG 36 Control input. The CDS operation is disabled when the BLKG is pulled low.
CLAMP 47 I CCD signal clamp control input
CLREF 48 O Clamp reference voltage output
CS 28 I Chip Select. A logic low on this input enables the TLV986.
D0–D9 7–16 O 10-bit 3-state ADC output data or offset DACs test data
DACO1 21 O Digital-to-analog converter output1
DACO2 22 O Digital-to-analog converter output2
DACT 23 O MUXed test output for internal offset DACs
DGND 5 Digital ground
DIGND 18 Digital interface circuit ground
DIN 1 I Input signal from CCD
DIV
DD
17 Digital interface circuit supply voltage, 1.8 V – 4.4 V
DV
DD
6 Digital supply voltage, 3-V
OBCLP 31 I Optical black level and offset calibration control input, active low
OE 24 I Output data enable, active low
PIN 2 I Input signal from CCD
RESET 29 I Hardware reset input, active low. This signal forces a reset of all internal registers.
RBD 38 O Internal bandgap reference for external decoupling
RMD 39 O Ref– output for external decoupling
RPD 40 O Ref+ output for external decoupling
SCLK 26 I Serial clock input. This clock synchronizes the serial data transfer.
SDIN 27 I Serial data input to configure the internal registers
SR 45 I CCD reference level sample clock input
STBY 30 I Hardware power-down control input, active low
SV 46 I CCD signal level sample clock input
TPM 34 O Muxed test output: PGA noninverting output or inverted PGA clock
TPP 35 O Muxed test output: PGA inverting output or inverted CDS clock
V
SS
42 Silicon substrate, normally connected to analog ground
TLV986
3-V, 10-BIT, 12.5 MSPS, AREA CCD SENSOR PROCESSOR
SLAS228 – JUL Y 1999
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
†
Supply voltage, AVDD, DVDD, DIVDD –0.3 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog input voltage range –0.3 V to AVDD+0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital input voltage range –0.3 V to AV
DD
+0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature range, TJ –40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
STG
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 in) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
power supplies
MIN NOM MAX UNIT
Analog supply voltage, A V
DD
2.7 3 3.3 V
Digital supply voltage, DV
DD
2.7 3 3.3 V
Digital interface supply voltage, DIV
DD
1.8 4.4 V
digital inputs
MIN NOM MAX UNIT
High–level input voltage, V
IH
DIVDD = 3 V 0.8DIV
DD
V
Low–level input voltage, V
IL
DIVDD = 3 V 0.2DIV
DD
V
Input ADCCLK frequency DVDD = 3 V 12.5 MHz
ADCCLK pulse duration, clock high, t
w(MCLK)
DVDD = 3 V 40 ns
ADCCLK pulse duration, clock low, t
w(MCLKL)
DVDD = 3 V 40 ns
Input SCLK frequency DVDD = 3 V 40 MHz
SCLK pulse duration, clock high, t
w(SCLKH)
DVDD = 3 V 12.5 ns
SCLK pulse duration, clock low, t
w(SCLKL)
DVDD = 3 V 12.5 ns
TLV986
3-V, 10-BIT, 12.5 MSPS, AREA CCD SENSOR PROCESSOR
SLAS228 – JUL Y 1999
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range,
T
A
= 25°C, AVDD = DVDD = 3 V, ADCCLK = 12.5 MHz (unlessotherwise noted)
total device
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AVDD operating current 41 mA
DVDD operation current 6 mA
Device power consumption 140 mW
Power consumption in power–down mode 2 mW
INL Full channel integral nonlinearity
±1 ±2 LSB
DNL Full channel differential nonlinearity
AV
DD
=
DV
DD
= 2.7 V – 3.
3V
–1 ±0.5 1.5 LSB
No missing code Assured
Full channel output latency 4.5
CLK
cycles
analog-to-digital converter (ADC)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ADC resolution 10 Bits
Full scale input span
2 V
P-P
Conversion rate 12.5 MHz
correlated double sampler (CDS) and programmable gain amplifier (PGA)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CDS and PGA sample rate 12.5 MHz
CDS full scale input span Single-ended input 1 V
Input capacitance of CDS 4 pF
Minimum PGA gain 0 1 dB
Maximum PGA gain 35 36 37 dB
PGA gain resolution 0.1 dB
PGA programming code resolution 8-bit monotonic gain control 9 Bits
internal digital-to-analog converters (DAC) for offset correction
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DAC resolution 8 Bits
INL Integral nonlinearity ±0.5 ±1.2 LSB
DNL Dif ferential nonlinearity ±0.5 ±0.9 LSB
Output settling time To 1% accuracy 80 ns
user digital-to-analog converters (DAC)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DAC resolution 8 Bits
INL Integral nonlinearity ±0.5 ±1.2 LSB
DNL Dif ferential nonlinearity ±0.6 ±0.9 LSB
Output voltage range 0 3 V
Output settling time 10 pF external load. Settle to 1 mV. 4 µs
TLV986
3-V, 10-BIT, 12.5 MSPS, AREA CCD SENSOR PROCESSOR
SLAS228 – JUL Y 1999
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range,
T
A
= 25°C, AVDD = DVDD = 3 V, ADCCLK = 12.5 MHz (unlessotherwise noted) (continued)
reference voltages
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Internal bandgap voltage reference 1.43 1.50 1.58 V
T emperature coef ficient 100 ppm/°C
ADC Reference+
p
1.8 2 2.2 V
ADC Reference–
Externally decoupled
0.9 1 1.1 V
digital specifications
logic inputs
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I
IH
High-level input current
–10 10 µA
I
IL
Low-level input current
DIV
DD
= 3
V
–10 10 µA
C
i
Input capacitance 5 pF
logic outputs
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
OH
High-level output voltage IOH = 50 µA, DIVDD = 3 V DIVDD–0.4 V
V
OL
Low-level output voltage IOL= 50 µA, DIVDD = 3 V 0.4 V
I
OZ
High-impedance-state output current –10 10 µA
C
O
Output capacitance 5 pF
key timing requirements
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
(SRW)
SR pulse width
p
10 ns
t
(SVW)
SV pulse width
Measured at 50% of pulse height
10 ns
t
(OBS)
OBCLP falling edge to ADCCLK rising edge Minimum 0.25 × one ADCCLK cycle
t
(OBE)
ADCCLK falling edge to OBCLP rising edge Not critical, but should not exceed 2N pixels
t
(OD)
ADCCLK to output data delay 4 9 ns
t
(CSF)
CS falling edge to SCLK rising edge 0 ns
t
(CSR)
SCLK falling edge to CS rising edge 5 ns
0
5
10
15
20
25
30
35
40
0 28 56 84 112 140 168 196 224 252 280 308 336 364 392 420 448 476 504
Gain – dB
PGA – Gain Code
TLV986 GAIN
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