TLV5614
2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188B – SEPTEMBER 1998 – REVISED APRIL 2003
D Four 12-Bit D/A Converters
D Programmable Settling Time of Either 3 µs
or 9 µs Typ
D TMS320, (Q)SPI, and Microwire
Compatible Serial Interface
D Dual 2.7-V to 5.5-V Supply (Separate Digital
and Analog Supplies)
D Hardware Power Down (10 nA)
D Software Power Down (10 nA)
D Simultaneous Update
D Internal Power-On Reset
D Low Power Consumption:
8 mW, Slow Mode – 5-V Supply
3.6 mW, Slow Mode – 3-V Supply
D Reference Input Buffer
D Voltage Output Range ...2× the Reference
Input Voltage
D Monotonic Over Temperature
description
The TL V5614 is a quadruple 12-bit voltage output
digital-to-analog converter (DAC) with a flexible
4-wire serial interface. The 4-wire serial interface
allows glueless interface to TMS320, SPI, QSPI,
and Microwire serial ports. The TLV5614 is
programmed with a 16-bit serial word comprised
of a DAC address, individual DAC control bits, and
a 12-bit DAC value. The device has provision for
two supplies: one digital supply for the serial
interface (via pins DV
the DACs, reference buffers, and output buffers (via pins A V
other, and can be any value between 2.7 V and 5.5 V. The dual supplies allow a typical application where the
DAC is controlled via a microprocessor operating on a 3 V supply (also used on pins DV
the DACs operating on a 5 V supply. Of course, the digital and analog supplies can be tied together.
and DGND), and one for
DD
applications
D Battery Powered Test Instruments
D Digital Offset and Gain Adjustment
D Industrial Process Controls
D Machine and Motion Control Devices
D Communications
D Arbitrary Waveform Generation
D OR PW PACKAGE
(TOP VIEW)
DV
LDAC
SCLK
DGND
and AGND). Each supply is independent of the
DD
DD
PD
DIN
CS
FS
1
2
3
4
5
6
7
8
AV
16
DD
REFINAB
15
OUTA
14
OUTB
13
OUTC
12
OUTD
11
REFINCD
10
AGND
9
and DGND), with
DD
The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer . The buffer features a Class AB
output stage to improve stability and reduce settling time. A rail-to-rail output stage and a power-down mode
makes it ideal for single voltage, battery based applications. The settling time of the DAC is programmable to
allow the designer to optimize speed versus power dissipation. The settling time is chosen by the control bits
within the 16-bit serial input string. A high-impedance buffer is integrated on the REFINAB and REFINCD
terminals to reduce the need for a low source impedance drive to the terminal. REFINAB and REFINCD allow
DACs A and B to have a different reference voltage then DACs C and D.
The TLV5614 is implemented with a CMOS process and is available in a 16-terminal SOIC package. The
TL V5614C is characterized for operation from 0°C to 70°C. The TLV5614I is characterized for operation from
–40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI and QSPI are trademarks of Motorola, Inc.
Microwire is a trademark of National Semiconductor Corporation.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1998 – 2003, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
TLV5614
2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188B – SEPTEMBER 1998 – REVISED APRIL 2003
AVAILABLE OPTIONS
PACKAGE
T
A
0°C to 70°C TLV5614CD TLV5614CPW –––
–40°C to 85°C TLV5614ID TLV5614IPW TLV5614IYE
†
Wafer Scale Packaging, also called Bumped Dice. See Figure 17.
functional block diagram
SOIC
(D)
TSSOP
(PW)
WSP
(YE)
†
REFINAB
DIN
FS
SCLK
CS
AV
DD
15 16 1
+
_
12-Bit
DAC
Latch
2-Bit
Control
Data
Latch
DAC B
Serial
4
Input
Register
7
DAC Select/
5
6
Power-On
Reset
2
Control
Logic
14
14-Bit
Data
and
Control
Register
12
2
DV
DD
10
2
2
Power-Down/
Speed Control
DAC A
+
_
13
14
OUTA
OUTB
REFINCD
2
10
9
AGND
8
DGND
DAC C
DAC D
32
LDAC
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PD
12
11
OUTC
OUTD
TLV5614
2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188B – SEPTEMBER 1998 – REVISED APRIL 2003
Terminal Functions
TERMINAL
NAME NO.
AGND 9 Analog ground
AV
DD
CS 6 I Chip select. This terminal is active low.
DGND 8 Digital ground
DIN 4 I Serial data input
DV
DD
FS
PD
LDAC
REFINAB 15 I Voltage reference input for DACs A and B.
REFINCD 10 I Voltage reference input for DACs C and D.
SCLK 5 I Serial clock input
OUTA 14 O DACA output
OUTB 13 O DACB output
OUTC 12 O DACC output
OUTD 11 O DACD output
I/O
16 Analog supply
1 Digital supply
7 I Frame sync input. The falling edge of the frame sync pulse indicates the start of a serial data frame shifted out to
the TLV5614.
2 I Power down pin. Powers down all DACs (overriding their individual power down settings), and all output stages.
This terminal is active low.
3 I Load DAC. When the LDAC signal is high, no DAC output updates occur when the input digital data is read into
the serial interface. The DAC outputs are only updated when LDAC
DESCRIPTION
is low.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, (DV
Supply voltage difference, (AV
Digital input voltage range –0.3 V to DV
Reference input voltage range –0.3 V to AV
Operating free-air temperature range, T
Storage temperature range, T
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
, AVDD to GND) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DD
to DVDD) –2.8 V to 2.8 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DD
: TLV5614C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A
TLV5614I –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
DD
DD
+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
TLV5614
2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188B – SEPTEMBER 1998 – REVISED APRIL 2003
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, AVDD, DV
High-level digital input voltage, V
Low-level digital input voltage, V
Reference voltage, V
Load resistance, R
Load capacitance, C
Serial clock rate, SCLK 20 MHz
Operating free-air temperature
NOTE 1: Voltages greater than AVDD/2 cause output saturation for large DAC codes.
DD
IH
IL
to REFINAB, REFINCD terminal
ref
L
L
electrical characteristics over recommended operating free-air temperature range, supply
voltages, and reference voltages (unless otherwise noted)
5-V supply 4.5 5 5.5
3-V supply 2.7 3 3.3
DVDD = 2.7 V 2
DVDD = 5.5 V 2.4
DVDD = 2.7 V 0.6
DVDD = 5.5 V 1
5-V supply, See Note 1 0 2.048 VDD–1.5
3-V supply, See Note 1 0 1.024 VDD–1.5
2 10 kΩ
100 pF
TLV5614C 0 70
TLV5614I –40 85
V
V
V
V
°C
static DAC specifications
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution 12 bits
Integral nonlinearity (INL), end point adjusted See Note 2 ±1.5 ±4 LSB
Differential nonlinearity (DNL) See Note 3 ±0.5 ±1 LSB
E
ZS
E
G
PSRR Power supply rejection ratio
NOTES: 2. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error , is the maximum deviation of the output
Zero scale error (offset error at zero scale) See Note 4 ±12 mV
Zero scale error temperature coefficient See Note 5 10 ppm/°C
min
% of FS
voltage
).
Gain error See Note 6 ±0.6
Gain error temperature coefficient See Note 7 10 ppm/°C
Zero scale
Full scale
from the line between zero and full scale excluding the effects of zero code and full-scale errors.
3. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal
1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains
constant) as a change in the digital input code.
4. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.
5. Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (T
6. Gain error is the deviation from the ideal output (2 V
7. Gain temperature coefficient is given by: EG TC = [EG(T
8. Zero-scale-error rejection ratio (EZS–RR) is measured by varying the AVDD from 5 ± 0.5 V and 3 ± 0.3 V dc, and measuring the
proportion of this signal imposed on the zero-code output voltage.
9. Full-scale rejection ratio (EG-RR) is measured by varying the AVDD from 5 ± 0.5 V and 3 ±0.3 V dc and measuring the proportion
of this signal imposed on the full-scale output voltage after subtracting the zero scale change.
See Notes 8 and 9
) – EZS (T
– 1 LSB) with an output load of 10 kΩ excluding the ef fects of the zero-error.
ref
max
) – EG (T
max
min
)]/V
× 106/(T
ref
min
)]/V
max
ref
– T
–80 dB
–80 dB
× 106/(T
min
max
).
– T
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5614
2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188B – SEPTEMBER 1998 – REVISED APRIL 2003
electrical characteristics over recommended operating free-air temperature range, supply
voltages, and reference voltages (unless otherwise noted) (continued)
individual DAC output specifications
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
O
reference inputs (REFINAB, REFINCD)
V
I
R
I
C
I
NOTES: 10. Reference input voltages greater than VDD/2 cause output saturation for large DAC codes.
Voltage output range RL = 10 kΩ 0 AVDD–0.4 V
Output load regulation accuracy RL = 2 kΩ vs 10 kΩ 0.1 0.25
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input voltage range See Note 10 0 AVDD–1.5 V
Input resistance 10 MΩ
Input capacitance 5 pF
Reference feed through
Reference input bandwidth REFIN = 0.2 Vpp + 1.024 V dc large signal
11. Reference feedthrough is measured at the DAC output with an input code = 000 hex and a V
input = 1.024 Vdc + 1 Vpp at 1 kHz.
REFIN = 1 Vpp at 1 kHz + 1.024 V dc
(see Note 11)
–75 dB
Slow 0.5
Fast 1
ref (REFINAB or REFINCD)
% of FS
voltage
MHz
digital inputs (DIN, CS, LDAC, PD)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I
IH
I
IL
C
I
High-level digital input current VI = V
Low-level digital input current VI = 0 V ±1 µA
Input capacitance 3 pF
power supply
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I
DD
Power supply current
Power down supply current (see Figure 12) 10 nA
DD
5-V supply,
No load, Clock running,
All inputs 0 V or V
3-V supply,
No load, Clock running,
All inputs 0 V or DV
DD
DD
±1 µA
Slow 1.6 2.4
Fast 3.8 5.6
Slow 1.2 1.8
Fast 3.2 4.8
mA
mA
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
TLV5614
To ± 0.5 LSB
C
L
100 F
To ± 0.5 LSB
C
L
100 F
,
f
= 400 KSPS
2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188B – SEPTEMBER 1998 – REVISED APRIL 2003
electrical characteristics over recommended operating free-air temperature range, supply
voltages, and reference voltages (unless otherwise noted) (continued)
analog output dynamic performance
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CL = 100 pF, RL = 10 kΩ,
SR Output slew rate
t
s
t
s(c)
SNR Signal-to-noise ratio
S/(N+D) Signal to noise + distortion
THD Total harmonic distortion
SFDR Spurious free dynamic range
NOTES: 12. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change
Output settling time
Output settling time, code to code
Glitch energy Code transition from 7FF to 800 10 nV-sec
ofFFF hex to 080 hex for 080 hex to FFF hex.
13. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change
of one count.
14. Limits are ensured by design and characterization, but are not production tested.
VO = 10% to 90%,
V
= 2.048 V, 1024 V
ref
To ± 0.5 LSB, C
RL = 10 kΩ, See Notes 12 and 14
To ± 0.5 LSB, C
RL = 10 kΩ, See Note 13
Sinewave generated by DAC,
Reference voltage = 1.024 at 3 V and 2.048 at 5 V ,
= 400 KSPS
f
s
f
= 1.1 kHz sinewave,
OUT
CL = 100 pF, RL = 10 kΩ,
BW = 20 kHz
= 100 pF,
,
=
= 100 pF,
,
=
,
p
,
,
Fast 5 V/µs
Slow 1 V/µs
Fast 3 5.5
Slow 9 20
Fast 1
Slow 2
74
66
–68
70
µs
µs
dB
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5614
2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188B – SEPTEMBER 1998 – REVISED APRIL 2003
electrical characteristics over recommended operating free-air temperature range, supply
voltages, and reference voltages (unless otherwise noted) (continued)
digital input timing requirements
MIN NOM MAX UNIT
t
su(CS–FS)
t
su(FS–CK)
t
su(C16–FS)
t
su(C16–CS)
t
wH
t
wL
t
su(D)
t
h(D)
t
wH(FS)
Setup time, CS low before FS↓ 10 ns
Setup time, FS low before first negative SCLK edge 8 ns
Setup time, sixteenth negative SCLK edge after FS low on which bit D0 is sampled before
rising edge of FS
Setup time. The first positive SCLK edge after D0 is sampled before CS rising edge. If FS
is used instead of the SCLK positive edge to update the DAC, then the setup time is between
the FS rising edge and CS rising edge.
Pulse duration, SCLK high 25 ns
Pulse duration, SCLK low 25 ns
Setup time, data ready before SCLK falling edge 8 ns
Hold time, data held valid after SCLK falling edge 5 ns
Pulse duration, FS high 20 ns
10 ns
10 ns
SCLK
DIN
CS
FS
t
su(D)
PARAMETER MEASUREMENT INFORMATION
t
wL
123451516
t
h(D)
D15 D14 D13 D12 D1 D0
t
su(FS-CK)
t
su(CS-FS)
t
wH(FS)
Figure 1. Timing Diagram
t
wH
t
t
su(C16-FS)
su(C16-CS)
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
TLV5614
2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188B – SEPTEMBER 1998 – REVISED APRIL 2003
TYPICAL CHARACTERISTICS
LOAD REGULATION
0.2
VDD = 3 V,
0.18
V
= 1 V,
ref
VO = Full Scale
0.16
0.14
0.12
0.10
– Output – V
0.08
O
V
0.06
0.04
0.02
0
0 0.01 0.02 0.05 0.1 0.2 0.5 1 20.8
3 V Slow Mode, Sink
3 V Fast Mode, Sink
Load Current – mA
Figure 2
LOAD REGULATION
4.01
5 V Slow Mode, Source
LOAD REGULATION
0.35
VDD = 5 V,
V
= 2 V,
0.30
0.25
0.20
– Output – V
0.15
O
V
0.10
0.05
ref
VO = Full Scale
0
0 0.02 0.04 0.1 0.2 0.4 1 2 40.8
Load Current – mA
Figure 3
LOAD REGULATION
2.0015
2.001
3 V Slow Mode, Source
5 V Slow Mode, Sink
5 V Fast Mode, Sink
4.005
4
– Output – V
3.995
O
V
3.99
3.985
0 0.02 0.04 0.1 0.2 0.4 1 2 40.8
5 V Fast Mode, Source
Load Current – mA
Figure 4
VDD = 5 V,
V
= 2 V,
ref
VO = Full Scale
2.0005
1.9995
– Output – V
1.9985
O
V
1.9975
1.9965
2.000
3 V Fast Mode, Source
1.999
1.998
1.997
0 0.01 0.02 0.05 0.1 0.2 0.5 1 20.8
Load Current – mA
Figure 5
VDD = 3 V,
V
= 1 V,
ref
VO = Full Scale
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5614
2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188B – SEPTEMBER 1998 – REVISED APRIL 2003
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
TEMPERATURE
4
VDD = 3 V,
V
= 1.024 V,
ref
VO Full Scale
(Worst Case For IDD)
3
2
1
–40 –20 0 20 40 60 80 100
Slow Mode
T – Temperature – °C
Fast Mode
– Supply Current – mA
DD
I
3.5
2.5
1.5
0.5
Figure 6
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
0
V
= 1 V dc + 1 V p/p Sinewave,
–10
ref
Output Full Scale
SUPPLY CURRENT
vs
TEMPERATURE
4
3.5
3
2.5
2
– Supply Current – mA
DD
1.5
I
1
0.5
–40 –20 0 20 40 60 80 100
Slow Mode
T – Temperature – °C
Fast Mode
VDD = 5 V,
V
= 1.024 V,
ref
VO Full Scale
(Worst Case For IDD)
Figure 7
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
0
V
= 1 V dc + 1 V p/p Sinewave,
–10
ref
Output Full Scale
THD – Total Harmonic Distortion – dB
–20
–30
––40
–50
–60
–70
–80
0 5 10 20
Fast Mode
30 50 100
f – Frequency – kHz
Figure 8
–20
–30
––40
–50
–60
THD – Total Harmonic Distortion – dB
–70
–80
0 5 10 20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Slow Mode
30 50 100
f – Frequency – kHz
Figure 9
9
TLV5614
2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188B – SEPTEMBER 1998 – REVISED APRIL 2003
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION AND NOISE
vs
FREQUENCY
0
V
= 1 V dc + 1 V p/p Sinewave,
ref
Output Full Scale
Fast Mode
0 5 10 20
f – Frequency – kHz
30 50 100
THD – Total Harmonic Distortion And Noise – dB
–10
–20
–30
––40
–50
–60
–70
–80
Figure 10
(WHEN ENTERING POWER-DOWN MODE)
4000
–10
–20
–30
––40
–50
–60
–70
THD – Total Harmonic Distortion And Noise – dB
–80
SUPPLY CURRENT
vs
TIME
TOTAL HARMONIC DISTORTION AND NOISE
vs
FREQUENCY
0
V
= 1 V dc + 1 V p/p Sinewave,
ref
Output Full Scale
Slow Mode
0 5 10 20
f – Frequency – kHz
30 50 100
Figure 11
3500
3000
Aµ
2500
2000
1500
– Supply Current –
DD
1000
I
500
0
0 200 400 600
800 1000
t – Time – ns
Figure 12
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5614
2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188B – SEPTEMBER 1998 – REVISED APRIL 2003
TYPICAL CHARACTERISTICS
DIFFERENTIAL NONLINEARITY
0.3
VCC = 5 V, V
0.25
0.2
0.15
0.1
0.05
0
–0.05
–0.1
–0.15
–0.2
–0.25
–0.3
0 256 768 1280 1536 2048 2560
DNL – Differential Nonlinearity – LSB
1
VCC = 5 V, V
SCLK = 1 MHz
0.5
512 1024 1792 2304 3072 3584
= 2 V, SCLK = 1 MHz)
ref
= 2 V,
ref
Digital Code
Figure 13
INTEGRAL NONLINEARITY
2816 3328 3840
4096
0
–0.5
–1
–1.5
INL – Integral Nonlinearity – LSB
0 256 768 1280 1536 2048 2560
512 1024 1792 2304 3072 3584
Digital Code
Figure 14
2816 3328 3840
4096
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
11
TLV5614
2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188B – SEPTEMBER 1998 – REVISED APRIL 2003
APPLICATION INFORMATION
general function
The TL V5614 is a 12-bit single supply DAC based on a resistor string architecture. The device consists of a serial
interface, speed and power down control logic, a reference input buffer , a resistor string, and a rail-to-rail output
buffer.
The output voltage (full scale determined by external reference) is given by:
2REF
CODE
where REF is the reference voltage and CODE is the digital input value within the range of 0
[V]
n
2
to 2n–1, where
10
n=12 (bits). The 16-bit data word, consisting of control bits and the new DAC value, is illustrated in the data
format section. A power-on reset initially resets the internal latches to a defined state (all bits zero).
serial interface
Explanation of data transfer: First, the device has to be enabled with CS set to low . Then, a falling edge of FS
starts shifting the data bit-per-bit (starting with the MSB) to the internal register on the falling edges of SCLK.
After 16 bits have been transferred or FS rises, the content of the shift register is moved to the DAC latch which
updates the voltage output to the new level.
The serial interface of the TLV5614 can be used in two basic modes:
D Four wire (with chip select)
D Three wire (without chip select)
Using chip select (four wire mode), it is possible to have more than one device connected to the serial port of
the data source (DSP or microcontroller). The interface is compatible with the TMS320 DSP family. Figure
15 shows an example with two TLV5614s connected directly to a TMS320 DSP.
TLV5614
CS
FS DIN SCLK
TLV5614
CS
FS DIN SCLK
TMS320
DSP
XF0
XF1
FSX
DX
CLKX
TMS320 is a trademark of Texas Instruments.
12
Figure 15. TMS320 Interface
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188B – SEPTEMBER 1998 – REVISED APRIL 2003
APPLICATION INFORMATION
serial interface (continued)
If there is no need to have more than one device on the serial bus, then CS can be tied low. Figure 16 shows
an example of how to connect the TLV5614 to a TMS320, SPI, or Microwire port using only three pins.
TLV5614
TMS320
DSP
FSX
DX
CLKX
TLV5614
FS
DIN
SCLK
CS
SPI
SS
MOSI
SCLK
TLV5614
FS
DIN
SCLK
CS
Microwire
I/O
SO
SK
TLV5614
FS
DIN
SCLK
CS
Figure 16. Three-Wire Interface
Notes on SPI and Microwire: Before the controller starts the data transfer, the software has to generate a falling
edge on the I/O pin connected to FS. If the word width is 8 bits (SPI and Microwire), two write operations must
be performed to program the TLV5614. After the write operation(s), the DAC output is updated automatically
on the next positive clock edge following the sixteenth falling clock edge.
serial clock frequency and update rate
The maximum serial clock frequency is given by:
f
SCLKmax
+
t
wH(min)
The maximum update rate is:
f
UPDATEmax
+
16
ǒ
1
) t
wL(min)
t
wH(min)
1
) t
+ 20 MHz
wL(min)
Ǔ
+ 1.25 MHz
Note that the maximum update rate is a theoretical value for the serial interface since the settling time of the
TLV5614 has to be considered also.
data format
The 16-bit data word for the TLV5614 consists of two parts:
D Control bits (D15 . . . D12)
D New DAC value (D11 ...D0)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
A1 A0 PWR SPD New DAC value (12 bits)
X: don’t care
SPD: Speed control bit. 1 → fast mode 0 → slow mode
PWR: Power control bit. 1 → power down 0 → normal operation
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
13
TLV5614
2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188B – SEPTEMBER 1998 – REVISED APRIL 2003
APPLICATION INFORMATION
In power-down mode, all amplifiers within the TLV5614 are disabled. A particular DAC (A, B, C, D) of the
TLV5614 is selected by A1 and A0 within the input word.
A1 A0 DAC
0 0 A
0 1 B
1 0 C
1 1 D
Using TLV5614IYE, Bumped Dice
D Melting point of eutectic solder is 183°C.
D Recommended peak reflow temperatures are in the 220°C to 230°C range.
D The use of underfill is required. The use of underfill greatly reduces the risk of thermal mismatch fails.
Underfill is an epoxy/adhesive that may be added during the board assembly process to improve board
level/system level reliability. The process is to dispense the epoxy under the dice after die attach reflow. The
epoxy adheres to the body of the device and to the printed-circuit board. It reduces stress placed upon the solder
joints due to the thermal coefficient of expansion (TCE) mismatch between the board and the component.
Underfill material is highly filled with silica or other fillers to increase an epoxy’s modulus, reduce creep
sensitivity, and decrease the material’s TCE.
The recommendation for peak flow temperatures of 220°C to 230°C is based on general empirical results that
indicate that this temperature range is needed to facilitate good wetting of the solder bump to the substrate or
circuit board pad. Lower peak temperatures may cause nonwets (cold solder joints).
NOTE A: All linear dimensions are in millimeters.
NOTE B: This drawing is subject to change without notice.
NOTE C: Scale = 18x
14
Figure 17. TLV5614IYE Bumped Dice
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188B – SEPTEMBER 1998 – REVISED APRIL 2003
TLV5614 interfaced to TMS320C203 DSP
hardware interfacing
Figure 17 shows an example of how to connect the TLV5614 to a TMS320C203 DSP. The serial port is
configured in burst mode, with FSX generated by the TMS320C203 to provide the frame sync (FS) input to the
TL V5614. Data is transmitted on the DX line, with the serial clock input on the CLKX line. The general-purpose
input/output port bits IO0 and IO1 are used to generate the chip select (CS
to the TLV5614. The active low power down (PD
TMS320C203
) is pulled high all the time to ensure the DACs are enabled.
TLV5614
) and DAC latch update (LDAC) inputs
TLV5614
DX
CLKX
FSX
I/O 0
I/O 1
REF
SDIN
SCLK
FS
CS
LDAC
REFINAB
REFINCD
V
DD
PD
VOUTA
VOUTB
VOUTC
VOUTD
V
SS
Figure 18. TL V5614 Interfaced With TMS320C203
software
The application example outputs a differential in-phase (sine) signal between the VOUT A and VOUTB pins, and
its quadrature (cosine) signal as the differential signal between VOUTC and VOUTD.
The on-chip timer is used to generate interrupts at a fixed frequency . The related interrupt service routine pulses
low to update all 4 DACs simultaneously, then fetches and writes the next sample to all 4 DACs. The
LDAC
samples are stored in a look-up table, which describes two full periods of a sine wave.
The synchronous serial port of the DSP is used in burst mode. In this mode, the processor generates an FS
pulse preceding the MSB of every data word. If multiple, contiguous words are transmitted, a violation of the
tsu(C16–FS) timing requirement occurs. T o avoid this, the program waits until the transmission of the previous
word has been completed.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
15
TLV5614
2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188B – SEPTEMBER 1998 – REVISED APRIL 2003
APPLICATION INFORMATION
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; Processor: TMS320C203 runnning at 40 MHz
;
; Description:
;
; This program generates a differential in–phase (sine) on (OUTA–OUTB) and it’s
; quadrature (cosine) as a differential signal on (OUTC–OUTD).
;
; The DAC codes for the signal samples are stored as a table of 64 12–bit values,
; describing 2 periods of a sine function. A rolling pointer is used to address the
; table location in the first period of this waveform, from which the DAC A samples
; are read. The samples for the other 3 DACs are read at an offset to this rolling
; pointer:
; DAC Function Offset from rolling pointer
; A sine 0
; B inverse sine 16
; C cosine 8
; D inverse cosine24
;
; The on–chip timer is used to generate interrupts at a fixed rate. The interrupt
; service routine first pulses LDAC low to update all DACs simultaneously
; with the values which were written to them in the previous interrupt. Then all
; 4 DAC values are fetched and written out through the synchronous serial interface
; Finally, the rolling pointer is incremented to address the next sample, ready for
; the next interrupt.
;
; 1998, Texas Instruments Inc.
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
;–––––––––––––––––––––––––––––– I/O and memory mapped regs –––––––––––––––––––––––––––––
;–––––––jump vectors –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
––––––––––– variables –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
temp .equ 0060h
r_ptr .equ 0061h
iosr_stat .equ 0062h
DACa_ptr .equ 0063h
DACb_ptr .equ 0064h
DACc_ptr .equ 0065h
DACd_ptr .equ 0066h
;–––––––––––constants––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; DAC control bits to be OR’ed onto data
; all fast mode
DACa_control .equ 01000h
DACb_control .equ 05000h
DACc_control .equ 09000h
DACd_control .equ 0d000h
;––––––––––– tables ––––––––––––––––––––––––––––––––
sinevals
.include ”regs.asm”
.ps 0h
b start
b int1
b int23
b timer_isr;
.ds 02000h
.word 00800h
.word 0097Ch
.word 00AE9h
.word 00C3Ah
.word 00D61h
.word 00E53h
.word 00F07h
.word 00F76h
.word 00F9Ch
.word 00F76h
.word 00F07h
.word 00E53h
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
.word 00D61h
.word 00C3Ah
.word 00AE9h
.word 0097Ch
.word 00800h
.word 00684h
.word 00517h
.word 003C6h
.word 0029Fh
.word 001ADh
.word 000F9h
.word 0008Ah
.word 00064h
.word 0008Ah
.word 000F9h
.word 001ADh
.word 0029Fh
.word 003C6h
.word 00517h
.word 00684h
.word 00800h
.word 0097Ch
.word 00AE9h
.word 00C3Ah
.word 00D61h
.word 00E53h
.word 00F07h
.word 00F76h
.word 00F9Ch
.word 00F76h
.word 00F07h
.word 00E53h
.word 00D61h
.word 00C3Ah
.word 00AE9h
.word 0097Ch
.word 00800h
.word 00684h
.word 00517h
.word 003C6h
.word 0029Fh
.word 001ADh
.word 000F9h
.word 0008Ah
.word 00064h
.word 0008Ah
.word 000F9h
.word 001ADh
.word 0029Fh
.word 003C6h
.word 00517h
.word 00684h
TLV5614
WITH POWER DOWN
SLAS188B – SEPTEMBER 1998 – REVISED APRIL 2003
APPLICATION INFORMATION
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
17
TLV5614
2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188B – SEPTEMBER 1998 – REVISED APRIL 2003
APPLICATION INFORMATION
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; Main Program
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
start
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; disable interrupts
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; set up the timer
; timer period set by values in PRD and TDDR
; period = (CLKOUT1 period) x (1+PRD) x (1+TDDR)
; examples for TMS320C203 with 40MHz main clock
; Timer rate TDDR PRD
; 80 kHz 9 24 (18h)
; 50 kHz 9 39 (27h)
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
prd_val.equ 0018h
tcr_val.equ 0029h
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; Configure IO0/1 as outputs to be :
; IO0 CS – and set high
; IO1 LDAC – and set high
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; set up serial port for
; SSPCR.TXM=1 Transmit mode – generate FSX
; SSPCR.MCM=1 Clock mode – internal clock source
; SSPCR.FSM=1 Burst mode
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; reset the rolling pointer
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; enable interrupts
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; loop forever!
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
.ps 1000h
.entry
setc INTM ; disable maskable interrupts
splk #0ffffh, IFR; clear all interrupts
splk #0004h, IMR; timer interrupts unmasked
splk #0000h, temp; clear timer
out temp, TIM
splk #prd_val, temp; set PRD
out temp, PRD
splk #tcr_val, temp; set TDDR, and TRB=1 for auto–reload
out temp, TCR
in temp, ASPCR; configure as output
lacl temp
or #0003h
sacl temp
out temp, ASPCR
in temp, IOSR; set them high
lacl temp
or #0003h
sacl temp
out temp, IOSR
splk #0000Eh, temp
out temp, SSPCR; reset transmitter
splk #0002Eh, temp
out temp,SSPCR
lacl #000h
sacl r_ptr
clrc INTM ; enable maskable interrupts
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5614
2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188B – SEPTEMBER 1998 – REVISED APRIL 2003
APPLICATION INFORMATION
next idle ;wait for interrupt
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; all else fails stop here
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
done b done ;hang there
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; Interrupt Service Routines
;––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
int1 ret ; do nothing and return
int23 ret ; do nothing and return
timer_isr:
b next
in iosr_stat, IOSR; store IOSR value into variable space
lacl iosr_stat ; load acc with iosr status
and #0FFFDh ; reset IO1 – LDAC low
sacl temp ;
out temp, IOSR ;
or #0002h ; set IO1 – LDAC high
sacl temp ;
out temp, IOSR ;
and #0FFFEh ; reset IO0 – CS low
sacl temp ;
out temp, IOSR ;
lacl r_ptr ; load rolling pointer to accumulator
add #sinevals ; add pointer to table start
sacl DACa_ptr ; to get a pointer for next DAC a sample
add #08h ; add 8 to get to DAC C pointer
sacl DACc_ptr
add #08h ; add 8 to get to DAC B pointer
sacl DACb_ptr
add #08h ; add 8 to get to DAC D pointer
sacl DACd_ptr
mar *,ar0 ; set ar0 as current AR
; DAC A
lar ar0, DACa_ptr ; ar0 points to DAC a sample
lacl * ; get DAC a sample into accumulator
or #DACa_control ; OR in DAC A control bits
sacl temp ;
out temp, SDTR ; send data
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; We must wait for transmission to complete before writing next word to the SDTR.;
TLV5614/04 interface does not allow the use of burst mode with the full packet; rate, as
we need a CLKX –ve edge to clock in last bit before FS goes high again,; to allow SPI
compatibility.
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
rpt #016h ; wait long enough for this configuration
nop ; of MCLK/CLKOUT1 rate
; DAC B
lar ar0, dacb_ptr ; ar0 points to DAC a sample
lacl * ; get DAC a sample into accumulator
or #DACb_control ; OR in DAC B control bits
sacl temp ;
out temp, SDTR ; send data
rpt #016h ; wait long enough for this configuration
nop ; of MCLK/CLKOUT1 rate
; DAC C
lar ar0, dacc_ptr ; ar0 points to dac a sample
lacl * ; get DAC a sample into accumulator
or #DACc_control ; OR in DAC C control bits
sacl temp ;
out temp, SDTR; send data
rpt #016h ; wait long enough for this configuration
nop ; of MCLK/CLKOUT1 rate
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
19
TLV5614
2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188B – SEPTEMBER 1998 – REVISED APRIL 2003
APPLICATION INFORMATION
; DAC D
lar ar0, dacd_ptr; ar0 points to DAC a sample
lacl * ; get DAC a sample into accumulator
or #dacd_control ; OR in DAC D control bits
sacl temp ;
out temp, SDTR ; send data
lacl r_ptr ; load rolling pointer to accumulator
add #1h ; increment rolling pointer
and #001Fh ; count 0–31 then wrap back round
sacl r_ptr ; store rolling pointer
rpt #016h ; wait long enough for this configuration
nop ; of MCLK/CLKOUT1 rate
; now take CS high again
lacl iosr_stat ; load acc with iosr status
or #0001h ; set IO0 – CS high
sacl temp ;
out temp, IOSR ;
clrc intm ; re-enable interrupts
ret ; return from interrupt
.end
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5614
®
2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188B – SEPTEMBER 1998 – REVISED APRIL 2003
APPLICATION INFORMATION
TLV5614 interfaced to MCS
51 microcontroller
hardware interfacing
Figure 18 shows an example of how to connect the TLV5614 to an MCS
51 Microcontroller. The serial DAC
input data and external control signals are sent via I/O Port 3 of the controller. The serial data is sent on the RxD
line, with the serial clock output on the TxD line. Port 3 bits 3, 4, and 5 are configured as outputs to provide the
DAC latch update (LDAC
down pin (PD
) of the TLV5614 is pulled high to ensure that the DACs are enabled.
), chip select (CS) and frame sync (FS) signals for the TL V5614. The active low power
MCS
51
RxD
TxD
P3.3
P3.4
P3.4
REF
TLV5614
SDIN
SCLK
LDAC
CS
FS
REFINAB
REFINCD
V
DD
PD
VOUTA
VOUTB
VOUTC
VOUTD
V
SS
Figure 19. TLV5614 Interfaced With MCS51
software
The example is the same as for the TMS320C203 in this data sheet, but adapted for a MCS
51 controller. It
generates a differential in-phase (sine) signal between the VOUT A and VOUTB pins, and its quadrature (cosine)
signal is the differential signal between VOUTC and VOUTD.
The on-chip timer is used to generate interrupts at a fixed frequency . The related interrupt service routine pulses
LDAC
low to update all 4 DACs simultaneously, then fetches and writes the next sample to all 4 DACs. The
samples are stored as a look-up table, which describes one full period of a sine wave.
The serial port of the controller is used in Mode 0, which transmits 8 bits of data on RxD, accompanied by a
synchronous clock on TxD. Two writes concatenated together are required to write a complete word to the
TL V5614. The CS
and FS signals are provided in the required fashion through control of IO port 3, which has
bit addressable outputs.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
21
TLV5614
2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188B – SEPTEMBER 1998 – REVISED APRIL 2003
APPLICATION INFORMATION
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; Processor: 80C51
;
; Description:
;
; This program generates a differential in-phase
(sine) on (OUTA–OUTB) ; and it’s quadrature (cosine)
as a differential signal on (OUTC–OUTD).
;
; 1998, Texas Instruments Inc.
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
NAME GENIQ
MAIN SEGMENT CODE
ISR SEGMENT CODE
SINTBL SEGMENT CODE
VAR1 SEGMENT DATA
STACK SEGMENT IDATA
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; Code start at address 0, jump to start
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
CSEG AT 0
LJMP start ; Execution starts at address 0 on power–up.
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; Code in the timer0 interrupt vector
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
CSEG AT 0BH
LJMP timer0isr ; Jump vector for timer 0 interrupt is 000Bh
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; Global variables need space allocated
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
RSEG VAR1
temp_ptr: DS 1
rolling_ptr: DS 1
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––;
Interrupt service routine for timer 0 interrupts
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
RSEG ISR
timer0isr:
PUSH PSW
PUSH ACC
CLR INT1 ; pulse LDAC low
SETB INT1 ; to latch all 4 previous values at the same time
CLR T0 ; set CS low
; 1st thing done in timer isr => fixed period
22
; The signal to be output on each DAC is a sine function.
; One cycle of a sine wave is held in a table @ sinevals
; as 32 samples of msb, lsb pairs (64 bytes).
; We have ; one pointer which rolls round this table, rolling_ptr,
; incrementing by 2 bytes (1 sample) on each interrupt (at the end of
; this routine).
; The DAC samples are read at an offset to this rolling pointer:
; DAC Function Offset from rolling_ptr
; A sine 0
; B inverse sine 32
; C cosine 16
; D inverse cosine48
MOV DPTR,#sinevals; set DPTR to the start of the table
; of sine signal values
MOV R7,rolling_ptr; R7 holds the pointer
;into the sine table
MOV A,R7 ; get DAC A msb
MOVC A,@A+DPTR ; msb of DAC A is in the ACC
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
SLAS188B – SEPTEMBER 1998 – REVISED APRIL 2003
APPLICATION INFORMATION
CLR T1 ; transmit it – set FS low
MOV SBUF,A ; send it out the serial port
INC R7 ; increment the pointer in R7
MOV A,R7 ; to get the next byte from the table
MOVC A,@A+DPTR ; which is the lsb of this sample, now in ACC
A_MSB_TX:
JNB TI,A_MSB_TX ; wait for transmit to complete
CLR TI ; clear for new transmit
MOV SBUF,A ; and send out the lsb of DAC A
; DAC C next
; DAC C codes should be taken from 16 bytes (8 samples) further on
; in the sine table – this gives a cosine function
MOV A,R7 ; pointer in R7
ADD A,#0FH ; add 15 – already done one INC
ANL A,#03FH ; wrap back round to 0 if > 64
MOV R7,A ; pointer back in R7
MOVC A,@A+DPTR ; get DAC C msb from the table
ORL A,#01H ; set control bits to DAC C address
A_LSB_TX:
JNB TI,A_LSB_TX ; wait for DAC A lsb transmit to complete
SETB T1 ; toggle FS
CLR T1
CLR TI ; clear for new transmit
MOV SBUF,A ; and send out the msb of DAC C
INC R7 ; increment the pointer in R7
MOV A,R7 ; to get the next byte from the table
MOVC A,@A+DPTR ; which is the lsb of this sample, now in ACC
C_MSB_TX:
JNB TI,C_MSB_TX ; wait for transmit to complete
CLR TI ; clear for new transmit
MOV SBUF,A ; and send out the lsb of DAC C
TLV5614
WITH POWER DOWN
; DAC B next
; DAC B codes should be taken from 16 bytes (8 samples) further on
; in the sine table – this gives an inverted sine function
MOV A,R7 ; pointer in R7
ADD A,#0FH ; add 15 – already done one INC
ANL A,#03FH ; wrap back round to 0 if > 64
MOV R7,A ; pointer back in R7
MOVC A,@A+DPTR ; get DAC B msb from the table
ORL A,#02H ; set control bits to DAC B address
C_LSB_TX:
JNB TI,C_LSB_TX ; wait for DAC C lsb transmit to complete
SETB T1 ; toggle FS
CLR T1
CLR TI ; clear for new transmit
MOV SBUF,A ; and send out the msb of DAC B
; get DAC B LSB
INC R7 ; increment the pointer in R7
MOV A,R7 ; to get the next byte from the table
MOVC A,@A+DPTR ; which is the lsb of this sample, now in ACC
B_MSB_TX:
JNB TI,B_MSB_TX ; wait for transmit to complete
CLR TI ; clear for new transmit
MOV SBUF,A ; and send out the lsb of DAC B
; DAC D next
; DAC D codes should be taken from 16 bytes (8 samples) further on
; in the sine table – this gives an inverted cosine function
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
23
TLV5614
2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188B – SEPTEMBER 1998 – REVISED APRIL 2003
APPLICATION INFORMATION
MOV A,R7 ; pointer in R7
ADD A,#0FH ; add 15 – already done one INC
ANL A,#03FH ; wrap back round to 0 if > 64
MOV R7,A ; pointer back in R7
MOVC A,@A+DPTR ; get DAC D msb from the table
ORL A,#03H ; set control bits to DAC D address
B_LSB_TX:
JNB TI,B_LSB_TX ; wait for DAC B lsb transmit to complete
SETB T1 ; toggle FS
CLR T1
CLR TI ; clear for new transmit
MOV SBUF,A ; and send out the msb of DAC D
INC R7 ; increment the pointer in R7
MOV A,R7 ; to get the next byte from the table
MOVC A,@A+DPTR ; which is the lsb of this sample, now in ACC
D_MSB_TX:
JNB TI,D_MSB_TX ; wait for transmit to complete
CLR TI ; clear for new transmit
MOV SBUF,A ; and send out the lsb of DAC D
; increment the rolling pointer to point to the next sample
; ready for the next interrupt
MOV A,rolling_ptr
ADD A,#02H ; add 2 to the rolling pointer
ANL A,#03FH ; wrap back round to 0 if > 64
MOV rolling_ptr,A ; store in memory again
D_LSB_TX:
JNB TI,D_LSB_TX ; wait for DAC D lsb transmit to complete
CLR TI ; clear for next transmit
SETB T1 ; FS high
SETB T0 ; CS high
POP ACC
POP PSW
RETI
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; Stack needs definition
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
RSEG STACK
DS 10h ; 16 Byte Stack!
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; Main program code
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
RSEG MAIN
start:
MOV SP,#STACK–1 ; first set Stack Pointer
CLR A
MOV SCON,A ; set serial port 0 to mode 0
MOV TMOD,#02H ; set timer 0 to mode 2 – auto–reload
MOV TH0,#038H ; set TH0 for 5kHs interrupts
SETB INT1 ; set LDAC = 1
SETB T1 ; set FS = 1
SETB T0 ; set CS = 1
SETB ET0 ; enable timer 0 interrupts
SETB EA ; enable all interrupts
MOV rolling_ptr,A ; set rolling pointer to 0
SETB TR0 ; start timer 0
always:
SJMP always ; while(1) !
RET
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; Table of 32 sine wave samples used as DAC data
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
RSEG SINTBL
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
sinevals:
DW 01000H
DW 0903EH
DW 05097H
DW 0305CH
DW 0B086H
DW 070CAH
DW 0F0E0H
DW 0F06EH
DW 0F039H
DW 0F06EH
DW 0F0E0H
DW 070CAH
DW 0B086H
DW 0305CH
DW 05097H
DW 0903EH
DW 01000H
DW 06021H
DW 0A0E8H
DW 0C063H
DW 040F9H
DW 080B5H
DW 0009FH
DW 00051H
DW 00026H
DW 00051H
DW 0009FH
DW 080B5H
DW 040F9H
DW 0C063H
DW 0A0E8H
DW 06021H
END
TLV5614
2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188B – SEPTEMBER 1998 – REVISED APRIL 2003
APPLICATION INFORMATION
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
25
TLV5614
2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188B – SEPTEMBER 1998 – REVISED APRIL 2003
MECHANICAL DATA
D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0.050 (1,27)
14
1
0.069 (1,75) MAX
0.020 (0,51)
0.014 (0,35)
8
7
A
0.010 (0,25)
0.004 (0,10)
DIM
0.157 (4,00)
0.150 (3,81)
PINS **
0.010 (0,25)
0.244 (6,20)
0.228 (5,80)
8
M
Seating Plane
0.004 (0,10)
14
0.008 (0,20) NOM
0°–ā8°
16
Gage Plane
0.010 (0,25)
0.044 (1,12)
0.016 (0,40)
A MAX
A MIN
NOTES: D. All linear dimensions are in inches (millimeters).
26
E. This drawing is subject to change without notice.
F. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
G. Falls within JEDEC MS-012
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
0.197
(5,00)
0.189
(4,80)
0.344
(8,75)
0.337
(8,55)
0.394
(10,00)
0.386
(9,80)
4040047/D 10/96
TLV5614
2.7-V TO 5.5-V 12-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188B – SEPTEMBER 1998 – REVISED APRIL 2003
MECHANICAL DATA
PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0,65
14
1
1,20 MAX
0,30
0,19
8
6,60
4,50
4,30
6,20
7
A
0,15
0,05
M
0,10
Seating Plane
0,10
0,15 NOM
Gage Plane
0,25
0°–ā8°
0,75
0,50
PINS **
DIM
A MAX
A MIN
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
8
3,10
2,90
14
5,10
4,90
16
5,10
20
6,60
6,404,90
24
7,90
7,70
28
9,80
9,60
4040064/E 08/96
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
27
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty . Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty . Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. T o minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third–party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party , or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright 2003, Texas Instruments Incorporated
Loading...