Texas Instruments TLV5613IPWR, TLV5613IPW, TLV5613IDW, TLV5613CPWR, TLV5613CPW Datasheet

TLV5613

2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER
WITH POWER DOWN

SLAS174A – DECEMBER 1997 – REVISED JUL Y 1998

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

12-Bit Voltage Output DAC

D

Single Supply 2.7-V to 5.5-V Operation

D

Separate Analog and Digital Supplies

D

±0.4 LSB Differential Nonlinearity (DNL),
±1.5 LSB Integral Nonlinearity (INL)

D

Programmable Settling Time vs Power
Consumption:

1 µs/4.2 mW in Fast Mode,

3.5 µs/1.2 mW in Slow Mode

D

8-Bit µController Compatible Interface (8+4
Bit)

D

Power-Down Mode (50 nW)

D

Rail-to-Rail Output Buffer

D

Synchronous or Asynchronous Update

D

Monotonic Over Temperature

applications

D

Digital Servo Control Loops

D

Battery Powered Test Instruments

D

Digital Offset and Gain Adjustment

D

Industrial Process Control

D

Speech Synthesis

D

Machine and Motion Control Devices

D

Mass Storage Devices

description

The TLV5613 is a 12-bit voltage output
digital-to-analog converter (DAC) with a 8-bit
microcontroller compatible parallel interface. The
8 LSBs, the 4 MSBs and 3 control bits are written
using three different addresses. Developed for a
wide range of supply voltages, the TLV5613 can
be operated from 2.7 V to 5.5 V.

The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer . The buffer features a Class A
(slow mode: AB) output stage to improve stability and reduce settling time. The programmable settling time of
the DAC allows the designer to optimize speed versus power dissipation. The settling time can be chosen by
the control bits within the 16-bit data word.

Implemented with a CMOS process, the device is designed for single supply operation from 2.7 V to 5.5 V. It
is available in 20 pin SOIC in standard commercial and industrial temperature ranges.

AVAILABLE OPTIONS

PACKAGE

T

A

SMALL OUTLINE

(DW)

TSSOP

(PW)

0°C to 70°C TLV5613CDW TLV5613CPW

–40°C to 85°C TLV5613IDW TLV5613IPW

Copyright  1998, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

1
2
3
4
5
6
7
8
9
10

20
19
18
17
16
15
14
13
12
11

D2
D3
D4
D5
D6
D7
A1
A0

SPD

DV

DD

D1
D0
CS
WE
LDAC
PWD
GND
OUT
REF
AV

DD

DW OR PW PACKAGE

(TOP VIEW)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TLV5613

2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER
WITH POWER DOWN

SLAS174A – DECEMBER 1997 – REVISED JUL Y 1998

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

Interface

Control

4-Bit

DAC MSW

Holding

Latch

A(0–1)

CS

WE

OUT

Power-On

Reset

x2

4

3-Bit

Control

Latch

3

Powerdown

and Speed

Control

2

12-Bit

DAC

Latch

12 12

REF

LDAC

2

8-Bit

DAC LSW

Holding

Latch

8 8

4

D(0–7)

PWD

SPD

8

Terminal Functions

TERMINAL

NAME NO.

I/O

DESCRIPTION

AV

DD

11 Analog positive power supply
A0 8 I Address input
A1 7 I Address input
CS 18 I Chip select. Digital input active low, used to enable/disable inputs
DV

DD

10 Digital positive power supply
D0 (LSB) – D7 (MSB) 1–6, 19, 20 I Data input
LDAC 16 I Load DAC. Digital input active low, used to load DAC output
OUT 13 O DAC analog voltage output

PWD 15 I Power down. Digital input active low
REF 12 I Analog reference voltage input
SPD 9 I Speed select. Digital input
GND 14 Ground

WE 17 I Write enable. Digital input active low, used to latch data

TLV5613

2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER
WITH POWER DOWN

SLAS174A – DECEMBER 1997 – REVISED JUL Y 1998

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage (DV

DD

, AVDD to GND) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Supply voltage difference, AVDD to DVDD – 2.8 V to 2.8 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference input voltage range – 0.3 V to AVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital input voltage range to GND – 0.3 V to DVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, TA: TLV5613C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TLV5613I –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

MIN NOM MAX UNIT

pp

5-V Supply 4.5 5 5.5

Suppl

y v

oltage, V

DD

3-V Supply 2.7 3 3.3

V

Supply voltage difference, ∆VDD = AVDD – DV

DD

–2.8 0 2.8 V
Power on reset, POR 0.55 2 V
High-level digital input voltage, V

IH

DVDD = 2.7 V to 5.5 V 2 V

Low-level digital input voltage, V

IL

DVDD = 2.7 V to 5.5 V 0.8 V
5-V Supply (see Note 1) GND 2.048 AVDD–1.5

Reference voltage, V

ref

to

REFIN terminal

3-V Supply (see Note 1) GND 1.024 AVDD–1.5

V

Load resistance, R

L

2 kΩ

Load capacitance, C

L

100 pF

p

p

TLV5613C 0 70 °C

Operating free-air temperature, T

A

TLV5613I –40 85 °C

NOTE 1: Due to the x2 output buffer, a reference input voltage ≥ (VDD – 0.4)/2 causes clipping of the transfer function.

TLV5613

2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER
WITH POWER DOWN

SLAS174A – DECEMBER 1997 – REVISED JUL Y 1998

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range, supply
voltages, and reference voltages (unless otherwise noted)

power supply

PARAMETER TEST CONDITIONS MIN TYP MAX

UNIT

Fast 1.6 3 mA

pp

No load,

p

V

DD

= 5

V

Slow 0.5 1.3 mA

IDDPower supply current

All inputs

=

GND or DV

DD

,

DAC latch = 0x800

Fast 1.4 2.7 mA

V

DD

= 3

V

Slow 0.4 1.1 mA

Power down supply current See Figure 14 0.01 10 µA

pp

Zero scale, See Note 2 –65

PSRR

Power supply rejection ratio

Full scale, See Note 3 –65

dB

NOTES: 2. Power supply rejection ratio at zero scale is measured by varying AVDD and is given by:

PSRR = 20 log [(EZS(AVDDmax) – EZS(AVDDmin))/AVDDmax]

3. Power supply rejection ratio at full scale is measured by varying AVDD and is given by:
PSRR = 20 log [(EG(AVDDmax) – EG(AVDDmin))/AVDDmax]

static DAC specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Resolution V

ref(REFIN)

= 2.048 V , 1.024 V 12 bits

Integral nonlinearity (INL), end point adjusted V

ref(REFIN)

= 2.048 V , 1.024 V, See Note 4 ±1.5 ±4 LSB

Differential nonlinearity (DNL) V

ref(REFIN)

= 2.048 V , 1.024 V, See Note 5 ±0.4 ±1 LSB

E

ZS

Zero-scale error (offset error at zero scale) V

ref(REFIN)

= 2.048 V , 1.024 V, See Note 6 ±3 ±20 mV

Zero-scale-error temperature coefficient V

ref(REFIN)

= 2.048 V , 1.024 V, See Note 7 3 ppm/°C

E

G

Gain error V

ref(REFIN)

= 2.048 V , 1.024 V, See Note 8 ±0.25 ±0.5

% of FS

voltage

Gain error temperature coefficient V

ref(REFIN)

= 2.048 V , 1.024 V, See Note 9 1 ppm/°C

NOTES: 4. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error , is the maximum deviation of the output

from the line between zero and full scale excluding the effects of zero code and full-scale errors.

5. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1

LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains
constant) as a change in the digital input code.

6. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.

7. Zero-scale-error temperature coef ficient is given by: EZSTC = [EZS(T

max

) – EZS(T

min

)]/V

ref

× 106/(T

max

– T

min

).

8. Gain error is the deviation from the ideal output (V

ref

– 1 LSB) with an output load of 10 kΩ excluding the effects of the zero-error.

9. Gain temperature coefficient is given by: EGTC = [EG(T

max

) – EG (T

min

)]/V

ref

× 106/(T

max

– T

min

).

output specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

O

Output voltage RL = 10 kΩ 0 AVDD–0.4 V
Output load regulation accuracy

V

O(OUT)

= 4.096 V , RL = 2 kΩ,

0.1 0.29

% of FS

voltage

p

p

AVDD = 5 V –100

I

OSC(

source

)

Out ut short circuit source current

V

O(OUT)

= 0 V,

in ut all 1s

AVDD = 3 V –25

mA

p

p

AVDD = 5 V –10

I

OSC(sink)

Out ut short circuit sink current

R

L

=

100 Ω, in ut all 1s

AVDD = 3 V –10

mA

TLV5613

2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER
WITH POWER DOWN

SLAS174A – DECEMBER 1997 – REVISED JUL Y 1998

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range, supply
voltages, and reference voltages (unless otherwise noted)

reference input (REFIN)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

ref

Input voltage reference See Note 10 0 AVDD–1.5 V
RiInput resistance 10 MΩ
CiInput capacitance 5 pF

p

Fast mode 1.6 MHz

Reference in ut bandwidth

REF

= 0.2

V

pp

+ 1.024 V dc

Slow mode 1 MHz

Reference feed through

REF = 1 Vpp at 1 kHz + 1.024 V dc,
See Note 10

–60 dB

NOTES: 10. Referen ce feedthrough is measured at the DAC output with an input code = 0x000.

digital inputs

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

I

IH

High-level digital input current VI = DV

DD

1 µA

I

IL

Low-level digital input current VI = 0 V –1 µA

C

i

Input capacitance 8 pF

operating characteristics over recommended operating free-air temperature range, supply
voltages, and reference voltages (unless otherwise noted)

analog output dynamic performance

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

p

R

= 10 kΩ,

See Note 11

Fast 1 3

t

s(FS)

Output settling time, full scale

L

,

CL = 100 pF,

Slow 3.5 7

µ

s

p

R

= 10 kΩ,

See Note 12

Fast 0.5 1.5

t

s(CC)

Output settling time, code-to-code

L

,

CL = 100 pF,

Slow 1 2

µ

s

R

= 10 kΩ, See Note 13

Fast 8

SR

Slew rate

L

,

CL = 100 pF,

Slow 1.5

V/µs

Glitch energy Code-to-code transition 1 nV–s
S/N Signal-to-noise 65 78
S/(N+D) Signal-to-noise + distortion

f

= 480 KSPS, f

= 1 kHz,

58 69

THD T otal harmonic distortion

s

,

out

,

RL = 10 k, CL = 100 pF

–68 –60

dB

Spurious free dynamic range 60 72

NOTES: 11. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change

of 0x020 to 0x3FF or 0x3FF to 0x020.

12. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change
of one count. The max time applies to code changes near zero scale or full scale.

13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.

TLV5613

2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER
WITH POWER DOWN

SLAS174A – DECEMBER 1997 – REVISED JUL Y 1998

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

timing requirements

digital inputs

MIN NOM MAX UNIT

t

su(D)

Setup time, data ready before positive WE edge 9 ns

t

su(CS-WE)

Setup time, CS low before positive WE edge 13 ns

t

su(A)

Setup time, address bits A0, A1 17 ns

t

h(D)

Hold time, data held after positive WE edge 0 ns

tsu(WE-LD) Setup time, positive WE edge before LDAC low 0 ns
tw(WE) Pulse duration, WE high 10 ns
tw(LD) Pulse duration, LDAC low 10 µs

PARAMETER MEASUREMENT INFORMATION

X Data X

X Address X

t

su(D)

t

su(A)

t

h(D)

t

w(WE)

t

su(WE-LD)

t

w(LD)

t

su(CS-WE)

D(0–7)

A(0–1)

CS

WE

LDAC

Figure 1. Timing Diagram

TLV5613

2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER
WITH POWER DOWN

SLAS174A – DECEMBER 1997 – REVISED JUL Y 1998

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

MSWX X LSW X

0XX1X

D(0–7)

A(0–1)

CS

WE

LDAC

Figure 2. Example of a Complete Write Cycle Using LDAC to Update the DAC

MSWX X LSW ControlXX

0XX13XX

D(0–7)

A(0–1)

CS

WE

LDAC

Figure 3. Example of a Complete Write Cycle Using the Control Word to Update the DAC