Texas Instruments TLV2332IDR, TLV2332ID, TLV2334IPWLE, TLV2334IPW, TLV2334IN Datasheet

TLV2332, TLV2332Y, TLV2334, TLV2334Y

LinCMOS LOW-VOLTAGE MEDIUM-POWER

OPERATIONAL AMPLIFIERS

SLOS189 – FEBRUARY 1997

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Wide Range of Supply Voltages Over
Specified Temperature Range:

T

A

= –40°C to 85°C...2 V to 8 V

D

Fully Characterized at 3 V and 5 V

D

Single-Supply Operation

D

Common-Mode Input-Voltage Range
Extends Below the Negative Rail and up to
V

DD

–1 V at TA = 25°C

D

Output Voltage Range Includes Negative
Rail

D

High Input Impedance...10

12

Ω Typ

D

ESD-Protection Circuitry

D

Designed-In Latch-Up Immunity

description

The TL V233x operational amplifiers are in a family
of devices that has been specifically designed for
use in low-voltage single-supply applications.
Unlike the TLV2322 which is optimized for
ultra-low power, the TLV233x is designed to
provide a combination of low power and good ac
performance. Each amplifier is fully functional
down to a minimum supply voltage of 2 V, is fully
characterized, tested, and specified at both 3-V
and 5-V power supplies. The common-mode
input-voltage range includes the negative rail and
extends to within 1 V of the positive rail.

Having a maximum supply current of only 310 µA
per amplifier over full temperature range, the
TLV233x devices offer a combination of good ac
performance and microampere supply currents.
From a 3-V power supply, the amplifier’s typical
slew rate is 0.38 V/µs and its bandwidth is
300 kHz.

AVAILABLE OPTIONS

PACKAGED DEVICES

T

A

VIOmax

AT 25°C

SMALL OUTLINE

†

(D)

PLASTIC DIP

(N)

PLASTIC DIP

(P)

TSSOP

‡

(PW)

CHIP FORM

§

(Y)

°

°

9 mV TLV2332ID — TLV2332IP TLV2332IPWLE TLV2332Y

–

40°C to 85°C

10 mV TLV2334ID TLV2334IN — TLV2334IPWLE TLV2334Y

†

The D package is available taped and reeled. Add R suffix to the device type (e.g., TL V2332IDR).

‡

The PW package is only available left-end taped and reeled (e.g., TLV2332IPWLE).

§

Chip forms are tested at 25°C only.

Copyright  1997, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

LinCMOS is a trademark of Texas Instruments Incorporated.

1
2
3
4

8
7
6
5

1OUT

1IN–
1IN+

V

DD–

/GND

V

DD

2OUT
2IN–
2IN+

1
2
3
4

8
7
6
5

1OUT

1IN–

1IN+

V

DD –

/GND

V

DD+

2OUT
2IN–
2IN+

TLV2332

D OR P PACKAGE

(TOP VIEW)

TLV2332

PW PACKAGE

(TOP VIEW)

1
2
3
4
5
6
7

14
13
12
11
10

9
8

1OUT

1IN–
1IN+

V

DD+

2IN+

2N–

2OUT

4OUT
4IN–
4IN+
V

DD–/GND

3IN+
3IN–
3OUT

4OUT
4IN–
4IN+
V

DD–/GND

3IN+
3IN–
3OUT

1OUT

1IN–
1IN+

V

DD+

2IN+
2IN–

2OUT

1

78

14

TLV2334

D OR N PACKAGE

(TOP VIEW)

TLV2334

PW PACKAGE

(TOP VIEW)

TLV2332, TLV2332Y, TLV2334, TLV2334Y
LinCMOS LOW-VOLTAGE MEDIUM-POWER
OPERATIONAL AMPLIFIERS

SLOS189 – FEBRUARY 1997

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description (continued)

These amplifiers offer a level of ac performance greater than that of many other devices operating at
comparable power levels. The TL V233x operational amplifiers are especially well suited for use in low-current
or battery-powered applications.

Low-voltage and low-power operation has been made possible by using the Texas Instruments silicon-gate
LinCMOS technology . The LinCMOS process also features extremely high input impedance and ultra-low bias
currents making these amplifiers ideal for interfacing to high-impedance sources such as sensor circuits or filter
applications.

T o facilitate the design of small portable equipment, the TL V233x is made available in a wide range of package
options, including the small-outline and thin-shrink small-outline package (TSSOP). The TSSOP package has
significantly reduced dimensions compared to a standard surface-mount package. Its maximum height of only

1.1 mm makes it particularly attractive when space is critical.
The device inputs and outputs are designed to withstand –100-mA currents without sustaining latch-up. The

TLV233x incorporates internal ESD-protection circuits that prevents functional failures at voltages up to
2000 V as tested under MIL-STD 883C, Method 3015.2; however, care should be exercised in handling these
devices as exposure to ESD may result in the degradation of the device parametric performance.

TLV2332Y chip information

This chip, when properly assembled, display characteristics similar to the TLV2332. Thermal compression or
ultrasonic bonding may be used on the doped-aluminum bonding pads. Chips may be mounted with conductive
epoxy or a gold-silicon preform.

BONDING PAD ASSIGNMENTS

CHIP THICKNESS: 15 MILS TYPICAL
BONDING PADS: 4 × 4 MILS MINIMUM
TJmax = 150°C
TOLERANCES ARE ±10%.
ALL DIMENSIONS ARE IN MILS.
PIN (4) IS INTERNALLY CONNECTED

TO BACKSIDE OF CHIP.

+

–

1OUT

1IN+

1IN–

V

DD

V

DD–

/GND

(8)

(6)

(3)

(2)

(5)

(1)

–

+

(7)

2IN+

2IN–

2OUT

(4)

59

72

(1)

(2)

(3)

(4)

(5)

(6)

(7)

(8)

TLV2332, TLV2332Y, TLV2334, TLV2334Y

LinCMOS LOW-VOLTAGE MEDIUM-POWER

OPERATIONAL AMPLIFIERS

SLOS189 – FEBRUARY 1997

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV2334Y chip information

This chip, when properly assembled, displays characteristics similar to the TL V2334. Thermal compression or
ultrasonic bonding may be used on the doped-aluminum bonding pads. Chips may be mounted with conductive
epoxy or a gold-silicon preform.

BONDING PAD ASSIGNMENTS

+

–

1OUT

1IN+

1IN–

V

DD

(4)

(6)

(3)

(2)

(5)

(1)

2IN+

2IN–

2OUT

(11)

V

DD–

/GND

+

–

3OUT

3IN+

3IN–

(13)

(10)

(9)

(12)

(8)

–

+

(14)

4OUT

4IN+

4IN–

+

–

(7)

CHIP THICKNESS: 15 MILS TYPICAL
BONDING PADS: 4 × 4 MILS MINIMUM
TJmax = 150°C
TOLERANCES ARE ±10%.
ALL DIMENSIONS ARE IN MILS.

68

108

(1) (2) (3) (4) (5) (6) (7)

(8)(9)(10)(11)(12)(13)(14)

TLV2332, TLV2332Y, TLV2334, TLV2334Y
LinCMOS LOW-VOLTAGE MEDIUM-POWER
OPERATIONAL AMPLIFIERS

SLOS189 – FEBRUARY 1997

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

equivalent schematic (each amplifier)

P1

P4

P5

P6

N3

N5

OUT

R6

V

DD

P3

P2

IN–

IN+

R1

R2

R5

C1

R3

D1

R4

N1

N2

D2

GND

N4

N6

R7

N7

ACTUAL DEVICE COMPONENT COUNT

†

COMPONENT TLV2332 TLV2334

Transistors 54 108
Resistors 14 28
Diodes 4 8
Capacitors 2 4

†

Includes both amplifiers and all ESD, bias, and trim
circuitry.

TLV2332, TLV2332Y, TLV2334, TLV2334Y

LinCMOS LOW-VOLTAGE MEDIUM-POWER

OPERATIONAL AMPLIFIERS

SLOS189 – FEBRUARY 1997

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

†

Supply voltage, V

DD

(see Note 1) 8 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Differential input voltage, V

ID

(see Note 2) V

DD±

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

I

(any input) –0.3 V to V

DD

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input current, I

I

±5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output current, I

O

±30 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Duration of short-circuit current at (or below) T

A

= 25°C (see Note 3) unlimited. . . . . . . . . . . . . . . . . . . . . . . . .

Continuous total dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T

A

–40°C to 85° C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. All voltage values, except differential voltages, are with respect to network ground.

2. Differential voltages are at the noninverting input with respect to the inverting input.

3. The output may be shorted to either supply. Temperature and /or supply voltages must be limited to ensure that the maximum
dissipation rating is not exceeded (see application section).

DISSIPATION RATING TABLE

T

≤ 25°C DERATING FACTOR T

= 85°C

PACKAGE

A

POWER RATING ABOVE TA = 25°C

A

POWER RATING

D–8 725 mW 5.8 mW/°C 377 mW

D–14 950 mW 7.6 mW/°C 494 mW

N 1575 mW 12.6 mW/°C 819 mW
P 1000 mW 8.0 mW/°C 520 mW

PW–8 525 mW 4.2 mW/°C 273 mW

PW–14 700 mW 5.6 mW/°C 364 mW

recommended operating conditions

MIN MAX UNIT

Supply voltage, V

DD

2 8 V

p

VDD = 3 V –0.2 1.8

Common-mode input voltage, V

IC

VDD = 5 V –0.2 3.8

V

Operating free-air temperature, T

A

–40 85 °C

TLV2332, TLV2332Y, TLV2334, TLV2334Y
LinCMOS LOW-VOLTAGE MEDIUM-POWER
OPERATIONAL AMPLIFIERS

SLOS189 – FEBRUARY 1997

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV2332I electrical characteristics at specified free-air temperature

TLV2332I

PARAMETER

TEST

T

A

†

VDD = 3 V VDD = 5 V

UNIT

CONDITIONS

A

MIN TYP MAX MIN TYP MAX

p

VO = 1 V,
V

= 1 V,

25°C 0.6 9 1.1 9

VIOInput offset voltage

IC

,

RS = 50 Ω,
RL = 100 kΩ

Full range 11 11

mV

α

VIO

Average temperature coefficient of
input offset voltage

25°C to

85°C

1 1.7 µV/°C

p

V

= 1 V,

25°C 0.1 0.1

p

IIOInput offset current (see Note 4)

O

,

VIC = 1 V

85°C 22 1000 24 1000

pA

p

V

= 1 V,

25°C 0.6 0.6

p

IIBInput bias current (see Note 4)

O

,

VIC = 1 V

85°C 175 2000 200 2000

pA

°

–0.2

–0.3

–0.2

–0.3

Common-mode input

25°C

t

o
2

t

o

2.3

t

o
4

t

o

4.2

V

ICR

voltage range (see Note 5)

Full range

–0.2

to

1.8

–0.2

to

3.8

V

p

VIC = 1 V,

25°C 1.75 1.9 3.2 3.9

VOHHigh-level output voltage

V

ID

=

100 mV

,

IOH = –1 mA

Full range 1.7 3

V

p

VIC = 1 V,

25°C 115 150 95 150

VOLLow-level output voltage

V

ID

= –

100 mV

,

IOL = 1 mA

Full range 190 190

mV

Large-signal differential

VIC = 1 V,

25°C 25 83 25 170

A

VD

gg

voltage amplification

R

L

=

100 kΩ

,

See Note 6

Full range 15 15

V/mV

VO = 1 V,

25°C 65 92 65 91

CMRR

Common-mode rejection ratio

V

IC

=

V

ICR

min,

RS = 50 Ω

Full range 60 60

dB

Supply-voltage rejection ratio

VIC = 1 V,

25°C 70 94 70 94

k

SVR

ygj

(∆VDD/∆VIO)

V

O

=

1 V

,

RS = 50 Ω

Full range 65 65

dB

pp

VO = 1 V,

25°C 160 500 210 560

IDDSupply current

V

IC

= 1 V,

No load

Full range 620 800

µ

A

†

Full range is –40°C to 85°C.

NOTES: 4. The typical values of input bias current and input offset current below 5 pA are determined mathematically .

5. This range also applies to each input individually.

6. At VDD = 5 V, VO = 0.25 V to 2 V; at VDD = 3 V, VO = 0.5 V to 1.5 V.

TLV2332, TLV2332Y, TLV2334, TLV2334Y

LinCMOS LOW-VOLTAGE MEDIUM-POWER

OPERATIONAL AMPLIFIERS

SLOS189 – FEBRUARY 1997

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV2332I operating characteristics at specified free-air temperature, VDD = 3 V

TLV2332I

PARAMETER

TEST CONDITIONS

T

A

MIN TYP MAX

UNIT

VIC = 1 V,

V

I(PP)

= 1 V,

p

25°C 0.38

SR

Slew rate at unity gain

R

L

=

100 kΩ

,

See Figure 34

C

L

= 20 F,

85°C

0.29

V/µs

V

n

Equivalent input noise voltage

f =1 kHz,
See Figure 35

RS = 20 Ω,

25°C 32

nV/√Hz

p

V

= V

, C

= 20 pF,

25°C 34

BOMMaximum output-swing bandwidth

OOH

,

RL = 100 kΩ,

L

,

See Figure 34

85°C

32

kH

z

V

= 10 mV, C

= 20 pF,

25°C 300

B1Unity-gain bandwidth

I

,

RL = 100 kΩ,

L

,

See Figure 36

85°C 235

kH

z

V

= 10 mV

,

f = B

,

–40°C 42°

φ

m

Phase margin

V

I

10

mV,

CL = 20 pF,

f B1,

RL = 100 kΩ,

25°C

39°

See Figure 36

85°C 36°

TLV2332I operating characteristics at specified free-air temperature, VDD = 5 V

TLV2332I

PARAMETER

TEST CONDITIONS

T

A

MIN TYP MAX

UNIT

25°C 0.43

V

IC

= 1 V,

RL = 100 kΩ,

V

I(PP)

= 1

V

85°C 0.35

SR

Slew rate at unity gain

L

,

CL = 20 pF,

25°C 0.40

V/µs

See Figure 34

V

I(PP)

= 2.5

V

85°C 0.32

V

n

Equivalent input noise voltage

f =1 kHz,
See Figure 35

RS = 20 Ω,

25°C 32

nV/√Hz

p

V

= V

, C

= 20 pF,

25°C 55

BOMMaximum output-swing bandwidth

OOH

,

RL = 100 kΩ,

L

,

See Figure 34

85°C

45

kH

z

V

= 10 mV, C

= 20 pF,

25°C 525

B1Unity-gain bandwidth

I

,

RL = 100 kΩ,

L

,

See Figure 36

85°C

370

kH

z

V

= 10 mV

,

f = B

,

–40°C 43°

φ

m

Phase margin

V

I

10

mV,

CL = 20 pF,

f B1,

RL = 100 kΩ,

25°C

40°

See Figure 36

85°C 38°

TLV2332, TLV2332Y, TLV2334, TLV2334Y
LinCMOS LOW-VOLTAGE MEDIUM-POWER
OPERATIONAL AMPLIFIERS

SLOS189 – FEBRUARY 1997

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV2334I electrical characteristics at specified free-air temperature

TLV2334I

PARAMETER TEST CONDITIONS

T

A

†

VDD = 3 V VDD = 5 V

UNIT

A

MIN TYP MAX MIN TYP MAX

p

VO = 1 V, VIC = 1 V,

25°C 0.6 10 1.1 10

VIOInput offset voltage

R

S

=

50 Ω

,

RL = 100 kΩ

Full range 12 12

mV

α

VIO

Average temperature coefficient
of input offset voltage

25°C to

85°C

1 1.7 µV/°C

p

25°C 0.1 0.1

p

IIOInput offset current (see Note 4)

V

O

= 1 V,

V

IC

= 1

V

85°C 22 1000 24 1000

pA

p

25°C 0.6 0.6

p

IIBInput bias current (see Note 4)

V

O

=

1 V

,

V

IC

=

1 V

85°C 175 2000 200 2000

pA

°

–0.2

–0.3

–0.2

–0.3

Common-mode input voltage

25°C

t

o
2

t

o

2.3

t

o
4

t

o

4.2

V

V

ICR

g

range (see Note 5)

Full range

–0.2

to

1.8

–0.2

to

3.8

V

p

VIC = 1 V,

25°C 1.75 1.9 3.2 3.9

VOHHigh-level output voltage

V

ID

=

100 mV

,

IOH = –1 mA

Full range 1.7 3

V

p

VIC = 1 V,

25°C 115 150 95 150

VOLLow-level output voltage

V

ID

= –

100 mV

,

IOL = 1 mA

Full range 190 190

mV

Large-signal differential

VIC = 1 V,

25°C 25 83 25 170

A

VD

gg

voltage amplification

R

L

=

100 kΩ

,

See Note 6

Full range 15 15

V/mV

VO = 1 V,

25°C 65 92 65 91

CMRR

Common-mode rejection ratio

V

IC

=

V

ICR

min,

RS = 50 Ω

Full range 60 60

dB

Supply-voltage rejection ratio

VDD = 3 V to 5 V,

25°C 70 94 70 94

k

SVR

ygj

(∆VDD/∆VIO)

V

IC

=

1 V

,

V

O

=

1 V

,

RS = 50 Ω

Full range 65 65

dB

pp

VO = 1 V, VIC = 1 V,

25°C 320 1000 420 1120

IDDSupply current

OIC

No load

Full range 1200 1600

µ

A

†

Full range is –40°C to 85°C.

NOTES: 4. The typical values of input bias current and input offset current below 5 pA are determined mathematically.

5. This range also applies to each input individually.

6. At VDD = 5 V, VO = 0.25 V to 2 V; at VDD = 3 V, VO = 0.5 V to 1.5 V.

TLV2332, TLV2332Y, TLV2334, TLV2334Y

LinCMOS LOW-VOLTAGE MEDIUM-POWER

OPERATIONAL AMPLIFIERS

SLOS189 – FEBRUARY 1997

9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV2334I operating characteristics at specified free-air temperature, VDD = 3 V

TLV2334I

PARAMETER

TEST CONDITIONS

T

A

MIN TYP MAX

UNIT

VIC = 1 V,

V

I(PP)

= 1 V,

p

25°C 0.38

SR

Slew rate at unity gain

R

L

=

100 kΩ

,

See Figure 34

C

L

= 20 F,

85°C

0.29

V/µs

V

n

Equivalent input noise voltage

f = 1 kHz,
See Figure 35

RS = 20 Ω,

25°C 32

nV/√Hz

p

V

= V

, C

= 20 pF,

25°C 34

BOMMaximum output-swing bandwidth

OOH

,

RL = 100 kΩ,

L

,

See Figure 34

85°C

32

kH

z

V

= 10 mV, C

= 20 pF,

25°C 300

B1Unity-gain bandwidth

I

,

RL = 100 kΩ,

L

,

See Figure 36

85°C

235

kH

z

V

= 10 mV

,

–40°C 42°

φ

m

Phase margin

V

I

10

mV,

CL = 20 pF,

f

=

B

1

,

=

25°C 39°

See Figure 36

R

L

=

100 kΩ

,

85°C 36°

TLV2334I operating characteristics at specified free-air temperature, VDD = 5 V

TLV2334I

PARAMETER

TEST CONDITIONS

T

A

MIN TYP MAX

UNIT

25°C 0.43

V

IC

= 1 V,

RL = 100 kΩ,

V

I(PP)

= 1

V

85°C 0.35

SR

Slew rate at unity gain

L

,

CL = 20 pF,

25°C 0.40

V/µs

See Figure 34

V

I(PP)

= 2.5

V

85°C 0.32

V

n

Equivalent input noise voltage

f = 1 kHz,
See Figure 35

RS = 20 Ω,

25°C 32

nV/√Hz

p

V

= V

, C

= 20 pF,

25°C 55

BOMMaximum output-swing bandwidth

OOH

,

RL = 100 kΩ,

L

,

See Figure 34

85°C

45

kH

z

V

= 10 mV, C

= 20 pF,

25°C 525

B1Unity-gain bandwidth

I

,

RL = 100 kΩ,

L

,

See Figure 36

85°C

370

kH

z

V

= 10 mV

,

f = B

,

–40°C 43°

φ

m

Phase margin

V

I

10

mV,

CL = 20 pF,

f B1,

RL = 100 kΩ,

25°C 40°

See Figure 36

85°C 38°

TLV2332, TLV2332Y, TLV2334, TLV2334Y
LinCMOS LOW-VOLTAGE MEDIUM-POWER
OPERATIONAL AMPLIFIERS

SLOS189 – FEBRUARY 1997

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV2332Y electrical characteristics, T

A

= 25°C

TLV2332Y

PARAMETER TEST CONDITIONS

VDD = 3 V VDD = 5 V

UNIT

MIN TYP MAX MIN TYP MAX

V

IO

Input offset voltage

VO = 1 V,
RS = 50 Ω,

VIC = 1 V,
RL = 100 kΩ

0.6 1.1 mV

I

IO

Input offset current (see Note 4) VO = 1 V, VIC = 1 V 0.1 0.1 pA

I

IB

Input bias current (see Note 4) VO = 1 V, VIC = 1 V 0.6 0.6 pA

V

ICR

Common-mode input voltage
range (see Note 5)

–0.3

to

2.3

–0.3

to

4.2

V

V

OH

High-level output voltage

VIC = 1 V,
IOH = –1 mA

VID = 100 mV ,

1.9 3.9 V

V

OL

Low-level output voltage

VIC = 1 V,
IOL = 1 mA

VID = 100 mV ,

115 95 mV

A

VD

Large-signal differential voltage
amplification

VIC = 1 V,
See Note 6

RL = 100 kΩ,

83 170 V/mV

CMRR Common-mode rejection ratio

VO = 1 V,
RS = 50 Ω

VIC = V

ICR

min,

92 91 dB

k

SVR

Supply-voltage rejection ratio
(∆VDD/∆VID)

VO = 1 V,
RS = 50 Ω

VIC = 1 V,

94 94 dB

I

DD

Supply current

VO = 1 V,
No load

VIC = 1 V,

160 210 µA

NOTES: 4. The typical values of input bias current and input offset current below 5 pA are determined mathematically .

5. This range also applies to each input individually.

6. At VDD = 5 V, VO = 0.25 V to 2 V; at VDD = 3 V, VO = 0.5 V to 1.5 V.

TLV2332, TLV2332Y, TLV2334, TLV2334Y

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TLV2334Y electrical characteristics, T

A

= 25°C

TLV2334Y

PARAMETER TEST CONDITIONS

VDD = 3 V VDD = 5 V

UNIT

MIN TYP MAX MIN TYP MAX

V

IO

Input offset voltage

VO = 1 V,
RS = 50 Ω,

VIC = 1 V
RL = 100 kΩ

0.6 1.1 mV

I

IO

Input offset current (see Note 4) VO = 1 V, VIC = 1 V 0.1 0.1 pA

I

IB

Input bias current (see Note 4) VO = 1 V, VIC = 1 V 0.6 0.6 pA

V

ICR

Common-mode input voltage
range (see Note 5)

–0.3

to

2.3

–0.3

to

4.2

V

V

OH

High-level output voltage

VIC = 1 V,
IOH = –1 mA

VID = 100 mV ,

1.9 3.9 V

V

OL

Low-level output voltage

VIC = 1 V,
IOL = 1 mA

VID = –100 mV,

115 95 mV

A

VD

Large-signal differential voltage
amplification

VIC = 1 V,
See Note 6

RL = 100 kΩ,

83 170 V/mV

CMRR Common-mode rejection ratio

VO = 1 V,
RS = 50 Ω

VIC = V

ICR

min,

92 91 dB

k

SVR

Supply-voltage rejection ratio
(∆VDD/∆VID)

VIC = 1 V,
RS = 50 Ω

VO = 1 V,

94 94 dB

I

DD

Supply current

VO = 1 V,
No load

VIC = 1 V,

320 420 µA

NOTES: 4. The typical values of input bias current offset current below 5 pA are determined mathematically.

5. This range also applies to each input individually.

6. At VDD = 5 V, VO = 0.25 V to 2 V; at VDD = 3 V, VO = 0.5 V to 1.5 V.

TLV2332, TLV2332Y, TLV2334, TLV2334Y
LinCMOS LOW-VOLTAGE MEDIUM-POWER
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TYPICAL CHARACTERISTICS

Table of Graphs

FIGURE

V

IO

Input offset voltage Distribution 1 – 4

α

VIO

Input offset voltage temperature coefficient Distribution 5 – 8

I

IB

Input bias current vs Free-air temperature 9

I

IO

Input offset current vs Free-air temperature 9

V

IC

Common-mode input voltage vs Supply voltage 10

V

OH

High-level output voltage

vs High-level output current
vs Supply voltage
vs Free-air temperature

11
12
13

V

OL

Low-level output voltage

vs Common-mode input voltage
vs Free-air temperature
vs Differential input voltage
vs Low-level output current

14

15, 16

17
18

A

VD

Large-signal differential voltage amplification

vs Supply voltage
vs Free-air temperature
vs Frequency

19
20

21, 22

I

DD

Supply current

vs Supply voltage
vs Free-air temperature

23
24

SR Slew rate

vs Supply voltage
vs Free-air temperature

25
26

V

O(PP)

Maximum peak-to-peak output voltage vs Frequency 27

B

1

Unity-gain bandwidth

vs Supply voltage
vs Free-air temperature

28
29

φ

m

Phase margin

vs Supply voltage
vs Free-air temperature
vs Load capacitance

30
31
32

Phase shift vs Frequency 21, 22

V

n

Equivalent input noise voltage vs Frequency 33

TLV2332, TLV2332Y, TLV2334, TLV2334Y

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TYPICAL CHARACTERISTICS

Figure 1

–5 –4 –3 –2 –1 0 1 2 3 4 5

50

40

20

10

0

30

Percentage of Units – %

DISTRIBUTION OF TLV2332

INPUT OFFSET VOLTAGE

VIO – Input Offset Voltage – mV

VDD = 3 V
TA = 25°C
P Package

Figure 2

–5 –4 –3 –2 –1 0 1 2 3 4 5

50

40

20

10

30

60

Percentage of Units – %

DISTRIBUTION OF TLV2332

INPUT OFFSET VOLTAGE

0

VIO – Input Offset Voltage – mV

VDD = 5 V
TA = 25°C
P Package

Figure 3

50

40

20

10

0

30

–1 0 1

Percentage of Units – %

2345

DISTRIBUTION OF TLV2334

INPUT OFFSET VOLTAGE

VIO – Input Offset Voltage – mV

VDD = 3 V
TA = 25°C
N Package

–5 –4 –3 –2

Figure 4

–5 –4 –3 –2

50

40

20

10

0

30

–1 0 1602345

Percentage of Units – %

VIO – Input Offset Voltage – mV

DISTRIBUTION OF TLV2334

INPUT OFFSET VOLTAGE

VDD = 5 V
TA = 25°C
N Package

TLV2332, TLV2332Y, TLV2334, TLV2334Y
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TYPICAL CHARACTERISTICS

Figure 5

–10–8–6–4–2 0 2 4 6 8 10

50

40

20

10

0

30

Percentage of Units – %

VDD = 3 V
TA = 25°C to 85°C
P Package

DISTRIBUTION OF TLV2332

INPUT OFFSET VOLTAGE

TEMPERATURE COEFFICIENT

α

VIO

– Temperature Coefficient – µV/°C

Figure 6

–10–8–6–4–20246810

50

40

20

10

30

60

0

Percentage of Units – %

VDD = 5 V
TA = 25°C to 85°C
P Package
Outliers:
(1) 33 mV/°C

DISTRIBUTION OF TLV2332

INPUT OFFSET VOLTAGE

TEMPERATURE COEFFICIENT

α

VIO

– Temperature Coefficient – µV/°C

Figure 7

–10 –2 0 2

Percentage of Units – %

46810

α

VIO

– Temperature Coefficient – µV/°C

50

40

20

10

0

30

VDD = 3 V
TA = 25°C to 85°C
N Package

DISTRIBUTION OF TLV2334

INPUT OFFSET VOLTAGE

TEMPERATURE COEFFICIENT

–8 –6 –4

Figure 8

–8 –6 –4

α

VIO

– Temperature Coefficient – µV/°C

Percentage of Units – %

–10 –2 0 2 4 6 8 10

50

40

20

10

0

30

60

DISTRIBUTION OF TLV2334

INPUT OFFSET VOLTAGE

TEMPERATURE COEFFICIENT

VDD = 5 V
TA = 25°C to 85°C
N Package
Outliers:
(1) 33 mV/°C

TLV2332, TLV2332Y, TLV2334, TLV2334Y

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TYPICAL CHARACTERISTICS

Figure 9

INPUT BIAS CURRENT AND INPUT OFFSET CURREN

T

vs

FREE-AIR TEMPERATURE

TA – Free-Air Temperature – °C

IIB and IIO – Input Bias and Input Offset Currents – pA

I

IB

I

IO

10

4

10

3

10

2

10

1

1

0.1
25 45 65 85 105 125

VDD = 3 V
VIC = 1 V
See Note A

I

IB

I

IO

NOTE: The typical values of input bias current and input offset

current below 5 pA were determined mathematically.

Figure 10

COMMON-MODE INPUT VOLTAGE

vs

SUPPLY VOLTAGE

4

2

0

8

6

02468

V

DD

– Supply Voltage – V

VIC – Common-Mode Input Voltage – V

IC

V

TA = 25°C
Positive Limit

Figure 11

V0H – High-Level Output Voltage – V

V

OH

3

2

1

0

0

4

5

IOH – High-Level Output Current – mA

HIGH-LEVEL OUTPUT VOLTAGE

vs

HIGH-LEVEL OUTPUT CURRENT

VIC = 1 V
VID = 100 mV
TA = 25°C

VDD = 3 V

VDD = 5 V

–2 –4 –6 –8

Figure 12

V0H – High-Level Output Voltage – V

V

OH

4

2

0

8

6

02468

HIGH-LEVEL OUTPUT VOLTAGE

vs

SUPPLY VOLTAGE

VDD – Supply Voltage – V

VIC = 1 V
VID = 100 mV
RL = 100 kΩ
TA = 25°C

TLV2332, TLV2332Y, TLV2334, TLV2334Y
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TYPICAL CHARACTERISTICS

Figure 13

1.8

1.2

0.6

0

2.4

3

HIGH-LEVEL OUTPUT VOLTAGE

vs

FREE-AIR TEMPERATURE

–75 –50 –25 0 25 50 75 100 125

TA – Free-Air Temperature – °C

V0H – High-Level Output Voltage – V

V

OH

VDD = 3 V
VIC = 1 V
VID = 100 mV

IOH = –500 µA
IOH = –1 mA
IOH = –2 mA
IOH = –3 mA
IOH = –4 mA

Figure 14

VOL – Low-Level Output V oltage – mV

V

OL

500

400

350

300

0 0.5 1 1.5 2 2.5

600

650

700

3 3.5 4

550

450

LOW-LEVEL OUTPUT VOLTAGE

vs

COMMON-MODE INPUT VOLTAGE

VIC – Common-Mode Input Voltage – V

VID = –100 mV

VID = –1 V

VDD = 5 V
IOL = 5 mA
TA = 25°C

Figure 15

–75 –50 –25 0 25 50 75 100 125

125

110

80
65
50

185

95

155

140

170

200

LOW-LEVEL OUTPUT VOLTAGE

vs

FREE-AIR TEMPERATURE

TA – Free-Air Temperature – °C

VOL – Low-Level Output V oltage – mV

V

OL

VDD = 3 V
VIC = 1 V
VID = –100 mV
IOL = 1 mA

Figure 16

400

200

100

0

600

700

800

500

300

LOW-LEVEL OUTPUT VOLTAGE

vs

FREE-AIR TEMPERATURE

900

–75 –50 –25 0 25 50 75 100 125

TA – Free-Air Temperature – °C

VOL – Low-Level Output V oltage – mV

V

OL

VDD = 5 V
VIC = 0.5 V
VID = –1 V
IOL = 5 mA

TLV2332, TLV2332Y, TLV2334, TLV2334Y

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TYPICAL CHARACTERISTICS

Figure 17

400

200

100

0

0–1–2–3–4–5

600

700

800

–6 –7 –8

500

300

LOW-LEVEL OUTPUT VOLTAGE

vs

DIFFERENTIAL INPUT VOLTAGE

VOL – Low-Level Output V oltage – mV

V

OL

VID – Differential Input Voltage – V

VDD = 5 V
VIC = |VID/2|
IOL = 5 mA
TA = 25°C

Figure 18

0.5

0.4

0.2

0.1
0

0.9

0.3

0123456

0.7

0.6

0.8

1

78

LOW-LEVEL OUTPUT VOLTAGE

vs

LOW-LEVEL OUTPUT CURRENT

VOL – Low-Level Output Voltage – V

V

OL

IOL – Low-Level Output Current – mA

VDD = 3 V

VDD = 5 V

VIC = 1 V
VID = –100 mV
TA = 25°C

Figure 19

02468

LARGE-SIGNAL

DIFFERENTIAL VOLTAGE AMPLIFICATION

vs

SUPPLY VOLTAGE

VDD – Supply Voltage – V

200
150

350

0

300

450

500

100

400

250

50

RL = 100 kΩ

TA = –40°C

TA = 25°C

TA = 85°C

– Large-Signal Differential Voltage
A

VD

Amplification – V/mV

Figure 20

200
150

350

300

450

500

100

400

250

50

LARGE-SIGNAL

DIFFERENTIAL VOLTAGE AMPLIFICATION

vs

FREE-AIR TEMPERATURE

–75 –50 –25 0 25 50 75 100 125

VDD = 3 V

RL = 100 kΩ

0

VDD = 5 V

TA – Free-Air Temperature – °C

– Large-Signal Differential Voltage
A

VD

Amplification – V/mV

TLV2332, TLV2332Y, TLV2334, TLV2334Y
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TYPICAL CHARACTERISTICS

10

7

10

6

10

5

10

4

10

3

10

2

10

1

1

0.1
1 10 100 1 k 10 k 100 k

f – Frequency – Hz

LARGE-SIGNAL DIFFERENTIAL VOLTAGE

AMPLIFICATION AND PHASE SHIFT

vs

FREQUENCY

1 M

Phase Shift

60°

30°

90°

–60°

–30°

0°

120°

150°

180°

Phase Shift

A

VD

VDD = 3 V
RL = 100 kΩ
CL = 20 pF
TA = 25°C

– Large-Signal Differential Voltage Amplification
A

VD

Figure 21

1 10 100 1 k 10 k 100 k 1 M

10

7

10

6

10

5

10

4

10

3

10

2

10

1

0.1

LARGE-SIGNAL DIFFERENTIAL VOLTAGE

AMPLIFICATION AND PHASE SHIFT

vs

FREQUENCY

f – Frequency – Hz

Phase Shift

VDD = 5 V
RL = 100 kΩ
CL = 20 pF
TA = 25°C

1

60°

30°

90°

–60°

–30°

0°

120°

150°

180°

Phase Shift

A

VD

– Large-Signal Differential Voltage Amplification
A

VD

Figure 22

TLV2332, TLV2332Y, TLV2334, TLV2334Y

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TYPICAL CHARACTERISTICS

Figure 23

02468

200

100

50

0

350

400

450

250

150

VIC = 1 V
VO = 1 V
No Load

TA = –40°C

TA = 25°C

TA = 85°C

SUPPLY CURRENT

vs

SUPPLY VOLTAGE

VDD – Supply Voltage – V

300

IDD – Supply Current – uA

DD

IAµ

Figure 24

1007550250–25–50–75

200

100

50

0

300

350

400

250

150

125

SUPPLY CURRENT

vs

FREE-AIR TEMPERATURE

TA – Free-Air Temperature – °C

VIC = 1 V
VO = 1 V
No Load

VDD = 5 V

IDD – Supply Current – uA

DD

IAµ

V

DD

= 3 V

Figure 25

02468

0.7

0.5

0.4

0.3

0.9

0.6

SR – Slew Rate – V/us

0.8

sµV/

VIC = 1 V
V

I(PP)

= 1 V
AV = 1
RL = 100 kΩ
CL = 20 pF
TA = 25°C

VDD – Supply Voltage – V

SLEW RATE

vs

SUPPLY VOLTAGE

Figure 26

0.7

0.5

0.4

0.3

0.9

0.6

0.8

–75 –50 –25 0 25 50 75 100 125

VDD = 5 V

VDD = 3 V

VIC = 1 V
V

I(PP)

= 1 V
AV = 1
RL = 100 kΩ
CL = 20 pF

0.2

TA – Free-Air Temperature – °C

SLEW RATE

vs

FREE-AIR TEMPERATURE

SR – Slew Rate – V/us

sµV/

TLV2332, TLV2332Y, TLV2334, TLV2334Y
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TYPICAL CHARACTERISTICS

Figure 27

1 10 100 1000

3

2

1

0

4

5

f – Frequency – kHz

MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE

vs

FREQUENCY

RL = 100 kΩ

VDD = 3 V

TA = 85°C

TA = 25°C

VDD = 5 V

– Maximum Peak-to-Peak Output Voltage – V

V

O(PP)

TA = – 40°C

Figure 28

600

400

300

200

800

900

700

500

1000

012345678

B1 – Unity-Gain Bandwidth – kHz

B

1

VI = 10 mV
RL = 100 kΩ
CL = 20 pF
TA = 25°C

UNITY-GAIN BANDWIDTH

vs

SUPPLY VOLTAGE

VDD – Supply Voltage – V

Figure 29

–75 –50 –25 0 25 50 75 100 125

B1 – Unity-Gain Bandwidth – kHz

600

400

300

200

800

900

1000

700

500

B

1

VDD = 5 V

VDD = 3 V

VI = 10 mV
RL = 100 kΩ
CL = 20 pF

UNITY-GAIN BANDWIDTH

vs

FREE-AIR TEMPERATURE

TA – Free-Air Temperature – °C

TLV2332, TLV2332Y, TLV2334, TLV2334Y

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TYPICAL CHARACTERISTICS

Figure 30

VDD – Supply Voltage – V

xm – Phase Margin

0123456

PHASE MARGIN

vs

SUPPLY VOLTAGE

78

V

I

= 10 mV
RL = 100 kΩ
CL = 20 pF
TA = 25°C

φ

m

50°

48°
46°
44°
42°
40°
38°
36°

34°
32°
30°

Figure 31

TA – Free-Air Temperature – °C

– 75 – 25 0 50 100 125–50 25 75

VDD = 3 V

VI = 10 mV
RL = 100 kΩ
CL = 20 pF

PHASE MARGIN

vs

FREE-AIR TEMPERATURE

xm – Phase Margin

φ

m

45°

43°

43°

39°

37°

35°

VDD = 5 V

Figure 32

CL – Load Capacitance – pF

0204060

PHASE MARGIN

vs

LOAD CAPACITANCE

80 100

VI = 10 mV
RL = 100 KΩ
TA = 25°C

VDD = 3 V

VDD = 5 V

xm – Phase Margin

φ

m

44°

42°

40°

38°

36°

34°

32°

30°

28°

Figure 33

Vn – Equivalent Input Noise Voltage – nVxHz

200

150

100

0

110

250

f – Frequency – Hz

EQUIVALENT INPUT NOISE VOLTAGE

vs

FREQUENCY

300

1000100

V

n

nV/

Hz

RS = 20 Ω
TA = 25°C

VDD = 3 V

50

VDD = 5 V

TLV2332, TLV2332Y, TLV2334, TLV2334Y
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PARAMETER MEASUREMENT INFORMATION

single-supply versus split-supply test circuits

Because the TL V233x is optimized for single-supply operation, circuit configurations used for the various tests
often present some inconvenience since the input signal, in many cases, must be offset from ground. This
inconvenience can be avoided by testing the device with split supplies and the output load tied to the negative
rail. A comparison of single-supply versus split-supply test circuits is shown below. The use of either circuit gives
the same result.

–
+

–
+

V

DD

V

O

R

L

C

L

V

I

R

L

C

L

V

O

V

DD+

V

I

V

DD–

(a) SINGLE SUPPLY (b) SPLIT SUPPLY

Figure 34. Unity-Gain Amplifier

–
+

–
+

V

DD

V

DD+

V

DD–

V

O

V

O

(a) SINGLE SUPPLY (b) SPLIT SUPPLY

20 Ω

20 Ω

20 Ω

20 Ω

1/2 V

DD

2 kΩ

2 kΩ

Figure 35. Noise-Test Circuit

–
+

–
+

10 kΩ

1/2 V

DD

100 Ω

V

O

V

DD

V

I

V

I

100 Ω

(a) SINGLE SUPPLY (b) SPLIT SUPPLY

10 kΩ

V

DD+

V

DD–

C

L

C

L

V

O

Figure 36. Gain-of-100 Inverting Amplifier

TLV2332, TLV2332Y, TLV2334, TLV2334Y

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PARAMETER MEASUREMENT INFORMATION

input bias current

Because of the high input impedance of the TL V233x operational amplifier , attempts to measure the input bias
current can result in erroneous readings. The bias current at normal ambient temperature is typically less than
1 pA, a value that is easily exceeded by leakages on the test socket. Two suggestions are offered to avoid
erroneous measurements:

• Isolate the device from other potential leakage sources. Use a grounded shield around and between the

device inputs (see Figure 37). Leakages that would otherwise flow to the inputs are shunted away.

• Compensate for the leakage of the test socket by actually performing an input bias current test (using a

picoammeter) with no device in the test socket. The actual input bias current can then be calculated by
subtracting the open-socket leakage readings from the readings obtained with a device in the test
socket.

Many automatic testers as well as some bench-top operational amplifier testers use the servo-loop
technique with a resistor in series with the device input to measure the input bias current (the voltage
drop across the series resistor is measured and the bias current is calculated). This method requires
that a device be inserted into a test socket to obtain a correct reading; therefore, an open-socket reading
is not feasible using this method.

V = V

IC

8

5

14

Figure 37. Isolation Metal Around Device Inputs (P package)

low-level output voltage

To obtain low-level supply-voltage operation, some compromise is necessary in the input stage. This
compromise results in the device low-level output voltage being dependent on both the common-mode input
voltage level as well as the differential input voltage level. When attempting to correlate low-level output
readings with those quoted in the electrical specifications, these two conditions should be observed. If
conditions other than these are to be used, please refer to the Typical Characteristics section of this data sheet.

input offset voltage temperature coefficient

Erroneous readings often result from attempts to measure temperature coefficient of input offset voltage. This
parameter is actually a calculation using input offset voltage measurements obtained at two different
temperatures. When one (or both) of the temperatures is below freezing, moisture can collect on both the device
and the test socket. This moisture results in leakage and contact resistance which can cause erroneous input
offset voltage readings. The isolation techniques previously mentioned have no effect on the leakage since the
moisture also covers the isolation metal itself, thereby rendering it useless. These measurements should be
performed at temperatures above freezing to minimize error.

full-power response

Full-power response, the frequency above which the operational amplifier slew rate limits the output voltage
swing, is often specified two ways: full-linear response and full-peak response. The full-linear response is

TLV2332, TLV2332Y, TLV2334, TLV2334Y
LinCMOS LOW-VOLTAGE MEDIUM-POWER
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PARAMETER MEASUREMENT INFORMATION

generally measured by monitoring the distortion level of the output while increasing the frequency of a sinusoidal
input signal until the maximum frequency is found above which the output contains significant distortion. The
full-peak response is defined as the maximum output frequency , without regard to distortion, above which full
peak-to-peak output swing cannot be maintained.

Because there is no industry-wide accepted value for significant distortion, the full-peak response is specified
in this data sheet and is measured using the circuit of Figure 34. The initial setup involves the use of a sinusoidal
input to determine the maximum peak-to-peak output of the device (the amplitude of the sinusoidal wave is
increased until clipping occurs). The sinusoidal wave is then replaced with a square wave of the same
amplitude. The frequency is then increased until the maximum peak-to-peak output can no longer be maintained
(Figure 38). A square wave is used to allow a more accurate determination of the point at which the maximum
peak-to-peak output is reached.

(d) f > B

OM

(c) f = B

OM

(b) BOM > f > 100 Hz(a) f = 100 Hz

Figure 38. Full-Power-Response Output Signal

test time

Inadequate test time is a frequent problem, especially when testing CMOS devices in a high-volume,
short-test-time environment. Internal capacitances are inherently higher in CMOS than in bipolar and BiFET
devices and require longer test times than their bipolar and BiFET counterparts. The problem becomes more
pronounced with reduced supply levels and lower temperatures.

APPLICATION INFORMATION

single-supply operation

While the TLV233x performs well using dual­power supplies (also called balanced or split
supplies), the design is optimized for single­supply operation. This includes an input common­mode voltage range that encompasses ground as
well as an output voltage range that pulls down to
ground. The supply voltage range extends down
to 2 V, thus allowing operation with supply levels
commonly available for TTL and HCMOS.

Many single-supply applications require that a
voltage be applied to one input to establish a
reference level that is above ground. This virtual
ground can be generated using two large
resistors, but a preferred technique is to use a
virtual-ground generator such as the TLE2426
(see Figure 39).

–
+

TLE2426

V

O

V

I

R1

R2

V

DD

Figure 39. Inverting Amplifier With Voltage

Reference

V

O

+ ǒ

VDD–V

I

2

Ǔ

R2
R1

)

V

DD

2

TLV2332, TLV2332Y, TLV2334, TLV2334Y

LinCMOS LOW-VOLTAGE MEDIUM-POWER

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APPLICATION INFORMATION

single-supply operation (continued)

The TLE2426 supplies an accurate voltage equal to VDD/2, while consuming very little power and is suitable
for supply voltages of greater than 4 V . The TL V233x works well in conjunction with digital logic; however , when
powering both linear devices and digital logic from the same power supply, the following precautions are
recommended:

• Power the linear devices from separate bypassed supply lines (see Figure 40); otherwise, the linear

device supply rails can fluctuate due to voltage drops caused by high switching currents in the digital
logic.

• Use proper bypass techniques to reduce the probability of noise-induced errors. Single capacitive

decoupling is often adequate; however, RC decoupling may be necessary in high-frequency
applications.

–
+

Logic Logic Logic

Power
Supply

–
+

Logic Logic Logic

Power
Supply

(a) COMMON-SUPPLY RAILS

(b) SEPARATE-BYPASSED SUPPLY RAILS (preferred)

Figure 40. Common Versus Separate Supply Rails

input characteristics

The TL V233x is specified with a minimum and a maximum input voltage that, if exceeded at either input, could
cause the device to malfunction. Exceeding this specified range is a common problem, especially in
single-supply operation. The lower the range limit includes the negative rail, while the upper range limit is
specified at V

DD

– 1 V at TA = 25°C and at VDD – 1.2 V at all other temperatures.

The use of the polysilicon-gate process and the careful input circuit design gives the TL V233x very good input
offset voltage drift characteristics relative to conventional metal-gate processes. Offset voltage drift in CMOS
devices is highly influenced by threshold voltage shifts caused by polarization of the phosphorus dopant
implanted in the oxide. Placing the phosphorus dopant in a conductor (such as a polysilicon gate) alleviates the
polarization problem, thus reducing threshold voltage shifts by more than an order of magnitude. The offset
voltage drift with time has been calculated to be typically 0.1 µV/month, including the first month of operation.

Because of the extremely high input impedance and resulting low bias-current requirements, the TLV233x is
well suited for low-level signal processing; however, leakage currents on printed-circuit boards and sockets can
easily exceed bias-current requirements and cause a degradation in device performance.

–
+

Figure 42. Compensation for Input Capacitance

TLV2332, TLV2332Y, TLV2334, TLV2334Y
LinCMOS LOW-VOLTAGE MEDIUM-POWER
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APPLICATION INFORMATION

input characteristics (continued)

It is good practice to include guard rings around inputs (similar to those of Figure 37 in the Parameter
Measurement Information section). These guards should be driven from a low-impedance source at the same
voltage level as the common-mode input (see Figure 41).

The inputs of any unused amplifiers should be tied to ground to avoid possible oscillation.

–
+

–
+

–
+

V

O

V

I

V

I

V

O

V

I

V

O

(a) NONINVERTING AMPLIFIER (b) INVERTING AMPLIFIER (c) UNITY-GAIN AMPLIFIER

Figure 41. Guard-Ring Schemes

noise performance

The noise specifications in operational amplifiers circuits are greatly dependent on the current in the first-stage
differential amplifier . The low input bias-current requirements of the TLV233x results in a very low noise current,
which is insignificant in most applications. This feature makes the device especially favorable over bipolar
devices when using values of circuit impedance greater than 50 kΩ, since bipolar devices exhibit greater noise
currents.

feedback

Operational amplifiers circuits nearly always
employ feedback, and since feedback is the first
prerequisite for oscillation, caution is appropriate.
Most oscillation problems result from driving
capacitive loads and ignoring stray input
capacitance. A small-value capacitor connected
in parallel with the feedback resistor is an effective
remedy (see Figure 42). The value of this
capacitor is optimized empirically.

electrostatic-discharge protection

The TLV233x incorporates an internal electrostatic-discharge (ESD)-protection circuit that prevents functional
failures at voltages up to 2000 V as tested under MIL-PRF-38535. Method 3015.2. Care should be exercised,
however, when handling these devices as exposure to ESD may result in the degradation of the device
parametric performance. The protection circuit also causes the input bias currents to be temperature dependent
and have the characteristics of a reverse-biased diode.

Figure 43. Resistive Pullup to Increase V

OH

–
+

RP+

VDD*

V

O

IF)

IL)

I

P

IP = Pullup Current
Required by the
Operational Amplifier
(typically 500 µA)

V

O

V

DD

R

P

I

P

I

F

I

L

R

L

V

I

R1

R2

–
+

V

O

C

L

V

I

2.5 V

TA = 25°C
f = 1 kHz
V

I(PP)

= 1 V

–2.5 V

Figure 44. Test Circuit for Output Characteristics

TLV2332, TLV2332Y, TLV2334, TLV2334Y

LinCMOS LOW-VOLTAGE MEDIUM-POWER

OPERATIONAL AMPLIFIERS

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APPLICATION INFORMATION

latch-up

Because CMOS devices are susceptible to latch-up due to their inherent parasitic thyristors, the TL V233x inputs
and outputs are designed to withstand –100-mA surge currents without sustaining latch-up; however,
techniques should be used to reduce the chance of latch-up whenever possible. Internal-protection diodes
should not by design be forward biased. Applied input and output voltage should not exceed the supply voltage
by more than 300 mV . Care should be exercised when using capacitive coupling on pulse generators. Supply
transients should be shunted by the use of decoupling capacitors (0.1 µF typical) located across the supply rails
as close to the device as possible.

The current path established if latch-up occurs is usually between the positive supply rail and ground and can
be triggered by surges on the supply lines and/or voltages on either the output or inputs that exceed the supply
voltage. Once latch-up occurs, the current flow is limited only by the impedance of the power supply and the
forward resistance of the parasitic thyristor and usually results in the destruction of the device. The chance of
latch-up occurring increases with increasing temperature and supply voltages.

output characteristics

The output stage of the TLV233x is designed to
sink and source relatively high amounts of current
(see Typical Characteristics). If the output is
subjected to a short-circuit condition, this high­current capability can cause device damage
under certain conditions. Output current capability
increases with supply voltage.

Although the TLV233x possesses excellent
high-level output voltage and current capability,
methods are available for boosting this capability
if needed. The simplest method involves the use
of a pullup resistor (R

P

) connected from the output
to the positive supply rail (see Figure 43). There
are two disadvantages to the use of this circuit.
First, the NMOS pulldown transistor N4 (see
equivalent schematic) must sink a comparatively
large amount of current. In this circuit, N4 behaves
like a linear resistor with an on resistance between
approximately 60 Ω and 180 Ω, depending on
how hard the operational amplifier input is driven.
With very low values of R

P

, a voltage offset from
0 V at the output occurs. Secondly , pullup resistor
R

P

acts as a drain load to N4 and the gain of the
operational amplifier is reduced at output voltage
levels where N5 is not supplying the output
current.

All operating characteristics of the TLV233x are measured using a 20-pF load. The device drives higher
capacitive loads; however, as output load capacitance increases, the resulting response pole occurs at lower
frequencies thereby causing ringing, peaking, or even oscillation (see Figure 44 and Figure 45). In many cases,
adding some compensation in the form of a series resistor in the feedback loop alleviates the problem.

TLV2332, TLV2332Y, TLV2334, TLV2334Y
LinCMOS LOW-VOLTAGE MEDIUM-POWER
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APPLICATION INFORMATION

output characteristics (continued)

(a) CL = 20 pF, RL = NO LOAD (b) CL = 170 pF, RL = NO LOAD (c) CL = 190 pF, RL = NO LOAD

Figure 45. Effect of Capacitive Loads

TLV2332, TLV2332Y, TLV2334, TLV2334Y

LinCMOS LOW-VOLTAGE MEDIUM-POWER

OPERATIONAL AMPLIFIERS

SLOS189 – FEBRUARY 1997

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MECHANICAL INFORMATION

D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PIN SHOWN

4040047/B 03/95

0.228 (5,80)

0.244 (6,20)

0.069 (1,75) MAX

0.010 (0,25)

0.004 (0,10)

1

14

0.014 (0,35)

0.020 (0,51)

A

0.157 (4,00)

0.150 (3,81)

7

8

0.044 (1,12)

0.016 (0,40)

Seating Plane

0.010 (0,25)

PINS **

0.008 (0,20) NOM

A MIN

A MAX

DIM

Gage Plane

0.189

(4,80)

(5,00)

0.197

8

(8,55)

(8,75)

0.337

14

0.344

(9,80)

16

0.394

(10,00)

0.386

0.004 (0,10)

M

0.010 (0,25)

0.050 (1,27)

0°–8°

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Four center pins are connected to die mount pad.

E. Falls within JEDEC MS-012

TLV2332, TLV2332Y, TLV2334, TLV2334Y
LinCMOS LOW-VOLTAGE MEDIUM-POWER
OPERATIONAL AMPLIFIERS

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MECHANICAL INFORMATION

N (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE

20

0.975

(24,77)

0.940

(23,88)

18

0.920

0.850

14

0.775

0.745

(19,69)

(18,92)

16

0.775

(19,69)

(18,92)

0.745

A MIN

DIM

A MAX

PINS **

0.310 (7,87)

0.290 (7,37)

(23.37)

(21.59)

Seating Plane

0.010 (0,25) NOM

14/18 PIN ONL Y

4040049/C 08/95

9

8

0.070 (1,78) MAX

A

0.035 (0,89) MAX

0.020 (0,51) MIN

16

1

0.015 (0,38)

0.021 (0,53)

0.200 (5,08) MAX

0.125 (3,18) MIN

0.240 (6,10)

0.260 (6,60)

M

0.010 (0,25)

0.100 (2,54)

0°–15°

16 PIN SHOWN

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001 (20 pin package is shorter then MS-001.)

TLV2332, TLV2332Y, TLV2334, TLV2334Y

LinCMOS LOW-VOLTAGE MEDIUM-POWER

OPERATIONAL AMPLIFIERS

SLOS189 – FEBRUARY 1997

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MECHANICAL INFORMATION

P (R-PDIP-T8) PLASTIC DUAL-IN-LINE PACKAGE

4040082/B 03/95

0.310 (7,87)

0.290 (7,37)

0.010 (0,25) NOM

0.400 (10,60)

0.355 (9,02)

58

41

0.020 (0,51) MIN

0.070 (1,78) MAX

0.240 (6,10)

0.260 (6,60)

0.200 (5,08) MAX

0.125 (3,18) MIN

0.015 (0,38)

0.021 (0,53)

Seating Plane

M

0.010 (0,25)

0.100 (2,54)

0°–15°

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001

TLV2332, TLV2332Y, TLV2334, TLV2334Y
LinCMOS LOW-VOLTAGE MEDIUM-POWER
OPERATIONAL AMPLIFIERS

SLOS189 – FEBRUARY 1997

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MECHANICAL INFORMATION

PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

4040064/D 10/95

14 PIN SHOWN

Seating Plane

0,10 MIN

1,20 MAX

1

A

7

14

0,19

4,50
4,30

8

6,10

6,70

0,32

0,75
0,50

0,25

Gage Plane

0,15 NOM

0,65

M

0,13

0°–8°

0,10

PINS **

A MIN

A MAX

DIM

2,90

3,10

8

4,90

5,10

14

6,60

6,404,90

5,10

16

7,70

20

7,90

24

9,60

9,80

28

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153

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