TEXAS INSTRUMENTS TLV2332, TLV2332Y, TLV2334, TLV2334Y Technical data

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VIOmax

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40°C to 85°C

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TLV2332, TLV2332Y, TLV2334, TLV2334Y

LinCMOS LOW-VOLTAGE MEDIUM-POWER

OPERATIONAL AMPLIFIERS

SLOS189 – FEBRUARY 1997

Wide Range of Supply Voltages Over Specified Temperature Range:

= –40°C to 85°C...2 V to 8 V

Fully Characterized at 3 V and 5 V

Single-Supply Operation

Common-Mode Input-Voltage Range Extends Below the Negative Rail and up to V

–1 V at TA = 25°C

Output Voltage Range Includes Negative Rail

High Input Impedance...10

ESD-Protection Circuitry

Designed-In Latch-Up Immunity

Ω Typ

description

The TL V233x operational amplifiers are in a family of devices that has been specifically designed for use in low-voltage single-supply applications. Unlike the TLV2322 which is optimized for ultra-low power, the TLV233x is designed to provide a combination of low power and good ac performance. Each amplifier is fully functional down to a minimum supply voltage of 2 V, is fully characterized, tested, and specified at both 3-V and 5-V power supplies. The common-mode input-voltage range includes the negative rail and extends to within 1 V of the positive rail.

Having a maximum supply current of only 310 µA per amplifier over full temperature range, the TLV233x devices offer a combination of good ac performance and microampere supply currents. From a 3-V power supply, the amplifier’s typical slew rate is 0.38 V/µs and its bandwidth is 300 kHz.

DD –

DD–

1OUT

/GND

1OUT

/GND

1IN–

1IN+

1OUT

1IN– 1IN+

DD+

2IN+ 2IN–

2OUT

TLV2332

D OR P PACKAGE

(TOP VIEW)

1IN– 1IN+

1OUT

1IN– 1IN+

2IN+

2OUT

2 3 4

TLV2332

PW PACKAGE

(TOP VIEW)

1 2 3 4

TLV2334

D OR N PACKAGE

(TOP VIEW)

1 2 3 4

DD+

2N–

6 7

TLV2334

PW PACKAGE

(TOP VIEW)

8 7 6 5

14 13 12 11 10

9 8

2OUT 2IN– 2IN+

DD+

2OUT 2IN– 2IN+

4OUT 4IN– 4IN+ V

DD–/GND

3IN+ 3IN– 3OUT

4OUT 4IN– 4IN+ V

DD–/GND

3IN+ 3IN– 3OUT

–

†

The D package is available taped and reeled. Add R suffix to the device type (e.g., TL V2332IDR).

‡

The PW package is only available left-end taped and reeled (e.g., TLV2332IPWLE).

Chip forms are tested at 25°C only.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

LinCMOS is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

AT 25°C

9 mV TLV2332ID — TLV2332IP TLV2332IPWLE TLV2332Y

10 mV TLV2334ID TLV2334IN — TLV2334IPWLE TLV2334Y

SMALL OUTLINE

AVAILABLE OPTIONS

PACKAGED DEVICES

†

PLASTIC DIP

(D)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(N)

PLASTIC DIP

(P)

‡

TSSOP

(PW)

(Y)

TLV2332, TLV2332Y, TLV2334, TLV2334Y LinCMOS LOW-VOLTAGE MEDIUM-POWER OPERATIONAL AMPLIFIERS

SLOS189 – FEBRUARY 1997

description (continued)

These amplifiers offer a level of ac performance greater than that of many other devices operating at comparable power levels. The TL V233x operational amplifiers are especially well suited for use in low-current or battery-powered applications.

Low-voltage and low-power operation has been made possible by using the Texas Instruments silicon-gate LinCMOS technology . The LinCMOS process also features extremely high input impedance and ultra-low bias currents making these amplifiers ideal for interfacing to high-impedance sources such as sensor circuits or filter applications.

T o facilitate the design of small portable equipment, the TLV233x is made available in a wide range of package options, including the small-outline and thin-shrink small-outline package (TSSOP). The TSSOP package has significantly reduced dimensions compared to a standard surface-mount package. Its maximum height of only

1.1 mm makes it particularly attractive when space is critical. The device inputs and outputs are designed to withstand –100-mA currents without sustaining latch-up. The

TLV233x incorporates internal ESD-protection circuits that prevents functional failures at voltages up to 2000 V as tested under MIL-STD 883C, Method 3015.2; however, care should be exercised in handling these devices as exposure to ESD may result in the degradation of the device parametric performance.

TLV2332Y chip information

This chip, when properly assembled, display characteristics similar to the TLV2332. Thermal compression or ultrasonic bonding may be used on the doped-aluminum bonding pads. Chips may be mounted with conductive epoxy or a gold-silicon preform.

BONDING PAD ASSIGNMENTS

(7)

(5)

(6)

(4)

(8)

(3)

(2)

(1)

(3)

1IN+

(2)

1IN–

2OUT

CHIP THICKNESS: 15 MILS TYPICAL BONDING PADS: 4 × 4 MILS MINIMUM TJmax = 150°C TOLERANCES ARE ±10%. ALL DIMENSIONS ARE IN MILS. PIN (4) IS INTERNALLY CONNECTED

TO BACKSIDE OF CHIP.

(7)

(8)

–

DD–

(4)

+ –

/GND

(1)

(5)

(6)

1OUT

2IN+

2IN–

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV2332, TLV2332Y, TLV2334, TLV2334Y

LinCMOS LOW-VOLTAGE MEDIUM-POWER

OPERATIONAL AMPLIFIERS

SLOS189 – FEBRUARY 1997

TLV2334Y chip information

This chip, when properly assembled, displays characteristics similar to the TL V2334. Thermal compression or ultrasonic bonding may be used on the doped-aluminum bonding pads. Chips may be mounted with conductive epoxy or a gold-silicon preform.

BONDING PAD ASSIGNMENTS

(8)(9)(10)(11)(12)(13)(14)

(1) (2) (3) (4) (5) (6) (7)

108

–

DD–

(4)

(11)

/GND

(1)

(7)

(8)

(14)

1OUT

2OUT

3OUT

4OUT

(3)

1IN+

(2)

1IN–

(5)

2IN+

(6)

2IN–

(10)

3IN+

(9)

3IN–

(12)

4IN+

(13)

4IN–

CHIP THICKNESS: 15 MILS TYPICAL BONDING PADS: 4 × 4 MILS MINIMUM TJmax = 150°C TOLERANCES ARE ±10%. ALL DIMENSIONS ARE IN MILS.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV2332, TLV2332Y, TLV2334, TLV2334Y LinCMOS LOW-VOLTAGE MEDIUM-POWER OPERATIONAL AMPLIFIERS

SLOS189 – FEBRUARY 1997

equivalent schematic (each amplifier)

IN–

IN+

GND

OUT

ACTUAL DEVICE COMPONENT COUNT

COMPONENT TLV2332 TLV2334

Transistors 54 108 Resistors 14 28 Diodes 4 8 Capacitors 2 4

†

Includes both amplifiers and all ESD, bias, and trim circuitry.

†

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV2332, TLV2332Y, TLV2334, TLV2334Y

PACKAGE

Common-mode input voltage, V

LinCMOS LOW-VOLTAGE MEDIUM-POWER

OPERATIONAL AMPLIFIERS

SLOS189 – FEBRUARY 1997

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Supply voltage, V Differential input voltage, V Input voltage range, V Input current, I Output current, I Duration of short-circuit current at (or below) T

(see Note 1) 8 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

±5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

±30 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(see Note 2) V

(any input) –0.3 V to V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

= 25°C (see Note 3) unlimited. . . . . . . . . . . . . . . . . . . . . . . . .

†

Continuous total dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T

–40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. All voltage values, except differential voltages, are with respect to network ground.

2. Differential voltages are at the noninverting input with respect to the inverting input.

3. The output may be shorted to either supply. Temperature and /or supply voltages must be limited to ensure that the maximum dissipation rating is not exceeded (see application section).

DISSIPATION RATING T ABLE

≤ 25°C DERATING FACTOR T

POWER RATING ABOVE TA = 25°C

D–8 725 mW 5.8 mW/°C 377 mW

D–14 950 mW 7.6 mW/°C 494 mW

N 1575 mW 12.6 mW/°C 819 mW P 1000 mW 8.0 mW/°C 520 mW

PW–8 525 mW 4.2 mW/°C 273 mW

PW–14 700 mW 5.6 mW/°C 364 mW

= 85°C

POWER RATING

DD±

recommended operating conditions

Supply voltage, V

Operating free-air temperature, T

VDD = 3 V –0.2 1.8 VDD = 5 V –0.2 3.8

MIN MAX UNIT

2 8 V

–40 85 °C

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV2332, TLV2332Y, TLV2334, TLV2334Y

TEST

†

CONDITIONS

VIOInput offset voltage

IIOInput offset current (see Note 4)

IIBInput bias current (see Note 4)

25°C

VOHHigh-level output voltage

100 mV

VOLLow-level output voltage

100 mV

100 kΩ

V/mV

CMRR

Common-mode rejection ratio

ygj

1 V

IDDSupply current

LinCMOS LOW-VOLTAGE MEDIUM-POWER OPERATIONAL AMPLIFIERS

SLOS189 – FEBRUARY 1997

TLV2332I electrical characteristics at specified free-air temperature

TLV2332I

PARAMETER

VO = 1 V, V

†

Full range is –40°C to 85°C.

NOTES: 4. The typical values of input bias current and input offset current below 5 pA are determined mathematically .

Average temperature coefficient of

VIO

input offset voltage

Common-mode input

ICR

voltage range (see Note 5)

Large-signal differential

voltage amplification

Supply-voltage rejection ratio

SVR

(∆VDD/∆VIO)

5. This range also applies to each input individually.

6. At VDD = 5 V, VO = 0.25 V to 2 V; at VDD = 3 V, VO = 0.5 V to 1.5 V.

= 1 V, RS = 50 Ω, RL = 100 kΩ

= 1 V,

VIC = 1 V V

= 1 V,

VIC = 1 V

VIC = 1 V,

IOH = –1 mA VIC = 1 V,

= –

IOL = 1 mA VIC = 1 V,

See Note 6 VO = 1 V,

ICR

RS = 50 Ω VIC = 1 V,

RS = 50 Ω VO = 1 V,

No load

= 1 V,

min,

25°C 0.6 9 1.1 9

Full range 11 11

25°C to

85°C 25°C 0.1 0.1 85°C 22 1000 24 1000 25°C 0.6 0.6 85°C 175 2000 200 2000

Full range

25°C 1.75 1.9 3.2 3.9

Full range 1.7 3

25°C 115 150 95 150

Full range 190 190

25°C 25 83 25 170

Full range 15 15

25°C 65 92 65 91

Full range 60 60

25°C 70 94 70 94

Full range 65 65

25°C 160 500 210 560

Full range 620 800

VDD = 3 V VDD = 5 V

MIN TYP MAX MIN TYP MAX

1 1.7 µV/°C

–0.2

1.8

–0.3

2.3

–0.2

3.8

–0.3 o 4

UNIT

4.2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV2332, TLV2332Y, TLV2334, TLV2334Y

PARAMETER

TEST CONDITIONS

UNIT

Slew rate at unity gain

100 kΩ

V/µs

BOMMaximum output-swing bandwidth

OOH

B1Unity-gain bandwidth

mV,

f B1,

PARAMETER

TEST CONDITIONS

UNIT

Slew rate at unity gain

V/µs

BOMMaximum output-swing bandwidth

OOH

B1Unity-gain bandwidth

mV,

f B1,

LinCMOS LOW-VOLTAGE MEDIUM-POWER

OPERATIONAL AMPLIFIERS

TLV2332I operating characteristics at specified free-air temperature, VDD = 3 V

VIC = 1 V,

See Figure 34

Equivalent input noise voltage

Phase margin

f =1 kHz, See Figure 35

= V

RL = 100 kΩ, V

= 10 mV, C

RL = 100 kΩ, V

= 10 mV

10 CL = 20 pF, See Figure 36

, C

= 1 V,

I(PP)

= 20 F,

RS = 20 Ω,

= 20 pF,

See Figure 34

= 20 pF,

See Figure 36 f = B

RL = 100 kΩ,

25°C 0.38 85°C

25°C 32 25°C 34

85°C 25°C 300 85°C 235

–40°C 42°

25°C 85°C 36°

TLV2332I operating characteristics at specified free-air temperature, VDD = 5 V

= 1 V, RL = 100 kΩ, CL = 20 pF, See Figure 34

Equivalent input noise voltage

Phase margin

f =1 kHz, See Figure 35

= V

, C

RL = 100 kΩ, V

= 10 mV, C

RL = 100 kΩ, V

= 10 mV

10 CL = 20 pF, See Figure 36

= 1

I(PP)

= 2.5

I(PP)

RS = 20 Ω,

= 20 pF,

See Figure 34

= 20 pF,

See Figure 36 f = B

RL = 100 kΩ,

25°C 0.43 85°C 0.35 25°C 0.40 85°C 0.32

25°C 32 25°C 55

85°C 25°C 525 85°C

–40°C 43°

25°C 85°C 38°

MIN TYP MAX

SLOS189 – FEBRUARY 1997

TLV2332I

0.29

nV/√Hz

39°

TLV2332I

nV/√Hz

370

40°

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV2332, TLV2332Y, TLV2334, TLV2334Y

†

VIOInput offset voltage

50 Ω

IIOInput offset current (see Note 4)

IIBInput bias current (see Note 4)

1 V

25°C

VOHHigh-level output voltage

100 mV

VOLLow-level output voltage

100 mV

100 kΩ

V/mV

CMRR

Common-mode rejection ratio

ygj

1 V

IDDSupply current

OIC

LinCMOS LOW-VOLTAGE MEDIUM-POWER OPERATIONAL AMPLIFIERS

SLOS189 – FEBRUARY 1997

TLV2334I electrical characteristics at specified free-air temperature

TLV2334I

PARAMETER TEST CONDITIONS

†

Full range is –40°C to 85°C.

NOTES: 4. The typical values of input bias current and input offset current below 5 pA are determined mathematically.

Average temperature coefficient

VIO

of input offset voltage

Common-mode input voltage

ICR

range (see Note 5)

Large-signal differential

voltage amplification

Supply-voltage rejection ratio

SVR

(∆VDD/∆VIO)

5. This range also applies to each input individually.

6. At VDD = 5 V, VO = 0.25 V to 2 V; at VDD = 3 V, VO = 0.5 V to 1.5 V.

VO = 1 V, VIC = 1 V,

RL = 100 kΩ

VIC = 1 V,

IOH = –1 mA VIC = 1 V,

IOL = 1 mA VIC = 1 V,

See Note 6 VO = 1 V,

RS = 50 Ω VDD = 3 V to 5 V,

RS = 50 Ω VO = 1 V, VIC = 1 V,

No load

= 1 V,

= –

ICR

= 1

min,

25°C 0.6 10 1.1 10

Full range 12 12

25°C to

85°C 25°C 0.1 0.1 85°C 22 1000 24 1000 25°C 0.6 0.6 85°C 175 2000 200 2000

Full range

25°C 1.75 1.9 3.2 3.9

Full range 1.7 3

25°C 115 150 95 150

Full range 190 190

25°C 25 83 25 170

Full range 15 15

25°C 65 92 65 91

Full range 60 60

25°C 70 94 70 94

Full range 65 65

25°C 320 1000 420 1120

Full range 1200 1600

VDD = 3 V VDD = 5 V

MIN TYP MAX MIN TYP MAX

1 1.7 µV/°C

–0.2

1.8

–0.3

2.3

–0.2

o 4

–0.2

3.8

UNIT

–0.3

4.2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV2332, TLV2332Y, TLV2334, TLV2334Y

PARAMETER

TEST CONDITIONS

UNIT

Slew rate at unity gain

100 kΩ

V/µs

BOMMaximum output-swing bandwidth

OOH

B1Unity-gain bandwidth

mV,

100 kΩ

PARAMETER

TEST CONDITIONS

UNIT

Slew rate at unity gain

V/µs

BOMMaximum output-swing bandwidth

OOH

B1Unity-gain bandwidth

mV,

f B1,

LinCMOS LOW-VOLTAGE MEDIUM-POWER

OPERATIONAL AMPLIFIERS

TLV2334I operating characteristics at specified free-air temperature, VDD = 3 V

VIC = 1 V,

See Figure 34

Equivalent input noise voltage

Phase margin

f = 1 kHz, See Figure 35

= V

RL = 100 kΩ, V

= 10 mV, C RL = 100 kΩ,

= 10 mV

10 CL = 20 pF, See Figure 36

, C

= 1 V,

I(PP)

= 20 F,

RS = 20 Ω,

= 20 pF,

See Figure 34

= 20 pF,

See Figure 36

25°C 0.38 85°C

25°C 32 25°C 34

85°C 25°C 300 85°C

–40°C 42°

25°C 39° 85°C 36°

TLV2334I operating characteristics at specified free-air temperature, VDD = 5 V

= 1 V, RL = 100 kΩ, CL = 20 pF, See Figure 34

Equivalent input noise voltage

Phase margin

f = 1 kHz, See Figure 35

= V

, C

RL = 100 kΩ, V

= 10 mV, C

RL = 100 kΩ, V

= 10 mV

10 CL = 20 pF, See Figure 36

= 1

I(PP)

= 2.5

I(PP)

RS = 20 Ω,

= 20 pF,

See Figure 34

= 20 pF,

See Figure 36 f = B

RL = 100 kΩ,

25°C 0.43 85°C 0.35 25°C 0.40 85°C 0.32

25°C 32 25°C 55

85°C 25°C 525 85°C

–40°C 43°

25°C 40° 85°C 38°

MIN TYP MAX

SLOS189 – FEBRUARY 1997

TLV2334I

0.29

nV/√Hz

235

TLV2334I

nV/√Hz

370

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV2332, TLV2332Y, TLV2334, TLV2334Y LinCMOS LOW-VOLTAGE MEDIUM-POWER OPERATIONAL AMPLIFIERS

SLOS189 – FEBRUARY 1997

TLV2332Y electrical characteristics, T

PARAMETER TEST CONDITIONS

ICR

CMRR Common-mode rejection ratio

SVR

NOTES: 4. The typical values of input bias current and input offset current below 5 pA are determined mathematically .

Input offset voltage Input offset current (see Note 4) VO = 1 V, VIC = 1 V 0.1 0.1 pA

Input bias current (see Note 4) VO = 1 V, VIC = 1 V 0.6 0.6 pA Common-mode input voltage

range (see Note 5)

High-level output voltage

Low-level output voltage Large-signal differential voltage

amplification

Supply-voltage rejection ratio (∆VDD/∆VID)

Supply current

5. This range also applies to each input individually.

6. At VDD = 5 V, VO = 0.25 V to 2 V; at VDD = 3 V, VO = 0.5 V to 1.5 V.

VO = 1 V, RS = 50 Ω,

VIC = 1 V, IOH = –1 mA

VIC = 1 V, IOL = 1 mA

VIC = 1 V, See Note 6

VO = 1 V, RS = 50 Ω

VO = 1 V, No load

= 25°C

VIC = 1 V, RL = 100 kΩ

VID = 100 mV,

RL = 100 kΩ,

VIC = V

VIC = 1 V,

ICR

min,

TLV2332Y

VDD = 3 V VDD = 5 V

MIN TYP MAX MIN TYP MAX

0.6 1.1 mV

–0.3

2.3

1.9 3.9 V

115 95 mV

83 170 V/mV

92 91 dB

94 94 dB

160 210 µA

–0.3

4.2

UNIT

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV2332, TLV2332Y, TLV2334, TLV2334Y

LinCMOS LOW-VOLTAGE MEDIUM-POWER

OPERATIONAL AMPLIFIERS

SLOS189 – FEBRUARY 1997

TLV2334Y electrical characteristics, T

PARAMETER TEST CONDITIONS

V I

CMRR Common-mode rejection ratio

SVR

NOTES: 4. The typical values of input bias current offset current below 5 pA are determined mathematically.

Input offset voltage

Input offset current (see Note 4) VO = 1 V, VIC = 1 V 0.1 0.1 pA Input bias current (see Note 4) VO = 1 V, VIC = 1 V 0.6 0.6 pA

Common-mode input voltage

ICR

range (see Note 5)

High-level output voltage

Low-level output voltage

Large-signal differential voltage

amplification

Supply-voltage rejection ratio (∆VDD/∆VID)

Supply current

5. This range also applies to each input individually.

6. At VDD = 5 V, VO = 0.25 V to 2 V; at VDD = 3 V, VO = 0.5 V to 1.5 V.

VO = 1 V, RS = 50 Ω,

VIC = 1 V, IOH = –1 mA

VIC = 1 V, IOL = 1 mA

VIC = 1 V, See Note 6

VO = 1 V, RS = 50 Ω

VIC = 1 V, RS = 50 Ω

VO = 1 V, No load

= 25°C

VIC = 1 V RL = 100 kΩ

VID = 100 mV,

VID = –100 mV,

RL = 100 kΩ,

VIC = V

VO = 1 V,

VIC = 1 V,

ICR

min,

TLV2334Y

VDD = 3 V VDD = 5 V

MIN TYP MAX MIN TYP MAX

0.6 1.1 mV

–0.3

2.3

1.9 3.9 V

115 95 mV

83 170 V/mV

92 91 dB

94 94 dB

320 420 µA

–0.3

4.2

UNIT

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV2332, TLV2332Y, TLV2334, TLV2334Y LinCMOS LOW-VOLTAGE MEDIUM-POWER OPERATIONAL AMPLIFIERS

SLOS189 – FEBRUARY 1997

TYPICAL CHARACTERISTICS

Table of Graphs

SR Slew rate V

O(PP)

Input offset voltage Distribution 1 – 4

Input offset voltage temperature coefficient Distribution 5 – 8

VIO

Input bias current vs Free-air temperature 9 Input offset current vs Free-air temperature 9 Common-mode input voltage vs Supply voltage 10

High-level output voltage

Low-level output voltage

Large-signal differential voltage amplification

Supply current

Maximum peak-to-peak output voltage vs Frequency 27

Unity-gain bandwidth

Phase margin

Phase shift vs Frequency 21, 22 Equivalent input noise voltage vs Frequency 33

vs High-level output current vs Supply voltage vs Free-air temperature

vs Common-mode input voltage vs Free-air temperature vs Differential input voltage vs Low-level output current

vs Supply voltage vs Free-air temperature vs Frequency

vs Supply voltage vs Free-air temperature

vs Supply voltage vs Free-air temperature vs Load capacitance

FIGURE

11 12 13

15, 16

17 18

19 20

21, 22

23 24

25 26

28 29

30 31 32

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV2332, TLV2332Y, TLV2334, TLV2334Y

LinCMOS LOW-VOLTAGE MEDIUM-POWER

TYPICAL CHARACTERISTICS

OPERATIONAL AMPLIFIERS

SLOS189 – FEBRUARY 1997

DISTRIBUTION OF TLV2332

INPUT OFFSET VOLTAGE

VDD = 3 V TA = 25°C P Package

Percentage of Units – %

–5 –4 –3 –2 –1 0 1 2 3 4 5

VIO – Input Offset Voltage – mV

Figure 1

DISTRIBUTION OF TLV2334

INPUT OFFSET VOLTAGE

VDD = 3 V TA = 25°C N Package

DISTRIBUTION OF TLV2332

INPUT OFFSET VOLTAGE

VDD = 5 V TA = 25°C P Package

Percentage of Units – %

–5 –4 –3 –2 –1 0 1 2 3 4 5

VIO – Input Offset Voltage – mV

Figure 2

DISTRIBUTION OF TLV2334

INPUT OFFSET VOLTAGE

VDD = 5 V TA = 25°C N Package

Percentage of Units – %

–5 –4 –3 –2

VIO – Input Offset Voltage – mV

–1 0 1

Figure 3

Percentage of Units – %

2345

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

–5 –4 –3 –2

–1 0 1602345

VIO – Input Offset Voltage – mV

Figure 4

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TYPICAL CHARACTERISTICS

DISTRIBUTION OF TLV2332

INPUT OFFSET VOLTAGE

TEMPERATURE COEFFICIENT

VDD = 3 V TA = 25°C to 85°C P Package

Percentage of Units – %

–10–8–6–4–2 0 2 4 6 8 10

– Temperature Coefficient – µV/°C

VIO

Figure 5

DISTRIBUTION OF TLV2334

INPUT OFFSET VOLTAGE

TEMPERATURE COEFFICIENT

VDD = 3 V TA = 25°C to 85°C N Package

DISTRIBUTION OF TLV2332

INPUT OFFSET VOLTAGE

TEMPERATURE COEFFICIENT

VDD = 5 V TA = 25°C to 85°C

P Package Outliers: (1) 33 mV/°C

Percentage of Units – %

–10–8–6–4–20246810

– Temperature Coefficient – µV/°C

VIO

Figure 6

DISTRIBUTION OF TLV2334

INPUT OFFSET VOLTAGE

TEMPERATURE COEFFICIENT

VDD = 5 V TA = 25°C to 85°C N Package

Outliers: (1) 33 mV/°C

Percentage of Units – %

–10 –2 0 2

–8 –6 –4

VIO

46810

– Temperature Coefficient – µV/°C

Figure 7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Percentage of Units – %

–8 –6 –4

–10 –2 0 2 4 6 8 10

– Temperature Coefficient – µV/°C

VIO

Figure 8

TLV2332, TLV2332Y, TLV2334, TLV2334Y

LinCMOS LOW-VOLTAGE MEDIUM-POWER

TYPICAL CHARACTERISTICS

OPERATIONAL AMPLIFIERS

SLOS189 – FEBRUARY 1997

INPUT BIAS CURRENT AND INPUT OFFSET CURREN

FREE-AIR TEMPERATURE

VDD = 3 V VIC = 1 V See Note A

0.1

IIB and IIO – Input Bias and Input Offset Currents – pA

25 45 65 85 105 125

TA – Free-Air Temperature – ° C

NOTE: The typical values of input bias current and input offset

current below 5 pA were determined mathematically.

Figure 9

COMMON-MODE INPUT VOLTAGE

SUPPLY VOLTAGE

TA = 25°C Positive Limit

VIC – Common-Mode Input Voltage – V

02468

– Supply Voltage – V

Figure 10

V0H – High-Level Output Voltage – V

HIGH-LEVEL OUTPUT VOLTAGE

HIGH-LEVEL OUTPUT CURRENT

VDD = 3 V

–2 –4 –6 –8

IOH – High-Level Output Current – mA

Figure 11

VIC = 1 V VID = 100 mV TA = 25°C

VDD = 5 V

HIGH-LEVEL OUTPUT VOLTAGE

SUPPLY VOLTAGE

VIC = 1 V VID = 100 mV RL = 100 kΩ TA = 25°C

V0H – High-Level Output Voltage – V

02468

VDD – Supply Voltage – V

Figure 12

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TYPICAL CHARACTERISTICS

HIGH-LEVEL OUTPUT VOLTAGE

FREE-AIR TEMPERATURE

VDD = 3 V VIC = 1 V VID = 100 mV

2.4

1.8

1.2 IOH = –500 µA

IOH = –1 mA IOH = –2 mA

0.6

V0H – High-Level Output Voltage – V

IOH = –3 mA IOH = –4 mA

0 –75 –50 –25 0 25 50 75 100 125

TA – Free-Air Temperature – ° C

Figure 13

LOW-LEVEL OUTPUT VOLTAGE

FREE-AIR TEMPERATURE

200

VDD = 3 V VIC = 1 V

185

VID = –100 mV

170

IOL = 1 mA

155

140 125

110

LOW-LEVEL OUTPUT VOLTAGE

COMMON-MODE INPUT VOLTAGE

700

650

600

550

VID = –100 mV

500

450

400

VID = –1 V

350

VOL – Low-Level Output Voltage – mV

300

0 0.5 1 1.5 2 2.5

VIC – Common-Mode Input Voltage – V

Figure 14

LOW-LEVEL OUTPUT VOLTAGE

FREE-AIR TEMPERATURE

900

VDD = 5 V VIC = 0.5 V

800

VID = –1 V IOL = 5 mA

700

600

500

400

300

VDD = 5 V IOL = 5 mA TA = 25°C

3 3.5 4

VOL – Low-Level Output Voltage – mV

80 65 50

–75 –50 –25 0 25 50 75 100 125

TA – Free-Air Temperature – ° C

Figure 15

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200

VOL – Low-Level Output Voltage – mV

100

0 –75 –50 –25 0 25 50 75 100 125

TA – Free-Air Temperature – ° C

Figure 16

TLV2332, TLV2332Y, TLV2334, TLV2334Y

LinCMOS LOW-VOLTAGE MEDIUM-POWER

TYPICAL CHARACTERISTICS

OPERATIONAL AMPLIFIERS

SLOS189 – FEBRUARY 1997

LOW-LEVEL OUTPUT VOLTAGE

DIFFERENTIAL INPUT VOLTAGE

800

700

600

500

400

300

200

VOL – Low-Level Output Voltage – mV

100

0–1–2–3–4–5

VID – Differential Input Voltage – V

Figure 17

LARGE-SIGNAL

DIFFERENTIAL VOLTAGE AMPLIFICATION

SUPPLY VOLTAGE

500

RL = 100 kΩ

450

VDD = 5 V VIC = |VID/2| IOL = 5 mA TA = 25°C

–6 –7 –8

LOW-LEVEL OUTPUT VOLTAGE

LOW-LEVEL OUTPUT CURRENT

VIC = 1 V

0.9

VID = –100 mV TA = 25°C

0.8

0.7

0.6

0.5

0.4

0.3

0.2

VOL – Low-Level Output Voltage – V

0.1 0

0123456

VDD = 3 V

IOL – Low-Level Output Current – mA

Figure 18

LARGE-SIGNAL

DIFFERENTIAL VOLTAGE AMPLIFICATION

FREE-AIR TEMPERATURE

500

RL = 100 kΩ

450

VDD = 5 V

400 350

300

250 200 150

Amplification – V/mV

– Large-Signal Differential Voltage

100

02468

TA = –40°C

TA = 25°C

TA = 85°C

VDD – Supply Voltage – V

Figure 19

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400 350

300

250 200 150

Amplification – V/mV

100

– Large-Signal Differential Voltage

–75 –50 –25 0 25 50 75 100 125

VDD = 5 V

VDD = 3 V

TA – Free-Air Temperature – ° C

Figure 20

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TYPICAL CHARACTERISTICS

LARGE-SIGNAL DIFFERENTIAL VOLTAGE

AMPLIFICATION AND PHASE SHIFT

FREQUENCY

VDD = 3 V RL = 100 kΩ CL = 20 pF TA = 25°C

–60°

–30°

0°

30°

60°

Phase Shift

– Large-Signal Differential Voltage Amplification

0.1

1 10 100 1 k 10 k 100 k

f – Frequency – Hz

Figure 21

LARGE-SIGNAL DIFFERENTIAL VOLTAGE

AMPLIFICATION AND PHASE SHIFT

FREQUENCY

VDD = 5 V RL = 100 kΩ CL = 20 pF TA = 25°C

1 M

–60°

–30°

0°

30°

60°

90°

120°

150°

180°

Phase Shift

– Large-Signal Differential Voltage Amplification

0.1

1 10 100 1 k 10 k 100 k 1 M

Phase Shift

f – Frequency – Hz

Figure 22

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90°

120°

150°

180°

Phase Shift

TLV2332, TLV2332Y, TLV2334, TLV2334Y

LinCMOS LOW-VOLTAGE MEDIUM-POWER

TYPICAL CHARACTERISTICS

OPERATIONAL AMPLIFIERS

SLOS189 – FEBRUARY 1997

SUPPLY CURRENT

SUPPLY VOLTAGE

450

VIC = 1 V VO = 1 V

400

No Load

350

300

250

200

150

IDD – Supply Current – uA

IAµ

100

02468

VDD – Supply Voltage – V

0.9 VIC = 1 V

= 1 V

I(PP)

AV = 1

0.8 RL = 100 kΩ

0.7

CL = 20 pF TA = 25°C

sµV/

TA = –40°C

TA = 25°C

Figure 23

SLEW RATE

SUPPLY VOLTAGE

TA = 85°C

SUPPLY CURRENT

FREE-AIR TEMPERATURE

400

VIC = 1 V VO = 1 V

350

No Load

300

250

= 3 V

200

150

IDD – Supply Current – uA

100

IAµ

TA – Free-Air Temperature – ° C

Figure 24

FREE-AIR TEMPERATURE

0.9

VIC = 1 V V

= 1 V

I(PP)

AV = 1

0.8 RL = 100 kΩ

0.7

CL = 20 pF

sµV/

VDD = 5 V

SLEW RATE

125

1007550250–25–50–75

0.6

0.5

SR – Slew Rate – V/us

0.4

0.3 02468

VDD – Supply Voltage – V

Figure 25

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0.6

0.5 VDD = 5 V

0.4

SR – Slew Rate – V/us

0.3

0.2

–75 –50 –25 0 25 50 75 100 125

VDD = 3 V

TA – Free-Air Temperature – ° C

Figure 26

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TYPICAL CHARACTERISTICS

MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE

FREQUENCY

– Maximum Peak-to-Peak Output Voltage – V

O(PP)

VDD = 5 V

VDD = 3 V

TA = 85°C

TA = 25°C

1 10 100 1000

f – Frequency – kHz

RL = 100 kΩ

TA = – 40°C

Figure 27

1000

900

1000

900

800

700

600

500

400

B1 – Unity-Gain Bandwidth – kHz

300

200

012345678

UNITY-GAIN BANDWIDTH

FREE-AIR TEMPERATURE

VI = 10 mV RL = 100 kΩ CL = 20 pF

UNITY-GAIN BANDWIDTH

SUPPLY VOLTAGE

VI = 10 mV RL = 100 kΩ CL = 20 pF TA = 25°C

VDD – Supply Voltage – V

Figure 28

800

700

600

500

400

B1 – Unity-Gain Bandwidth – kHz

300

200

–75 –50 –25 0 25 50 75 100 125

TA – Free-Air Temperature – ° C

VDD = 5 V

VDD = 3 V

Figure 29

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PHASE MARGIN

SUPPLY VOLTAGE

50°

48° 46° 44° 42° 40° 38°

xm – Phase Margin

36°

34° 32° 30°

0123456

VDD – Supply Voltage – V

Figure 30

= 10 mV

RL = 100 kΩ CL = 20 pF TA = 25°C

PHASE MARGIN

FREE-AIR TEMPERATURE

45°

43°

39°

xm – Phase Margin

37°

35°

– 75 – 25 0 50 100 125–50 25 75

VDD = 3 V

TA – Free-Air Temperature – ° C

Figure 31

VI = 10 mV RL = 100 kΩ CL = 20 pF

VDD = 5 V

PHASE MARGIN

LOAD CAPACITANCE

44°

42°

40°

VDD = 5 V

38°

36°

34°

xm – Phase Margin

32°

30°

28°

VDD = 3 V

0204060

CL – Load Capacitance – pF

Figure 32

VI = 10 mV RL = 100 KΩ TA = 25°C

80 100

EQUIVALENT INPUT NOISE VOLTAGE

300

250

nV/

200

150

100

Vn – Equivalent Input Noise Voltage – nVxHz

110

VDD = 3 V

Figure 33

FREQUENCY

RS = 20 Ω TA = 25°C

VDD = 5 V

1000100

f – Frequency – Hz

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PARAMETER MEASUREMENT INFORMATION

single-supply versus split-supply test circuits

Because the TL V233x is optimized for single-supply operation, circuit configurations used for the various tests often present some inconvenience since the input signal, in many cases, must be offset from ground. This inconvenience can be avoided by testing the device with split supplies and the output load tied to the negative rail. A comparison of single-supply versus split-supply test circuits is shown below. The use of either circuit gives the same result.

1/2 V

– +

(a) SINGLE SUPPLY (b) SPLIT SUPPLY

– +

DD+

DD–

Figure 34. Unity-Gain Amplifier

2 kΩ

20 Ω

– +

DD+

DD–

20 Ω

2 kΩ

– +

20 Ω

1/2 V

(a) SINGLE SUPPLY (b) SPLIT SUPPLY

Figure 35. Noise-Test Circuit

10 kΩ

100 Ω

(a) SINGLE SUPPLY (b) SPLIT SUPPLY

– +

100 Ω

10 kΩ

DD+

– +

DD–

Figure 36. Gain-of-100 Inverting Amplifier

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PARAMETER MEASUREMENT INFORMATION

input bias current

Because of the high input impedance of the TL V233x operational amplifier , attempts to measure the input bias current can result in erroneous readings. The bias current at normal ambient temperature is typically less than 1 pA, a value that is easily exceeded by leakages on the test socket. Two suggestions are offered to avoid erroneous measurements:

• Isolate the device from other potential leakage sources. Use a grounded shield around and between the

device inputs (see Figure 37). Leakages that would otherwise flow to the inputs are shunted away.

• Compensate for the leakage of the test socket by actually performing an input bias current test (using a

picoammeter) with no device in the test socket. The actual input bias current can then be calculated by subtracting the open-socket leakage readings from the readings obtained with a device in the test socket.

Many automatic testers as well as some bench-top operational amplifier testers use the servo-loop technique with a resistor in series with the device input to measure the input bias current (the voltage drop across the series resistor is measured and the bias current is calculated). This method requires that a device be inserted into a test socket to obtain a correct reading; therefore, an open-socket reading is not feasible using this method.

V = V

Figure 37. Isolation Metal Around Device Inputs (P package)

low-level output voltage

To obtain low-level supply-voltage operation, some compromise is necessary in the input stage. This compromise results in the device low-level output voltage being dependent on both the common-mode input voltage level as well as the differential input voltage level. When attempting to correlate low-level output readings with those quoted in the electrical specifications, these two conditions should be observed. If conditions other than these are to be used, please refer to the Typical Characteristics section of this data sheet.

input offset voltage temperature coefficient

Erroneous readings often result from attempts to measure temperature coefficient of input offset voltage. This parameter is actually a calculation using input offset voltage measurements obtained at two different temperatures. When one (or both) of the temperatures is below freezing, moisture can collect on both the device and the test socket. This moisture results in leakage and contact resistance which can cause erroneous input offset voltage readings. The isolation techniques previously mentioned have no effect on the leakage since the moisture also covers the isolation metal itself, thereby rendering it useless. These measurements should be performed at temperatures above freezing to minimize error.

full-power response

Full-power response, the frequency above which the operational amplifier slew rate limits the output voltage swing, is often specified two ways: full-linear response and full-peak response. The full-linear response is

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PARAMETER MEASUREMENT INFORMATION

generally measured by monitoring the distortion level of the output while increasing the frequency of a sinusoidal input signal until the maximum frequency is found above which the output contains significant distortion. The full-peak response is defined as the maximum output frequency , without regard to distortion, above which full peak-to-peak output swing cannot be maintained.

Because there is no industry-wide accepted value for significant distortion, the full-peak response is specified in this data sheet and is measured using the circuit of Figure 34. The initial setup involves the use of a sinusoidal input to determine the maximum peak-to-peak output of the device (the amplitude of the sinusoidal wave is increased until clipping occurs). The sinusoidal wave is then replaced with a square wave of the same amplitude. The frequency is then increased until the maximum peak-to-peak output can no longer be maintained (Figure 38). A square wave is used to allow a more accurate determination of the point at which the maximum peak-to-peak output is reached.

(b) BOM > f > 100 Hz(a) f = 100 Hz

(d) f > B

Figure 38. Full-Power-Response Output Signal

test time

Inadequate test time is a frequent problem, especially when testing CMOS devices in a high-volume, short-test-time environment. Internal capacitances are inherently higher in CMOS than in bipolar and BiFET devices and require longer test times than their bipolar and BiFET counterparts. The problem becomes more pronounced with reduced supply levels and lower temperatures.

APPLICATION INFORMATION

single-supply operation

While the TLV233x performs well using dualpower supplies (also called balanced or split supplies), the design is optimized for singlesupply operation. This includes an input commonmode voltage range that encompasses ground as well as an output voltage range that pulls down to ground. The supply voltage range extends down to 2 V, thus allowing operation with supply levels commonly available for TTL and HCMOS.

Many single-supply applications require that a voltage be applied to one input to establish a reference level that is above ground. This virtual ground can be generated using two large resistors, but a preferred technique is to use a virtual-ground generator such as the TLE2426 (see Figure 39).

TLE2426

Figure 39. Inverting Amplifier With Voltage

– +

Reference

+ ǒ

VDD–V

R2 R1

)

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APPLICATION INFORMATION

single-supply operation (continued)

The TLE2426 supplies an accurate voltage equal to VDD/2, while consuming very little power and is suitable for supply voltages of greater than 4 V . The TL V233x works well in conjunction with digital logic; however , when powering both linear devices and digital logic from the same power supply, the following precautions are recommended:

• Power the linear devices from separate bypassed supply lines (see Figure 40); otherwise, the linear

device supply rails can fluctuate due to voltage drops caused by high switching currents in the digital logic.

• Use proper bypass techniques to reduce the probability of noise-induced errors. Single capacitive

decoupling is often adequate; however, RC decoupling may be necessary in high-frequency applications.

– +

Logic Logic Logic

(a) COMMON-SUPPLY RAILS

Logic Logic Logic

(b) SEPARATE-BYPASSED SUPPLY RAILS (preferred)

Power Supply

Figure 40. Common Versus Separate Supply Rails

input characteristics

The TL V233x is specified with a minimum and a maximum input voltage that, if exceeded at either input, could cause the device to malfunction. Exceeding this specified range is a common problem, especially in single-supply operation. The lower the range limit includes the negative rail, while the upper range limit is specified at V

The use of the polysilicon-gate process and the careful input circuit design gives the TL V233x very good input offset voltage drift characteristics relative to conventional metal-gate processes. Offset voltage drift in CMOS devices is highly influenced by threshold voltage shifts caused by polarization of the phosphorus dopant implanted in the oxide. Placing the phosphorus dopant in a conductor (such as a polysilicon gate) alleviates the polarization problem, thus reducing threshold voltage shifts by more than an order of magnitude. The offset voltage drift with time has been calculated to be typically 0.1 µV/month, including the first month of operation.

– 1 V at TA = 25°C and at VDD – 1.2 V at all other temperatures.

Because of the extremely high input impedance and resulting low bias-current requirements, the TLV233x is well suited for low-level signal processing; however, leakage currents on printed-circuit boards and sockets can easily exceed bias-current requirements and cause a degradation in device performance.

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APPLICATION INFORMATION

input characteristics (continued)

It is good practice to include guard rings around inputs (similar to those of Figure 37 in the Parameter Measurement Information section). These guards should be driven from a low-impedance source at the same voltage level as the common-mode input (see Figure 41).

The inputs of any unused amplifiers should be tied to ground to avoid possible oscillation.

–

(a) NONINVERTING AMPLIFIER (b) INVERTING AMPLIFIER (c) UNITY-GAIN AMPLIFIER

– +

Figure 41. Guard-Ring Schemes

noise performance

The noise specifications in operational amplifiers circuits are greatly dependent on the current in the first-stage differential amplifier . The low input bias-current requirements of the TLV233x results in a very low noise current, which is insignificant in most applications. This feature makes the device especially favorable over bipolar devices when using values of circuit impedance greater than 50 kΩ, since bipolar devices exhibit greater noise currents.

feedback

Operational amplifiers circuits nearly always employ feedback, and since feedback is the first prerequisite for oscillation, caution is appropriate. Most oscillation problems result from driving capacitive loads and ignoring stray input capacitance. A small-value capacitor connected in parallel with the feedback resistor is an effective remedy (see Figure 42). The value of this capacitor is optimized empirically.

– +

electrostatic-discharge protection

Figure 42. Compensation for Input Capacitance

The TLV233x incorporates an internal electrostatic-discharge (ESD)-protection circuit that prevents functional failures at voltages up to 2000 V as tested under MIL-PRF-38535. Method 3015.2. Care should be exercised, however, when handling these devices as exposure to ESD may result in the degradation of the device parametric performance. The protection circuit also causes the input bias currents to be temperature dependent and have the characteristics of a reverse-biased diode.

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APPLICATION INFORMATION

latch-up

Because CMOS devices are susceptible to latch-up due to their inherent parasitic thyristors, the TL V233x inputs and outputs are designed to withstand –100-mA surge currents without sustaining latch-up; however, techniques should be used to reduce the chance of latch-up whenever possible. Internal-protection diodes should not by design be forward biased. Applied input and output voltage should not exceed the supply voltage by more than 300 mV. Care should be exercised when using capacitive coupling on pulse generators. Supply transients should be shunted by the use of decoupling capacitors (0.1 µF typical) located across the supply rails as close to the device as possible.

The current path established if latch-up occurs is usually between the positive supply rail and ground and can be triggered by surges on the supply lines and/or voltages on either the output or inputs that exceed the supply voltage. Once latch-up occurs, the current flow is limited only by the impedance of the power supply and the forward resistance of the parasitic thyristor and usually results in the destruction of the device. The chance of latch-up occurring increases with increasing temperature and supply voltages.

output characteristics

2.5 V

– +

RP+

IP = Pullup Current Required by the Operational Amplifier (typically 500 µA)

–2.5 V

VDD*

IF)

The output stage of the TLV233x is designed to sink and source relatively high amounts of current (see Typical Characteristics). If the output is subjected to a short-circuit condition, this highcurrent capability can cause device damage under certain conditions. Output current capability increases with supply voltage.

Although the TLV233x possesses excellent high-level output voltage and current capability, methods are available for boosting this capability if needed. The simplest method involves the use of a pullup resistor (R

) connected from the output

to the positive supply rail (see Figure 43). There are two disadvantages to the use of this circuit. First, the NMOS pulldown transistor N4 (see equivalent schematic) must sink a comparatively large amount of current. In this circuit, N4 behaves like a linear resistor with an on resistance between approximately 60 Ω and 180 Ω, depending on how hard the operational amplifier input is driven. With very low values of R

, a voltage offset from

0 V at the output occurs. Secondly , pullup resistor R

acts as a drain load to N4 and the gain of the

operational amplifier is reduced at output voltage levels where N5 is not supplying the output current.

–

Figure 43. Resistive Pullup to Increase V

TA = 25°C f = 1 kHz V

= 1 V

I(PP)

Figure 44. Test Circuit for Output Characteristics

IL)

All operating characteristics of the TLV233x are measured using a 20-pF load. The device drives higher capacitive loads; however, as output load capacitance increases, the resulting response pole occurs at lower frequencies thereby causing ringing, peaking, or even oscillation (see Figure 44 and Figure 45). In many cases, adding some compensation in the form of a series resistor in the feedback loop alleviates the problem.

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APPLICATION INFORMATION

output characteristics (continued)

(a) CL = 20 pF, RL = NO LOAD (b) CL = 170 pF, RL = NO LOAD (c) CL = 190 pF, RL = NO LOAD

Figure 45. Effect of Capacitive Loads

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MECHANICAL INFORMATION

D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PIN SHOWN

0.069 (1,75) MAX

0.050 (1,27)

0.020 (0,51)

0.014 (0,35)

0.010 (0,25)

0.004 (0,10)

0.010 (0,25)

0.157 (4,00)

0.150 (3,81)

0.244 (6,20)

0.228 (5,80)

Seating Plane

0.004 (0,10)

PINS **

DIM

A MAX

A MIN

0.008 (0,20) NOM

Gage Plane

0°–8°

0.197

(5,00)

0.189

(4,80)

0.344

(8,75)

0.337

(8,55)

0.044 (1,12)

0.016 (0,40)

4040047/B 03/95

0.394

(10,00)

0.386

(9,80)

0.010 (0,25)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). D. Four center pins are connected to die mount pad.

E. Falls within JEDEC MS-012

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV2332, TLV2332Y, TLV2334, TLV2334Y LinCMOS LOW-VOLTAGE MEDIUM-POWER OPERATIONAL AMPLIFIERS

SLOS189 – FEBRUARY 1997

MECHANICAL INFORMATION

N (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE

16 PIN SHOWN

0.035 (0,89) MAX

PINS **

DIM

0.260 (6,60)

0.240 (6,10)

0.070 (1,78) MAX

0.020 (0,51) MIN

0.200 (5,08) MAX

A MAX

A MIN

Seating Plane

0.775

(19,69)

0.745

(18,92)

0.775

(19,69)

0.745

(18,92)

0.920

(23.37)

0.850

(21.59)

0.975

(24,77)

0.940

(23,88)

0.310 (7,87)

0.290 (7,37)

0.100 (2,54)

0.021 (0,53)

0.015 (0,38)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001 (20 pin package is shorter then MS-001.)

0.010 (0,25)

0.125 (3,18) MIN

0°–15°

0.010 (0,25) NOM

14/18 PIN ONL Y

4040049/C 08/95

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV2332, TLV2332Y, TLV2334, TLV2334Y

LinCMOS LOW-VOLTAGE MEDIUM-POWER

OPERATIONAL AMPLIFIERS

SLOS189 – FEBRUARY 1997

MECHANICAL INFORMATION

P (R-PDIP-T8) PLASTIC DUAL-IN-LINE PACKAGE

0.400 (10,60)

0.355 (9,02)

0.260 (6,60)

0.240 (6,10)

0.070 (1,78) MAX

0.020 (0,51) MIN

0.200 (5,08) MAX

0.125 (3,18) MIN

0.100 (2,54)

0.021 (0,53)

0.015 (0,38)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001

0.010 (0,25)

0.310 (7,87)

0.290 (7,37)

Seating Plane

0°–15°

0.010 (0,25) NOM

4040082/B 03/95

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV2332, TLV2332Y, TLV2334, TLV2334Y LinCMOS LOW-VOLTAGE MEDIUM-POWER OPERATIONAL AMPLIFIERS

SLOS189 – FEBRUARY 1997

MECHANICAL INFORMATION

PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PIN SHOWN

0,65

1,20 MAX

0,10 MIN

0,32 0,19

6,70

4,50 4,30

6,10

0,13

Seating Plane

0,10

0,15 NOM

Gage Plane

0,25

0°–8°

0,75 0,50

PINS **

DIM

A MAX

A MIN

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

3,10

2,90

5,10

4,90

5,10

6,60

6,404,90

7,90

7,70

9,80

9,60

4040064/D 10/95

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.

CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

TEXAS INSTRUMENTS TLV2332, TLV2332Y, TLV2334, TLV2334Y Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual