Texas Instruments TLV1543MJ, TLV1543MJB, TLV1543MFKB, TLV1543IDBR, TLV1543IDBLE Datasheet

TLV1543C, TLV1543M

3.3-V 10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS072C – DECEMBER 1992 – REVISED MARCH 1995

D

3.3-V Supply Operation

D

10-Bit-Resolution A/D Converter

D

11 Analog Input Channels

D

Three Built-In Self-Test Modes

D

Inherent Sample and Hold

D

Total Unadjusted Error...±1 LSB Max

D

On-Chip System Clock

D

End-of-Conversion (EOC) Output

D

Pin Compatible With TLC1543

D

CMOS Technology

DB, DW, FK, J, OR N PACKAGE

(TOP VIEW)

A0
A1
A2
A3
A4
A5
A6
A7
A8

GND

1
2
3
4
5
6
7
8
9
10

V

20

EOC

19

I/O CLOCK

18

ADDRESS

17

DATA OUT

16

CS

15
14

REF+

13

REF–

12

A10

11

A9

CC

description

FN PACKAGE

The TL V1543C and TL V1543M are CMOS 10-bit,
switched-capacitor, successive-approximation,
analog-to-digital converters. These devices have
three inputs and a 3-state output [chip select (CS
input-output clock (I/O CLOCK), address input
(ADDRESS), and data output (DATA OUT)] that
provide a direct 4-wire interface to the serial port
of a host processor. The devices allow high-speed
data transfers from the host.

),

A3
A4
A5
A6
A7

In addition to a high-speed A/D converter and
versatile control capability , these devices have an
on-chip 14-channel multiplexer that can select
any one of 11 analog inputs or any one of three
internal self-test voltages. The sample-and-hold
function is automatic. At the end of A/D conversion, the end-of-conversion (EOC) output goes high to indicate
that conversion is complete. The converter incorporated in the devices features differential high-impedance
reference inputs that facilitate ratiometric conversion, scaling, and isolation of analog circuitry from logic and
supply noise. A switched-capacitor design allows low-error conversion over the full operating free-air
temperature range.

(TOP VIEW)

A2A1A0

3212019

4
5
6
7
8

910111213

A8

GND

A9

V

A10

CC

EOC

18
17
16
15
14

REF –

I/O CLOCK
ADDRESS
DATA OUT
CS
REF+

The TL V1543C is characterized for operation from 0°C to 70°C. The TLV1543M is characterized for operation
over the full military temperature range of –55°C to 125°C.

AVAILABLE OPTIONS

PACKAGE

T

A

0°C to 70°C TLV1543CDB TLV1543CDW — — TLV1543CN TLV1543CFN

–55°C to 125°C — — TLV1543MFK TLV1543MJ — —

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

SMALL

OUTLINE

(DB)

SMALL

OUTLINE

(DW)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CHIP CARRIER

(FK)

CERAMIC DIP

(J)

PLASTIC DIP

(N)

Copyright  1995, Texas Instruments Incorporated

PLASTIC CHIP

CARRIER

(FN)

1

TLV1543C, TLV1543M

3.3-V 10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS072C – DECEMBER 1992 – REVISED MARCH 1995

functional block diagram

1

A10

ADDRESS

A0
A1
A2
A3
A4

A5
A6
A7
A8

A9

3

17

2
3

4
5
6
7
8

9
11
12

14-Channel

Analog

Multiplexer

Self-Test

Reference

Sample and

4

Input Address

Register

Hold

REF+ REF–

14 13

10-Bit

Analog-to-Digital

Converter

(switched capacitors)

10

Output

Data

Register

System Clock,
Control Logic,

and I/O

Counters

10

10-to-1 Data

Selector and

Driver

4

19

16

DATA
OUT

EOC

CS

18
15

I/O CLOCK

typical equivalent inputs

INPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE INPUT CIRCUIT IMPEDANCE DURING HOLD MODE

1 kΩ TYP

A0–A10

Ci = 60 pF TYP
(equivalent input
capacitance)

A0–A10

5 MΩ TYP

2

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I/O

DESCRIPTION

TLV1543C, TLV1543M

3.3-V 10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS072C – DECEMBER 1992 – REVISED MARCH 1995

Terminal Functions

TERMINAL

NAME NO.

ADDRESS 17 I Serial address. A 4-bit serial address selects the desired analog input or test voltage that is to be converted

A0–A10 1–9, 11,

CS 15 I Chip select. A high-to-low transition on CS resets the internal counters and controls and enables DAT A OUT ,

DATA OUT 16 O The 3-state serial output for the A/D conversion result. DAT A OUT is in the high-impedance state when CS

EOC 19 O End of conversion. EOC goes from a high- to a low- logic level on the trailing edge of the tenth I/O CLOCK

GND 10 I The ground return terminal for the internal circuitry . Unless otherwise noted, all voltage measurements are

I/O CLOCK 18 I Input/output clock. I/O CLOCK receives the serial I/O CLOCK input and performs the following four functions:

REF+ 14 I The upper reference voltage value (nominally VCC) is applied to REF+. The maximum input voltage range

REF– 13 I The lower reference voltage value (nominally ground) is applied to REF–.
V

CC

12

20 I Positive supply voltage

next. The address data is presented with the MSB first and is shifted in on the first four rising edges of I/O
CLOCK. After the four address bits have been read into the address register, ADDRESS is ignored for the
remainder of the current conversion period.

I Analog signal. The 11 analog inputs are applied to A0–A10 and are internally multiplexed. The driving source

impedance should be less than or equal to 1 kΩ .

ADDRESS, and I/O CLOCK within a maximum of a setup time plus two falling edges of the internal system
clock. A low-to-high transition disables ADDRESS and I/O CLOCK within a setup time plus two falling edges
of the internal system clock.

is high and active when CS is low. With a valid chip select, DA T A OUT is removed from the high-impedance
state and is driven to the logic level corresponding to the MSB value of the previous conversion result. The
next falling edge of I/O CLOCK drives DAT A OUT to the logic level corresponding to the next most significant
bit, and the remaining bits are shifted out in order with the LSB appearing on the ninth falling edge of I/O
CLOCK. On the tenth falling edge of I/O CLOCK, DATA OUT is driven to a low logic level so that serial
interface data transfers of more than ten clocks produce zeroes as the unused LSBs.

and remains low until the conversion is complete and data are ready for transfer.

with respect to GND.

1) It clocks the four input address bits into the address register on the first four rising edges of I/O
CLOCK with the multiplex address available after the fourth rising edge.

2) On the fourth falling edge of I/O CLOCK, the analog input voltage on the selected multiplex input begins
charging the capacitor array and continues to do so until the tenth falling edge of I/O CLOCK.

3) It shifts the nine remaining bits of the previous conversion data out on DATA OUT.

4) It transfers control of the conversion to the internal state controller on the falling edge of the tenth clock.

is determined by the difference between the voltage applied to REF+ and the voltage applied to the REF–
terminal.

detailed description

With chip select (CS) inactive (high), the ADDRESS and I/O CLOCK inputs are initially disabled and DA TA OUT
is in the high-impedance state. When the serial interface takes CS
with the enabling of I/O CLOCK and ADDRESS and the removal of DA T A OUT from the high-impedance state.
The host then provides the 4-bit channel address to ADDRESS and the I/O CLOCK sequence to I/O CLOCK.
During this transfer, the host serial interface also receives the previous conversion result from DATA OUT. I/O
CLOCK receives an input sequence that is between 10 and 16 clocks long from the host. The first four I/O clocks
load the address register with the 4-bit address on ADDRESS selecting the desired analog channel and the next
six clocks providing the control timing for sampling the analog input.

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active (low), the conversion sequence begins

3

TLV1543C, TLV1543M

Fast Modes

Slow Modes

3.3-V 10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS072C – DECEMBER 1992 – REVISED MARCH 1995

detailed description (continued)

There are six basic serial interface timing modes that can be used with the device. These modes are determined
by the speed of I/O CLOCK and the operation of CS
a 10-clock transfer and CS
and CS

active (low) continuously , (3) a fast mode with an 11- to 16-clock transfer and CS inactive (high) between

inactive (high) between conversion cycles, (2) a fast mode with a 10-clock transfer

conversion cycles, (4) a fast mode with a 16-bit transfer and CS
an 11- to 16-clock transfer and CS
16-clock transfer and CS

active (low) continuously.

inactive (high) between conversion cycles, and (6) a slow mode with a

as shown in T able 1. These modes are (1) a fast mode with

active (low) continuously , (5) a slow mode with

The MSB of the previous conversion appears on DA T A OUT on the falling edge of CS

in mode 1, mode 3, and
mode 5, on the rising edge of EOC in mode 2 and mode 4, and following the 16th clock falling edge in mode 6.
The remaining nine bits are shifted out on the next nine falling edges of I/O CLOCK. Ten bits of data are
transmitted to the host through DA T A OUT. The number of serial clock pulses used also depends on the mode
of operation, but a minimum of ten clock pulses is required for conversion to begin. On the 10th clock falling
edge, the EOC output goes low and returns to the high logic level when conversion is complete and the result
can be read by the host. On the 10th clock falling edge, the internal logic takes DA TA OUT low to ensure that
the remaining bit values are zero if the I/O CLOCK transfer is more than ten clocks long.

T able 1 lists the operational modes with respect to the state of CS

, the number of I/O serial transfer clocks that

can be used, and the timing edge on which the MSB of the previous conversion appears at the output.

Table 1. Mode Operation

MODES

Mode 1 High between conversion cycles 10 CS falling edge Figure 9
Mode 2 Low continuously 10 EOC rising edge Figure 10
Mode 3 High between conversion cycles 11 to 16
Mode 4 Low continuously 16
Mode 5 High between conversion cycles 11 to 16
Mode 6 Low continuously 16

†

These edges also initiate serial-interface communication.

‡

No more than 16 clocks should be used.

CS

NO. OF

I/O CLOCKS

‡

‡

‡

‡

MSB AT DATA OUT

CS falling edge Figure 11
EOC rising edge Figure 12
CS falling edge Figure 13
16th clock falling edge Figure 14

†

TIMING

DIAGRAM

fast modes

The device is in a fast mode when the serial I/O CLOCK data transfer is completed before the conversion is
completed. With a 10-clock serial transfer, the device can only run in a fast mode since a conversion does not
begin until the falling edge of the 10th I/O CLOCK.

mode 1: fast mode, CS inactive (high) between conversion cycles, 10-clock transfer

In this mode, CS is inactive (high) between serial I/O CLOCK transfers and each transfer is ten clocks long. The
falling edge of CS

ends the sequence by returning DA T A OUT to the high-impedance state within the specified delay time.

of CS
Also, the rising edge of CS

begins the sequence by removing DA TA OUT from the high-impedance state. The rising edge

disables the I/O CLOCK and ADDRESS terminals within a setup time plus two falling

edges of the internal system clock.

mode 2: fast mode, CS active (low) continuously, 10-clock transfer

In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer is ten clocks long. After
the initial conversion cycle, CS

is held active (low) for subsequent conversions; the rising edge of EOC then
begins each sequence by removing DATA OUT from the low logic level, allowing the MSB of the previous
conversion to appear immediately on this output.

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV1543C, TLV1543M

3.3-V 10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS072C – DECEMBER 1992 – REVISED MARCH 1995

mode 3: fast mode, CS inactive (high) between conversion cycles, 11- to 16-clock transfer

In this mode, CS is inactive (high) between serial I/O CLOCK transfers and each transfer can be 1 1 to 16 clocks
long. The falling edge of CS
rising edge of CS
delay time. Also, the rising edge of CS
plus two falling edges of the internal system clock.

ends the sequence by returning DA T A OUT to the high-impedance state within the specified

mode 4: fast mode, CS active (low) continuously, 16-clock transfer

In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer must be exactly 16 clocks
long. After the initial conversion cycle, CS
EOC then begins each sequence by removing DATA OUT from the low logic level, allowing the MSB of the
previous conversion to appear immediately on this output.

slow modes

In a slow mode, the conversion is completed before the serial I/O CLOCK data transfer is completed. A slow
mode requires a minimum 11-clock transfer into I/O CLOCK, and the rising edge of the eleventh clock must
occur before the conversion period is complete; otherwise, the device loses synchronization with the host serial
interface, and CS
occur within 9.5 µs after the tenth I/O clock falling edge.

has to be toggled to initialize the system. The eleventh rising edge of the I/O CLOCK must

mode 5: slow mode, CS inactive (high) between conversion cycles, 11- to 16-clock transfer

In this mode, CS is inactive (high) between serial I/O CLOCK transfers and each transfer can be 1 1 to 16 clocks
long. The falling edge of CS
rising edge of CS
delay time. Also, the rising edge of CS
plus two falling edges of the internal system clock.

ends the sequence by returning DA T A OUT to the high-impedance state within the specified

begins the sequence by removing DA T A OUT from the high-impedance state. The

disables the I/O CLOCK and ADDRESS terminals within a setup time

is held active (low) for subsequent conversions; the rising edge of

begins the sequence by removing DA T A OUT from the high-impedance state. The

disables the I/O CLOCK and ADDRESS terminals within a setup time

mode 6: slow mode, CS active (low) continuously, 16-clock transfer

In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer must be exactly 16 clocks
long. After the initial conversion cycle, CS
the sixteenth I/O CLOCK then begins each sequence by removing DA TA OUT from the low state, allowing the
MSB of the previous conversion to appear immediately at DATA OUT. The device is then ready for the next
16-clock transfer initiated by the serial interface.

address bits

The 4-bit analog channel-select address for the next conversion cycle is presented to the ADDRESS terminal
(MSB first) and is clocked into the address register on the first four leading edges of I/O CLOCK. This address
selects one of 14 inputs (11 analog inputs or 3 internal test inputs).

analog inputs and test modes

The 1 1 analog inputs and the 3 internal test inputs are selected by the 14-channel multiplexer according to the
input address as shown in Tables 2 and 3. The input multiplexer is a break-before-make type to reduce
input-to-input noise injection resulting from channel switching.

Sampling of the analog input starts on the falling edge of the fourth I/O CLOCK, and sampling continues for six
I/O CLOCK periods. The sample is held on the falling edge of the tenth I/O CLOCK. The three test inputs are
applied to the multiplexer, sampled, and converted in the same manner as the external analog inputs.

is held active (low) for subsequent conversions. The falling edge of

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

TLV1543C, TLV1543M

SELECTED

)

‡

VOLTAGE SELECTED

†

()

ref

)

ref

1011B200

3.3-V 10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS072C – DECEMBER 1992 – REVISED MARCH 1995

Table 2. Analog-Channel-Select Address

ANALOG INPUT

A0 0000 0
A1 0001 1
A2 0010 2
A3 0011 3
A4 0100 4
A5 0101 5
A6 0110 6
A7 0111 7
A8 1000 8
A9 1001 9

A10 1010 A

VALUE SHIFTED INTO

ADDRESS INPUT

BINARY HEX

Table 3. Test-Mode-Select Address

INTERNAL SELF-TEST

V

–V

–

2

V

ref–

V

†

V

ref+

input.

‡

The output results shown are the ideal values and vary with the reference stability and with
internal offsets.

ref+

is the voltage applied to the REF+ input, and V

VALUE SHIFTED INTO

ADDRESS INPUT

BINARY HEX

1100 C 000
1101 D 3FF

ref–

OUTPUT RESULT (HEX

is the voltage applied to the REF–

converter and analog input

The CMOS threshold detector in the successive-approximation conversion system determines each bit by
examining the charge on a series of binary-weighted capacitors (see Figure 1). In the first phase of the
conversion process, the analog input is sampled by closing the S

switch and all ST switches simultaneously .

C

This action charges all the capacitors to the input voltage.
In the next phase of the conversion process, all S

and SC switches are opened and the threshold detector

T

begins identifying bits by identifying the charge (voltage) on each capacitor relative to the reference (REF–)
voltage. In the switching sequence, ten capacitors are examined separately until all ten bits are identified and
the charge-convert sequence is repeated. In the first step of the conversion phase, the threshold detector looks
at the first capacitor (weight = 512). Node 512 of this capacitor is switched to the REF+ voltage, and the
equivalent nodes of all the other capacitors on the ladder are switched to REF–. If the voltage at the summing
node is greater than the trip point of the threshold detector (approximately one-half the V

voltage), a bit 0 is

CC

placed in the output register and the 512-weight capacitor is switched to REF–. If the voltage at the summing
node is less than the trip point of the threshold detector, a bit 1 is placed in the register and the 512-weight
capacitor remains connected to REF+ through the remainder of the successive-approximation process. The
process is repeated for the 256-weight capacitor, the 128-weight capacitor, and so forth down the line until all
bits are counted.

With each step of the successive-approximation process, the initial charge is redistributed among the
capacitors. The conversion process relies on charge redistribution to count and weigh the bits from MSB to LSB.

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV1543C, TLV1543M

3.3-V 10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS072C – DECEMBER 1992 – REVISED MARCH 1995

converter and analog input (continued)

S

C

Threshold

Detector

Node 512

REF–

V

I

512

REF–

S

T

REF+

REF–

S

T

REF+

REF–

S

T

REF+

REF–

S

T

REF+

REF–

S

T

REF+

REF–

S

T

REF+

REF–

S

T

REF+

REF–

S

T

1124816128256

S

T

Figure 1. Simplified Model of the Successive-Approximation System

chip-select operation

The trailing edge of CS
A high-to-low transition on CS

starts all modes of operation, and CS can abort a conversion sequence in any mode.

within the specified time during an ongoing cycle aborts the cycle, and the device
returns to the initial state (the contents of the output data register remain at the previous conversion result).
Exercise care to prevent CS

from being taken low close to completion of conversion because the output data

can be corrupted.

To Output
Latches

reference voltage inputs

There are two reference inputs used with these devices: REF+ and REF–. These voltage values establish the
upper and lower limits of the analog input to produce a full-scale and zero-scale reading respectively . The values
of REF+, REF–, and the analog input should not exceed the positive supply or be lower than GND consistent
with the specified absolute maximum ratings. The digital output is at full scale when the input signal is equal
to or higher than REF+ and at zero when the input signal is equal to or lower than REF–.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V
Input voltage range, V

Output voltage range, V
Positive reference voltage, V
Negative reference voltage, V

Peak input current (any input) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Peak total input current (all inputs) ±30 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T
Storage temperature range, T

Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to digital ground with REF– and GND wired together (unless otherwise noted).

(see Note 1): TLV1543C –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

TLV1543M –0.5 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(any input) –0.3 V to VCC + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

–0.3 V to VCC + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

V

ref+

–0.1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ref–

: TLV1543C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A

TLV1543M –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

CC

+ 0.1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7

TLV1543C, TLV1543M

Suppl

oltage, V

High-level control input voltage, V

Low-level control input voltage, V

Clock frequency at I/O CLOCK (see Note 4)

MH

Operating free-air temperature, T

°C

3.3-V 10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS072C – DECEMBER 1992 – REVISED MARCH 1995

recommended operating conditions

MIN NOM MAX UNIT

pp

y v

Positive reference voltage, V
Negative reference voltage, V
Differential reference voltage, V
Analog input voltage (see Note 2) 0 V

Setup time, address bits at data input before I/O CLOCK↑, t
Hold time, address bits after I/O CLOCK↑, t
Hold time, CS low after last I/O CLOCK↓, t
Setup time, CS low before clocking in first address bit, t

Pulse duration, I/O CLOCK high, t
Pulse duration, I/O CLOCK low, t
Transition time, I/O CLOCK, t
Transition time, ADDRESS and CS, t

p

NOTES: 2. Analog input voltages greater than that applied to REF+ convert as all ones (1 111111111), while input voltages less than that applied

CC

(see Note 2) V

ref+

(see Note 2) 0 V

ref–

– V

ref+

p

p

p

to REF– convert as all zeros (0000000000). The device is functional with reference voltages down to 1 V (V
the electrical specifications are no longer applicable.

3. To minimize errors caused by noise at CS
clock after CS
setup time has elapsed.

4. For 1 1- to 16-bit transfers, after the tenth I/O CLOCK falling edge (≤ 2 V), at least one I/O clock rising edge (≥ 2 V) must occur within

9.5 µs.

5. This is the time required for the clock input signal to fall from VIHmin to VILmax or to rise from VILmax to VIHmin. In the vicinity of
normal room temperature, the devices function with input clock transition time as slow as 1 µs for remote data-acquisition
applications where the sensor and the A/D converter are placed several feet away from the controlling microprocessor.

IH

IL

wH(I/O)

wL(I/O)

(see Note 5) 1 µs

t(I/O)

A

↓ before responding to control input signals. No attempt should be made to clock in an address until the minimum CS

(see Note 2) 2.5 V

ref–

h(A)

h(CS)

t(CS)

TLV1543C 3 3.3 5.5 V
TLV1543M 3 3.3 3.6 V

CC

ref+

+0.2 V

CC

10 µs

– V

ref–

°

); however,

CCVCC

TLV1543C VCC = 3 V to 5.5 V 2 V
TLV1543M VCC = 3 V to 3.6 V 2 V
TLV1543C VCC = 3 V to 5.5 V 0.6 V
TLV1543M VCC = 3 V to 3.6 V 0.8 V

(see Figure 4) 100 ns

su(A)

(see Figure 4) 0 ns

0 ns

(see Note 3) 1.425 µs

su(CS)

TLC1543C 0 1.1
TLC1543M 0 2.1

190 ns
190 ns

TLV1543C 0 70
TLV1543M –55 125

, the internal circuitry waits for a setup time plus two falling edges of the internal system

V

V

z

8

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TLV1543C

VOHHigh-level output voltage

TLV1543M

TLV1543C

VOLLow-level output voltage

TLV1543M

IOZOff-state (high-impedance-state) output current

A

Selected channel leakage current

A

Input capacitance, Analog inputs

pF

C

Input capacitance, Control inputs

pF

TLV1543C, TLV1543M

3.3-V 10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS072C – DECEMBER 1992 – REVISED MARCH 1995

electrical characteristics over recommended operating free-air temperature range,
V

= V

CC

V

= V

CC

noted)

I

High-level input current VI = V

IH

I

Low-level input current VI = 0 –0.005 –2.5 µA

IL

I

Operating supply current CS at 0 V 0.8 2.5 mA

CC

Maximum static analog reference current into REF+ V

i

†

All typical values are at VCC = 5 V, TA = 25°C.

= 3 V to 5.5 V, I/O CLOCK frequency = 1.1 MHz for the TLV1543C,

ref+

= 3 V to 3.6 V, I/O CLOCK frequency = 2.1 MHz for the TLV1543M (unless otherwise

ref+

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

VCC = 3 V, IOH = –1.6 mA 2.4 V

p

p

p

p

p

p

p

p

TLV1543C 7 55

p

TLV1543M 7
TLV1543C 5 15

p

TLV1543M 5

VCC = 3 V to 5.5 V, IOH = 20 µA VCC–0.1 V
VCC = 3 V, IOH = –1.6 mA 2.4 V
VCC = 3 V to 3.6 V, IOH = 20 µA VCC–0.1 V
VCC = 3 V, IOL = 1.6 mA 0.4 V
VCC = 3 V to 5.5 V, IOL = 20 µA 0.1 V
VCC = 3 V, IOL = 1.6 mA 0.4 V
VCC = 3 V to 3.6 V, IOL = 20 µA 0.1 V
VO = VCC, CS at V
VO = 0, CS at V

CC

Selected channel at VCC,
Unselected channel at 0 V

Selected channel at 0 V ,
Unselected channel at V

= VCC, V

ref+

CC
CC

0.005 2.5 µA

CC

= GND 10 µA

ref–

10

–10

–1

µ

1

µ

p

p

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9

TLV1543C, TLV1543M

3.3-V 10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS072C – DECEMBER 1992 – REVISED MARCH 1995

operating characteristics over recommended operating free-air temperature range,
V

= V

CC

V

= V

CC

t

conv

t

c

t

acq

t

v

t

d(I/O-DATA)

t

d(I/O-EOC)

t

d(EOC-DATA)

t

, t

PZH

PZL

t

, t

PHZ

PLZ

t

r(EOC)

t

f(EOC)

t

r(bus)

t

f(bus)

t

d(I/O-CS)

†

All typical values are at TA = 25°C.

NOTES: 2. Analog input voltages greater than that applied to REF+ convert as all ones (1111111111), while input voltages less than that applied

= 3 V to 5.5 V, I/O CLOCK frequency = 1.1 MHz for the TLV1543C,

ref+

= 3 V to 3.6 V, I/O CLOCK frequency = 2.1 MHz for the TLV1543M

ref+

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

Linearity error (see Note 6) ±1 LSB
Zero error (see Note 7) See Note 2 ±1 LSB
Full-scale error (see Note 7) See Note 2 ±1 LSB
Total unadjusted error (see Note 8) ±1 LSB

ADDRESS = 1011 512

Self-test output code (see Table 3 and Note 9)

Conversion time See Figures 9–14 21 µs

Total cycle time (access, sample, and conversion)

Channel acquisition time (sample)

Valid time, DATA OUT remains valid after I/O CLOCK↓ See Figure 6 10 ns
Delay time, I/O CLOCK↓ to DATA OUT valid See Figure 6 240 ns
Delay time, tenth I/O CLOCK↓ to EOC↓ See Figure 7 70 240 ns
Delay time, EOC↑ to DATA OUT (MSB) See Figure 8 100 ns
Enable time, CS↓ to DATA OUT (MSB driven) See Figure 3 1.3 µs
Disable time, CS↑ to DATA OUT (high impedance) See Figure 3 150 ns
Rise time, EOC See Figure 8 300 ns
Fall time, EOC See Figure 7 300 ns
Rise time, data bus See Figure 6 300 ns
Fall time, data bus See Figure 6 300 ns
Delay time, tenth I/O CLOCK↓ to CS↓ to abort conversion

(see Note 11)

to REF– convert as all zeros (0000000000). The device is functional with reference voltages down to 1 V (V
the electrical specifications are no longer applicable.

6. Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics.

7. Zero-scale error is the difference between 0000000000 and the converted output for zero input voltage; full-scale error is the
difference between 1 111111111 and the converted output for full-scale input voltage.

8. Total unadjusted error comprises linearity, zero-scale, and full-scale errors.

9. Both the input address and the output codes are expressed in positive logic.

10. I/O CLOCK period = 1/(I/O CLOCK frequency) (see Figure 6).

11. Any transitions of CS
(1.425 µs) after the transition.

are recognized as valid only if the level is maintained for a setup time plus two falling edges of the internal clock

ADDRESS = 1100
ADDRESS = 1101 1023

See Figures 9–14
and Note 10

See Figures 9–14
and Note 10

0

ref+

21

+10 I/O

CLOCK

periods

6

9 µs

– V

ref–

µs

I/O

CLOCK

periods

); however,

10

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TLV1543C, TLV1543M

3.3-V 10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS072C – DECEMBER 1992 – REVISED MARCH 1995

PARAMETER MEASUREMENT INFORMATION

EOC

CL = 50 pF

Test Point V

12 kΩ

CC

RL = 2.18 kΩ

Figure 2. Load Circuits

CS

DATA

OUT

t

PZH

V

IL

, t

PZL

2.4 V

0.4 V

2 V

t
90%
10%

PHZ

, t

PLZ

Figure 3. DATA OUT to Hi-Z Voltage Waveforms

DATA OUT

CL = 100 pF

ADDRESS

I/O CLOCK

Test Point V

12 kΩ

2 V
V

IL

t

su(A)

Address

Valid

V

IL

CC

RL = 2.18 kΩ

t

h(A)

Figure 4. ADDRESS Setup V oltage Waveforms

CS

I/O CLOCK

V

IL

t

su(CS)

V

First

IL

Clock

Last

Clock

Figure 5. CS and I/O CLOCK Voltage Waveforms

2 V

t

h(CS)

V

IL

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11

TLV1543C, TLV1543M

3.3-V 10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS072C – DECEMBER 1992 – REVISED MARCH 1995

PARAMETER MEASUREMENT INFORMATION

t

t(I/O)

t

t(I/O)

I/O CLOCK

t

d(I/O-DATA)

DATA OUT

2 V

t

V

IL

I/O CLOCK Period

v

2.4 V

0.4 V

2.4 V

0.4 V

V

IL

t

r(bus)

2 V

, t

f(bus)

V

IL

Figure 6. DATA OUT and I/O CLOCK Voltage Waveforms

I/O CLOCK

EOC

10th

Clock

t

d(I/O-EOC)

V

t

f(EOC)

IL

2.4 V

0.4 V

Figure 7. I/O CLOCK and EOC Voltage Waveforms

t

r(EOC)

EOC

0.4 V

DATA OUT

2.4 V

t

d(EOC-DATA)

2.4 V

0.4 V

Valid MSB

Figure 8. EOC and DATA OUT Voltage Waveforms

12

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CS

(see Note A)

TLV1543C, TLV1543M

3.3-V 10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS072C – DECEMBER 1992 – REVISED MARCH 1995

I/O

CLOCK

DATA

OUT

ADDRESS

EOC

NOTE A: To minimize errors caused by noise at CS

after CS
time has elapsed.

123456 78910 1

Access Cycle B

MSB LSB

B3 B2 B1 B0 C3

MSB LSB

↓ before responding to control input signals. No attempt should be made to clock in an address until the minimum CS setup

Previous Conversion Data

Shift in New Multiplexer Address,

Simultaneously Shift Out Previous

Figure 9. Timing for 10-Clock Transfer Using CS

CS

(see Note A)

Must be High on Power Up

Sample Cycle B

Hi-Z State

Conversion Value

, the internal circuitry waits for a setup time plus two falling edges of the internal system clock

A/D Conversion

Interval

B9A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

InitializeInitialize

I/O

CLOCK

DATA

OUT

ADDRESS

EOC

Initialize

NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system clock

after CS
time has elapsed.

123456 78910 1

Access Cycle B

MSB LSB

B3 B2 B1 B0 C3

MSB LSB

↓ before responding to control input signals. No attempt should be made to clock in an address until the minimum CS setup

Previous Conversion Data

Shift in New Multiplexer Address,

Simultaneously Shift Out Previous

Conversion Value

Sample Cycle B

Low Level

A/D Conversion

Interval

B9A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Initialize

Figure 10. Timing for 10-Clock Transfer Not Using CS

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13

TLV1543C, TLV1543M

3.3-V 10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS072C – DECEMBER 1992 – REVISED MARCH 1995

CS

(see Note A)(see Note A)

See Note B

I/O

CLOCK

DATA

OUT

ADDRESS

EOC

Initialize

NOTES: A. To minimize errors caused by noise at CS, the internal circuitry waits for a set up time plus two falling edges of the internal system

clock after CS
setup time has elapsed.

B. A low-to-high transition of CS disables ADDRESS and the I/O CLOCK within a maximum of a setup time plus two falling edges of

the internal system clock.

123456 78910 1

Access Cycle B

MSB LSB

B3 B2 B1 B0 C3

MSB LSB

↓ before responding to control input signals. No attempt should be made to clock in an address until the minimum CS

Previous Conversion Data

Shift in New Multiplexer Address,

Simultaneously Shift Out Previous

Conversion Value

Sample Cycle B

11 16

Low

Level

A/D Conversion

Interval

Hi-Z

B9A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Initialize

Figure 11. Timing for 11- to 16-Clock Transfer Using CS (Serial Transfer Interval Shorter Than Conversion)

CS

(see Note A)

I/O

CLOCK

DATA

OUT

ADDRESS

EOC

Initialize

NOTES: A. The first I/O CLOCK must occur after the rising edge of EOC.

B. A low-to-high transition of CS

Must be High on Power Up

123456 78910 1

Access Cycle B

MSB LSB

B3 B2 B1 B0 C3

MSB LSB

the internal system clock.

Previous Conversion Data

Shift in New Multiplexer Address,

Simultaneously Shift Out Previous

Conversion Value

disables ADDRESS and the I/O CLOCK within a maximum of a setup time plus two falling edges of

Sample Cycle B

14 15 16

Low Level

A/D Conversion

Interval

Initialize

See Note B

Figure 12. Timing for 16-Clock Transfer Not Using CS (Serial Transfer Interval Shorter Than Conversion)

B9A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

14

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ÎÎ

TLV1543C, TLV1543M

3.3-V 10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS072C – DECEMBER 1992 – REVISED MARCH 1995

(see Note A)

CS

I/O

CLOCK

DATA

OUT

ADDRESS

EOC

Initialize

NOTES: A. To minimize errors caused by noise at CS, the internal circuitry waits for a set up time plus two falling edges of the internal system

B. The eleventh rising edge of the I/O CLOCK sequence must occur before the conversion is complete to prevent losing serial

12345678910 1

Access Cycle B

MSB LSB

B3 B2 B1 B0 C3

MSB LSB

clock after CS
chip CS

interface synchronization.

↓ before responding to control input signals. No attempt should be made to clock in an address until the minimum

setup time has elapsed.

Previous Conversion Data

Shift in New Multiplexer Address,

Simultaneously Shift Out Previous

Conversion Value

Sample Cycle B

11

16

See Note B

Low

Level

A/D Conversion

Interval

Hi-Z State

B9A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Initialize

Figure 13. Timing for 11- to 16-Clock Transfer Using CS (Serial Transfer Interval Longer Than Conversion)

(see Note A)

CS

I/O

CLOCK

DATA

OUT

ADDRESS

EOC

Initialize

NOTES: A. The eleventh rising edge of the I/O CLOCK sequence must occur before the conversion is complete to prevent losing serial

interface synchronization.

B. The I/O CLOCK sequence is exactly 16 clock pulses long.

Must be High on Power Up

123456 78910 1

Access Cycle B

MSB LSB

B3 B2 B1 B0 C3

MSB LSB

Previous Conversion Data

Shift in New Multiplexer Address,

Simultaneously Shift Out Previous

Conversion Value

Sample Cycle B

A/D Conversion

14 15 16

See Note A

Low Level

Interval

See Note B

B9A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Figure 14. Timing for 16-Clock Transfer Not Using CS (Serial Transfer Interval Longer Than Conversion)

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15

TLV1543C, TLV1543M

3.3-V 10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS072C – DECEMBER 1992 – REVISED MARCH 1995

APPLICATION INFORMATION

1111111111

See Notes A and B

1111111110

1111111101

1000000001

1000000000

0111111111

Digital Output Code

V

0000000010

0000000001

0000000000

0 0.0096 2.4528 2.4576 2.4624

NOTES: A. This curve is based on the assumption that V

0 to 1 (VZT) is 0.0024 V and the transition to full scale (VFT) is 4.908 V. 1 LSB = 4.8 mV.

B. The full-scale value (VFS) is the step whose nominal midstep value has the highest absolute value. The zero-scale value (VZS)

is the step whose nominal midstep value equals zero.

VZT = VZS + 1/2 LSB

ZS

0.0048

0.0024
VI – Analog Input Voltage – V

ref+

and V

V

FS

VFT = VFS – 1/2 LSB

4.9056 4.9104 4.9152

4.9080

have been adjusted so that the voltage at the transition from digital

ref–

1023

1022

1021

513

512

511

2

1

0

Step

Analog

Inputs

To Source

Ground

Figure 15. Ideal Conversion Characteristics

1
2
3
4
5
6
7
8
9
11
12

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10

TLV1543

I/O CLOCK

ADDRESS

DATA OUT

GND

10

CS

EOC

REF+

REF–

15
18
17

16
19

14
13

3-V DC Regulated

Figure 16. Serial Interface

Processor

Control

Circuit

16

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simplified analog input analysis

TLV1543C, TLV1543M

3.3-V 10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS072C – DECEMBER 1992 – REVISED MARCH 1995

APPLICATION INFORMATION

Using the equivalent circuit in Figure 17, the time required to charge the analog input capacitance from 0 to V
within 1/2 LSB can be derived as follows:

The capacitance charging voltage is given by

–t

= VS 1–e

V

C

( )

c/RtCi

where

= Rs + r

R

t

i

The final voltage to 1/2 LSB is given by

(1/2 LSB) = VS – (VS/2048)

C

Equating equation 1 to equation 2 and solving for time t

–t

–(VS/2048) = VS 1–e

V

S

( )

c/RtCi

gives

c

and

t

(1/2 LSB) = Rt × Ci × ln(2048) (4)

c

Therefore, with the values given the time for the analog input signal to settle is

(1/2 LSB) = (Rs + 1 kΩ) × 60 pF × ln(2048)

t

c

This time must be less than the converter sample time shown in the timing diagrams.

Driving Source

†

TLV1543

S

(1)

(2)V

(3)

(5)

R

s

V

S

VI= Input Voltage at A0–A10
VS= External Driving Source Voltage
Rs= Source Resistance
ri= Input Resistance
Ci= Input Capacitance

†

Driving source requirements:

• Noise and distortion for the source must be equivalent to the
resolution of the converter.

• Rs must be real at the input frequency.

V

I

1 kΩ MAX

r

i

V

C

C

i

50 pF MAX

Figure 17. Equivalent Input Circuit Including the Driving Source

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17

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