Texas Instruments TLFD500PN Datasheet

TLFD500PN

3.3 V INTEGRATED G.LITE ANALOG FRONT END

SLAS207A – JUNE 1999 – REVISED NOVEMBER 1999

D

Complies With ITU G.992.2 Standard

D

14-Bit Integrated A/D and D/A Converters

D

1.104 Msps Update Rate for the RX Channel

D

276 ksps Update Rate for the TX Channel

D

Minimum 50 dB Missing Tone Rejection for
DMT Signals

D

Integrated TX/RX Filters

D

Integrated Digital Phase Lock Loop (DPLL)
and VCXO DAC

D

Integrated Equalizer for Receive Channel

D

Integrated PGA in Receive, and PAA in
Transmit Channels

description

The TLFD500PN is a high-speed analog front end for a remote terminal-side ADSL G.Lite modem. The device
is designed to perform transmit encoding (D/A conversion), receive decoding (A/D conversion), transmit and
receive filtering functions, and receive equalizer functions for a frequency division multiplex (FDM) G.Lite
application. The receive channel has an update rate of 1.104 Msps, while the transmit channel has an update
rate of 276 ksps. Both channels use 2s complement data format.

D

Direct Single Serial Interface to TI’s C54x or
C6x DSP (Data and Control)

D

Eight General-Purpose I/O Pins

D

Software and Hardware Power-Down
Modes

D

Industrial Temperature Range
(–40°C to 85°C)

D

Integrated Auxiliary Amplifiers for System
Flexibility

D

Single 3.3 V Supply

D

80-Pin LQFP (PN) Package

D

2s Complement Data Format

When used in a G.Lite system, the TLFD500PN requires a minimum number of external components. The
device incorporates integrated filtering, DPLL, VCXO DAC (uses 2s complement data format), and 8
general-purpose I/O ports. The general-purpose I/O ports provide a means of reading or writing status bits in
the system. Four auxiliary amplifiers on the chip can be configured (external components may be required) to
provide additional onboard filtering and amplification.

A simple serial interface for data transfer on the digital side reduces system component count. The interface
can be connected directly to the TI C6x and C54x families of DSPs.

The TLFD500PN device is available in an 80-pin PN LQFP package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1999, Texas Instruments Incorporated

1

TLFD500PN

3.3 V INTEGRATED G.LITE ANALOG FRONT END

SLAS207A – JUNE 1999 – REVISED NOVEMBER 1999

PN PACKAGE

(TOP VIEW)

AMP4OUTP

AMP4OUTM

NC

AMP3OUTP

AMP3INM

AMP3INP

AMP3OUTM

AVDD_RX

AVSS_RX

RXINP

RXINM

HPF2OUTP

HPF2INM

HPF2INP

HPF2OUTM

HPF1OUTP

HPF1INM

HPF1INP

HPF1OUTM

VSS

AMP4INM

AMP4INP

59 58 57 56 5560 54

61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80

23

1

NC

DVSS_RX

5678

4

DVSS_RX

DVSS_RX

DVSS_RXNCDVSS_RX

TLFD500PN

DVDD_RX

52 51 5053

9

10 11 12 13

VMID_RX

AVSS_RX

AVDD_RX

47 46 45 44

49 48

14 15 16 17

AVDD_REF

REFP

REFM

RXBANDGAP

PLLSEL

AVSS_REF

43 42 41

18 19 20

DVSS

DVSS

40

DVDD

39

RESET

38

MCLKIN/PLLCLKIN

37

NC

36

DGPO

35

DVSS

34

DVSS_IO

33

DVDD_IO

32

DVDD

31

GPIO7

30

GPIO6

29

GPIO5

27

GPIO4

27

GPIO3

26

GPIO2

25

GPIO1

24

GPIO0

23

FSX

22

FSR

21

NC – No connection

AMP2INP

AMP2INM

AMP2OUTM

AMP2OUTP

TXOUTP

TXOUTM

A VDD_TX

A VSS_TX

AMP1INM

AMP1OUTP

AMP1INP

VCXOCNTL

AMP1OUTM

PWRDN

COMPDAC2

COMPDAC1

TXBANDGAP

SDX

SDR

SCLK

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functional block diagram

TLFD500PN

3.3 V INTEGRATED G.LITE ANALOG FRONT END

SLAS207A – JUNE 1999 – REVISED NOVEMBER 1999

FSR

FSX

SDR

SDX

SCLK

Serial

Interface

and

Control

VCXO

DAC

276

KSPS

Digital Loop-back

552 kHz

RX

1104

KSPS

INTERNAL CLOCK

Generator

LPF

Clock

30 kHz to 138 kHz

30 kHz 138 kHz
Digital

HPF

DPLL

Digital

LPF

4.416 MSPS

4.416 MSPS

14 Bit

ADC

0 to 18 dB

(6 dB/step)

RX PGA2

INTERNAL

REFERENCE

14 Bit

138 kHz

TX

DAC

0 to 9 dB

(0.25 dB/Step)

RX PGA3

PGA

PGA PGA

Purpose I/O

TX

LPF

180 kHz

HPF2

General

0 to –24 dB

(–1 dB/step)

TX PAA

PAA

Analog

Loop-back

552 kHz

Equalizer+

RX LPF

0 to 12 dB

(3 dB/Step)

RX PGA1

180 kHz

HPF1

AUX Amps(4)

TXOUTP/
TXOUTM

RXINP/
RXINM

See Note

HPF2OUTP/
HPF2OUTM

HPF2INP/
HPF2INM

See Note

HPF1OUTP/
HPF1OUTM

HPF1INP/
HPF1INM

AMPOUTP/
AMPOUTM

AMPINP/
AMPINM

VCXOCNTL

35.328 MHz

NOTE: Refer to Figure 17 for application details.

External

VCXO

MCLKIN

External

Oscillator

35.328 MHz

MCLKIN

VMID_RX

REFP

REFM

TXBANDGAP/

RXBANDGAP

GPI00–GPI07

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TLFD500PN

I/O

DESCRIPTION

3.3 V INTEGRATED G.LITE ANALOG FRONT END

SLAS207A – JUNE 1999 – REVISED NOVEMBER 1999

Terminal Functions

TERMINAL

NAME NO.

AMP1INP– AMP4INP 11,2,66,59 I Auxiliary amplifier 1–4 positive input
AMP1INM– AMP4INM 10,3,65,60 I Auxiliary amplifier 1–4 negative input
AMP1OUTP– AMP2OUTP 9,4 O Auxiliary amplifier 1–2 positive output. Outputs are self-biased to AVDD_TX/2.
AMP3OUTP– AMP4OUTP 64, 61 O Auxiliary amplifier 3–4 positive output. Outputs are self-biased to AVDD_RX/2.
AMP1OUTM– AMP2OUTM 12,1 O Auxiliary amplifier 1–2 negative output. Outputs are self-biased to AVDD_TX/2.
AMP3OUTM– AMP4OUTM 67,62 O Auxiliary amplifier 3–4 negative output. Outputs are self-biased to AVDD_RX/2.
AVDD_REF 47 I Analog supply for reference circuit
AVDD_RX 48,68 I RX channel analog supply
AVDD_TX 7 I TX channel analog supply
AVSS_REF 44 I Analog supply return for reference(analog ground)
AVSS_RX 49,69 I RX channel analog supply return (analog ground)
AVSS_TX 8 I TX channel analog supply return (analog ground)
COMPDAC1 16 I TX channel decoupling cap input A. Add 1 µF capacitor to AVDD_TX
COMPDAC2 15 I TX channel decoupling cap input B. Add 1 µF capacitor to AVDD_TX
DGPO 35 O Direct general-purpose output. This pin reflects the last value written to the DGPO bit

DVDD 31,39 I Digital power supply
DVDD_IO 32 I Digital I/O buffer supply
DVDD_RX 51 I RX channel digital supply
DVSS 34,40,41 I Digital ground
DVSS_IO 33 I Digital I/O buffer supply return (digital ground)
DVSS_RX 52,54,55,

56,57
FSX 22 O Serial port frame sync transmit signal
FSR 21 O Serial port frame sync receive signal
GPIO0–GPIO7 23–30 I/O General-purpose I/O
HPF1INP 78 I RX channel stage 1 amplifier positive input. Input signal needs to have AVDD_RX/2

HPF1INM 77 I RX channel stage 1 amplifier negative input. Input signal needs to have AVDD_RX/2

HPF2INP 74 I RX channel stage 2 positive input. Input signal need to have AVDD_RX/2 common mode

HPF2INM 73 I RX channel stage 2 negative input. Input signal need to have AVDD_RX/2 common mode

HPF1OUTP 76 O RX channel stage 1 amplifier positive output. Used to connect external components to obtain

HPF1OUTM 79 O RX channel stage 1 amplifier negative output. Used to connect external components to

HPF2OUTP 72 O RX channel stage 2 positive output. Output signal has AVDD_RX/2 common mode voltage.
HPF2OUTM 75 O RX channel stage 2 negative output. Output signal has AVDD_RX/2 common mode voltage.
MCLKIN/PLLCLKIN 37 I Multiplexed pin based on value of PLLSEL. Selects master clock input, or clock input for PLL

location in the SDR data stream. It is a general-purpose output that does not require a
secondary transfer to control.

I RX channel digital supply return (digital ground)

common mode voltage.

common mode voltage.

voltage.

voltage.

stage 1 HPF.

obtain stage 1 HPF.

mode.

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I/O

DESCRIPTION

TLFD500PN

3.3 V INTEGRATED G.LITE ANALOG FRONT END

SLAS207A – JUNE 1999 – REVISED NOVEMBER 1999

Terminal Functions (Continued)

TERMINAL

NAME NO.

NC 36,53, 58,

63

PLLSEL 42 I Selects between VCXO mode and DPLL mode. If the pin is tied high PLL mode is selected.

PWRDN 17 I Power-down pin. When PWRDN is pulled low the device goes into power-down mode. The

REFM 45 O Negative reference filter node. This terminal is provided for low-pass filtering of the internal

REFP 46 O Positive reference filter node. This terminal is provided for low-pass filtering of the internal

RESET 38 I Device reset input pin. Initializes all the device’s internal registers to their default values.

RXBANDGAP 43 O RX channel band-gap filter node. This terminal is provided for decoupling of the 1.5-V

RXINP 70 I RX channel stage 3 positive input. The input is self-biased at AVDD_RX/2.
RXINM 71 I RX channel stage 3 negative input. The input is self-biased at AVDD_RX/2.
SCLK 19 O Serial port shift clock (transmit and receive)
SDR 20 I Serial data receive from DSP
SDX 18 O Serial data transmit to DSP
TXBANDGAP 14 O TX channel band-gap filter node. This terminal is provided for decoupling of the 1.5-V

TXOUTP 5 O TX channel positive output
TXOUTM 6 O TX channel negative output
VCXOCNTL 13 O DAC output to control onboard VCXO
VMID_RX 50 I/O Decoupling Vmid for ADC. Add 10 µF (tantalum) and 0.1 µF (ceramic) capacitors to analog

VSS 80 I Substrate. Connect to analog ground.

No connection. Keep floating.

Pin should be tied low for VCXO mode. Cannot be left floating.

default state of this pin is low.

band-gap reference. The optimal ceramic capacitor value is 10 µF (tantalum) and 0.1 µF
(ceramic), connected to analog ground. The nominal dc voltage at this terminal is 0.5 V.

band-gap reference. The optimal ceramic capacitor value is 10 µF (tantalum) 0.1 µF
(ceramic), connected to analog ground. The nominal dc voltage at this terminal is 2.5 V.

The default state of this pin is low.

band-gap reference. The optimal capacitor value is 10 µF (tantalum) and 0.1 µF (ceramic).
This node should not be used as a voltage source.

band-gap reference. The optimal capacitor value is 10 µF (tantalum) and 0.1 µF (ceramic).
This node should not be used as a voltage source.

ground.

detailed description

transmit

The transmit channel is powered by a high performance DAC. The transmit channel update rate is 276 kHz.
The DAC is a 14-bit DAC at 4.416-MHz. This provides 16X oversampling. A band-pass filter limits the output
of the transmitter to a frequency range of 30 kHz to 138 kHz. A differential amplifier drives the output into the
external line driver. The dif ferential amplifier has programmable attenuation for added flexibility. The transmitter
high-pass filter can be bypassed by writing the appropriate bit to the filter bypass control register (BCR).

The output spectrum of the DAC complies with the nonoverlapped power spectrum density (PSD) mask
specified in the ITU draft recommendation G.992.2 for G.Lite.

The TXP AA is a programmable-attenuation amplifier. It provides 0 dB to 24 dB of attenuation in1-dB steps. The
TXP AA is controlled via the P AA control register (PCR). For details about register programming see the register
programming section.

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5

TLFD500PN

3.3 V INTEGRATED G.LITE ANALOG FRONT END

SLAS207A – JUNE 1999 – REVISED NOVEMBER 1999

detailed description (continued)

receive

The receive channel consists of a high-pass filter, a programmable gain amplifier, an ADC, and filters. In
addition, it has an equalizer to attain maximum system performance. The input of the receiver is fully differential.

The ADC in the receive channel is a 14-bit converter which samples at 4.416 Msps for 4X oversampling. An
on-chip decimator reduces the sampling frequency to 1.104 MHz. The low pass filtering of the receive channel
limits the converted data to frequencies below 552 kHz.

The high-pass analog filter is used to reject the near-end echo to maximize the dynamic range of the ADC. The
high-pass filter consists of two stages: (1) a second order high-pass filter (HPF1) and, (2) a third order elliptic
high-pass filter (HPF2). Both stages have a cutoff at 180 kHz. The filter is divided into two stages to minimize
the noise from a single stage being amplified throughout. T ogether , the two high-pass filters typically attenuate
the echo power by 30 dB. There is a programmable gain amplifier (PGA) between the two filters for coarse gain
adjustments of 0-dB –12-dB in 3-dB steps. After the high-pass filter stage, the receiver channel has a
0-dB –18-dB PGA that can be adjusted in 6-dB steps. HPF2 and PGAs are integrated in one block. Figure 1(a),
1(b), and 1(c) show the frequency response of HPF1 and HPF2 (with PGAs).

The PGA is followed by a 552-kHz low-pass filter with a programmable 25-dB/MHz slope (5-dB/MHz step)
equalizer incorporated. After the equalizer, there is a fine-gain adjustment PGA of 0-dB to 9-dB in 0.25-dB steps.

All the RX PGAs are controlled via the PGA control registers (PCR–RX1 and PCR–RX2). See the register
programming section for details about register programming.

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detailed description (continued)

TLFD500PN

3.3 V INTEGRATED G.LITE ANALOG FRONT END

SLAS207A – JUNE 1999 – REVISED NOVEMBER 1999

50

0

–50

–100

Gain – dB

–150

–200

–250

0 0.5 1

f – Frequency – Hz

(a) RX-Stage HPF1 Frequency Response (0 to 200 kHz)

0

–
3

–
6

–
9

–12

dB

–15
–18
–21
–24
–27

1.5 2

× 10

2

0

–2

–4

Gain – dB

–6

–8

–10

5

1 1.2 1.4

f – Frequency – Hz

(b) RX-Stage HPF1 Frequency Response (100 kHz to 200 kHz)

1.6 1.8 2
5

× 10

38.6 90.6 142.
6

(c) RX-Stage HPF2 Frequency Response (PGA1 = PGA2 = 0 dB)

kHz

194.
6

246.
6

298.
6

Figure 1. RX Stage HPF1 and HPF2 Frequency Response

clock control – VCXO mode

The VCXODAC uses a 12-bit, 2s complement number to control a 0-V to 3-V analog output. The two 8-bit
registers, VCR-M and VCR-L, are used to generate the 12-bit control code (2s complement). This implies the
use of 16 bits to obtain a 12-bit number.

VCR-M register occupy the most significant 8 bits in the 12-bit number and the lower 4 bits of the VCR-L register
(VCR-L[3:0] ) are used for the low 4 bits of the 12-bit number. The 12-bit code is updated every time either
register is updated. VCR-L[7:4] must always be zero.

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7

TLFD500PN

3.3 V INTEGRATED G.LITE ANALOG FRONT END

SLAS207A – JUNE 1999 – REVISED NOVEMBER 1999

clock control – DPLL mode

As an alternative to the VCXODAC and VCXO, an off-chip crystal oscillator (XO) followed by an on-chip digital
PLL are also implemented. Refer to Figure 7 for an internal function block diagram. The input clock (35.328
MHz) goes to a programmable frequency divider to generate sampling clock for the ADC and DAC converters.
By changing the divide ratio, the phase of the sampling clock can be adjusted. Setting PLLSEL (pin 42) high
will enable the DPLL mode. Refer to DPLL section for detail.

clock generation

The clock generation block creates the necessary internal and external clocks needed by the device. All the
clocks generated are produced from the CLKIN signal.

The following are recommended operational parameters for the external VCXO:

3.3-V supply, 35.328 MHz ±50 PPM center frequency , and input control voltage range of 0 V–3 V.
The recommended duty cycle is 50/50.

clock generation – SCLK

SCLK is an output and is used for serial data transfer. It runs at 35.328 MHz. Although SCLK and MCLK run
at the same speed, there is no fixed phase relationship between them.

serial interface

The serial interface on the TLFD500PN connects directly to TI’s C54x or C6x families of DSPs. The interface
operates at 35.328 MHz. The serial port consists of five signals: SCLK, FSX, FSR, SDX, and SDR. A typical
connection diagram is shown in Figure 2.

DSP

CLKR
CLKX

FSX
FSR

DX
DR

TLFD500PN

SCLK
FSR
FSX
SDR
SDX

Figure 2. Typical Serial Port Connection

The serial port utilizes a primary/secondary scheme to transfer conversion data and control register data. A
primary transfer scheme, used to transfer conversion data, occurs every conversion period. A secondary
transfer scheme, used to transfer control data, happens only when requested by the host processor. The host
processor requests a secondary transfer by using the LSB of the SDR data of the primary scheme. A value of
1 indicates a secondary transfer request. Once the secondary request is made and the primary transfer has
been completed, secondary frame sync pulse (FSX/FSR) are transmitted to the host processor to indicate the
beginning of the secondary transfer. The secondary FSX signal arrives 16 SCLKs after the primary FSX, and
thus 48 SCLKs after the host processor request. This is because the span between FSX pulses for primary
transfers is always 32 SCLKs. Each bit is read/written at the rising edge of the SCLK clock. Data bit mappings
and example data transfers are shown in Table 1.

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TLFD500PN

3.3 V INTEGRATED G.LITE ANALOG FRONT END

SLAS207A – JUNE 1999 – REVISED NOVEMBER 1999

detailed description (continued)

Table 1. SDR LSB Control Function

CONTROL BIT D0 CONTROL BIT FUNCTION

0 No secondary transfer requested
1 Secondary transfer requested

primary transfer data mapping

The data bit mapping of a primary transfer is shown in Figure 3. Bits D2–D15 of the SDR data stream are DAC
data. D1 is the control bit for the DGPO pin. The value written to this bit is reflected on the DGPO pin. See the
timing diagram in Figures 5 and 6 for detailed timing information. D0 is the secondary transfer request bit. When
a 1 is written to this bit, the host is requesting a secondary data transfer.

In the SDX data stream, D2–D15 contain the ADC conversion data. D0 and D1 can be set to reflect the values
of GPIO1 and GPIO2. To set D0 and D1 to reflect the GPIO values, the proper bit in the MCR register needs
to be set.

Secondary

Transfer

Data to CODEC

DGPO Bit

Request

SDR

SDX

GPIOx Status if Configured as

Input. Zero if GPIOx Configured

Data from CODEC

D15 – D2

D1 D0D15 – D2

as output or if Masked Off

GPIO1 GPIO0

Figure 3. Primary Transfer Data Bit Mapping

secondary transfer data mapping

Secondary serial communication is used to configure the device. The data bit mapping for a secondary transfer
is shown in Figure 4. Bits D10–D14 of the SDR data from the host contain the address of the control register
involved in the transfer. D15 is a R/W bit. To read out the control register by the host processor, bit R/W must
be set to 1. T o write to the control register by the host processor, bit R/W must be set to 0. During a read operation,
bits D0–D7 are don’t care. For a write operation, bits D0–D7 contain the data for the register addressed by
D10–D14. The eight bits of SDX always reflect the status of GPI00–7.

If the secondary transfer is a read operation, the contents of the control register addressed by D10–D14 of the
SDR data are reflected in bits D0–D7 of the SDX data stream. If the secondary transfer is a write operation, bits
D0–D7 on SDX will be all zeroes.

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TLFD500PN

3.3 V INTEGRATED G.LITE ANALOG FRONT END

SLAS207A – JUNE 1999 – REVISED NOVEMBER 1999

secondary transfer data mapping (continued)

D9 D0

A0

SDR (Read)

SDX (Read)

D15

A4 A3 A2 A1

1

Register Address Don’t Care

D15 D0D8 D7

GPIO0 – 7 Status

Read Cycle (Codec Register Data Read by DSP)

D8 D7

Don’t Care

Register Data

SDR (Write)

SDX (Write)

D9 D8 D7

0

A4 A3 A2

Register Address

D15 D0D8 D7

GPIO0 – 7 Status

A1 A0

Don’t Care

Write Cycle (DSP Data Write to Codec Register)

Data to the Register

All 0

D0

Figure 4. Secondary Transfer Data Bit Mapping

example data transfers

Figures 5(a) and 5(b) show the timing relationship for SCLK, FSX, SDX, FSR, and SDR in a primary
communication. The timing sequence for this operation is as follows:

1. FS is set high and remains high during one SCLK period, then returns to low.

2. A 16-bit word is transmitted from the ADC (SDX), and a 16-bit word is received for DAC conversion (SDR).
Figure 6(a) and 6(b) shows the timing relationship with secondary request.

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detailed description (continued)

SCLK

(Output)

FSX

(output)

TLFD500PN

3.3 V INTEGRATED G.LITE ANALOG FRONT END

SLAS207A – JUNE 1999 – REVISED NOVEMBER 1999

SDX

(Output)

SCLK

(Output)

FSR

(output)

SDR

(Input)

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

t1 t2 t3

t1 t2 t3

t1: DSP detects FSX
t2: TLFD500PN sends data
t3: DSP latches data

D15

D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

t1: DSP detects FSR
t2: DSP sends data
t3: TLFD500PN latches data

(a) TLFD500PN to DSP

(b) DSP to TLFD500PN

NOTE: TI DSP requires 10 ns after the positive edge of the SCLK to give the SDR data. This plus the board delay, output buffer (for SCLK) and

input buffer delay (for SDR) to around 17 ns. As a consequence the SDR data can not be latched at the negative edge of SCLK.

Figure 5. Data Transfers

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11

TLFD500PN

3.3 V INTEGRATED G.LITE ANALOG FRONT END

SLAS207A – JUNE 1999 – REVISED NOVEMBER 1999

detailed description (continued)

128 SCLKs

FSR

FSX

16 SCLKs

SDR

SDX

FSR

P

48 SCLKs

Data Command

Data Data Data Data Data

P

Don’t Care Don’t Care

Zeroes

S

Status

(a) With Secondary Request

128 SCLKs

Zeroes Zeroes

P

PPPPPS

Data

P

FSX

16 SCLKs

SDR

SDX

32 SCLKs

PPPPP

Data

Data Data Data Data Data

Zeroes

Zeroes

(b) Without Secondary Request

Don’t Care

Zeroes Zeroes

Data

Figure 6. Data Transfers

12

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