RHBDAP
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On/Off
Input
Shift
Register
DC Input
Shift
Register
7−bit DC Register
Delay
x0
Constant Current
Driver
LOD
MODE
0 1
MODE
0 1
0
15
111
0
On/Off Register
0
6
0
0
01
Temperature
Error Flag
(TEF)
LED Open
Detection
(LOD)
7−bit DC Register
Delay
x1
Constant Current
Driver
LOD
On/Off Register
7
13
1
1
7−bit DC Register
Delay
x15
Constant Current
Driver
LOD
On/Off Register
105
111
15
15
BLANK
0
Max. OUTn
Current
GNDVCC SINSCLK
SOUT
IREF
XERR
XLATMODE
OUT0
OUT1
OUT15
PGND BLANK
BLANK
BLANK
16
16
112
1
16-CHANNEL LED DRIVER WITH DOT CORRECTION
FEATURES APPLICATIONS
• 16 Channels
• Drive Capability
– 0 to 80 mA (Constant-Current Sink)
• Constant Current Accuracy: ±1% (typical)
• Serial Data Interface
• Fast Switching Output: Tr/ Tf= 10ns (typical)
• CMOS Level Input/Output
• 30 MHz Data Transfer Rate
• V
• Operating Temperature = –40 ° C to 85 ° C
• LED Supply Voltage up to 17 V
• 32-pin HTSSOP( PowerPAD™) and QFN
• Dot Correction
• Controlled In-Rush Current
• Error Information
= 3.0 V to 5.5 V
CC
Packages
– 7 bit (128 Steps)
– individual adjustable for each channel
– LOD: LED Open Detection
– TEF: Thermal Error Flag
TLC5923
SLVS550A – DECEMBER 2004 – REVISED NOVEMBER 2005
• Monocolor, Multicolor, Fullcolor LED Display
• Monocolor, Multicolor LED Signboard
• Display Backlighting
• Multicolor LED lighting applications
DESCRIPTION
The TLC5923 is a 16 channel constant-current sink
driver. Each channel has a On/Off state and a
128-step adjustable constant current sink (dot
correction). The dot correction adjusts the brightness
variations between LED, LED channels and other
LED drivers. Both dot correction and On/Off state are
accessible via a serial data interface. A single
external resistor sets the maximum current of all 16
channels.
The TLC5923 features two error information circuits.
The LED open detection (LOD) indicates a broken or
disconnected LED at an output terminal. The thermal
error flag (TEF) indicates an overtemperature
condition.
FUNCTIONAL BLOCK DIAGRAM
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2004–2005, Texas Instruments Incorporated
www.ti.com
TLC5923
SLVS550A – DECEMBER 2004 – REVISED NOVEMBER 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
(1)
(1)
T
A
–40 ° C to 85 ° C
ORDERING INFORMATION
Package Part Number
32-pin, HTSSOP, PowerPAD™ TLC5923DAP
32-pin, 5 mm x 5 mm QFN TLC4923RHB
(1) For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or see the TI website at www.ti.com .
ABSOLUTE MAXIMUM RATINGS
(1) (2)
TLC5923 UNIT
V
Supply voltage
CC
I
Output current (dc) I
O
V
Input voltage range
I
V
Output voltage range
O
ESD rating
T
Storage temperature range –40 to 150 °C
stg
(2)
(2)
(2)
L(LC)
V
, V
, V
, V
(BLANK)
V
(SOUT)
V
(OUT0)
(XLAT)
(SCLK)
, V
(XDOWN)
– V
(OUT15)
, V
(SIN)
(MODE)
–0.3 to 6 V
90 mA
–0.3 to V
–0.3 to V
+ 0.3 V
CC
+ 0.3 V
CC
-0.3 to 18 V
HBM (JEDEC JESD22-A114, Human Body Model) 2 kV
CDM (JEDEC JESD22-C101, Charged Device Model) 500 V
Continuous total power dissipation at (or below) TA= 25 ° C 3.9 W
Power dissipation rating at (or
above) TA= 25 ° C
(3)
HTSSOP (DAP) 42.54 mW/ ° C
QFN (RHB) 27.86 mW/ ° C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) See SLMA002 for more information about PowerPAD™
RECOMMENDED OPERATING CONDITIONS—DC Characteristics
MIN NOM MAX UNIT
V
Supply voltage 3 5.5 V
CC
V
Voltage applied to output, (Out0 - Out15) 17 V
O
V
High-level input voltage 0.8 VCC VCC V
IH
V
Low-level input voltage GND 0.2 VCC V
IL
I
High-level output current V
OH
I
Low-level output current V
OL
I
Constant output current OUT0 to OUT15 80 mA
OLC
T
Operating free-air temperature range -40 85 ° C
A
2
= 5 V at SOUT –1 mA
CC
= 5 V at SOUT, XDOWN 1 mA
CC
www.ti.com
SLVS550A – DECEMBER 2004 – REVISED NOVEMBER 2005
RECOMMENDED OPERATING CONDITIONS—AC Characteristics
V
= 3 V to 5.5 V, TA= -40°C to 85°C (unless otherwise noted)
CC
MIN TYP MAX UNIT
f
SCLK
t
wh0
t
wh1
t
su0
t
su1
t
su2
t
su3
t
h0
t
h1
t
h2
t
h3
Clock frequency SCLK 30 MHz
/t
CLK pulse duration SCLK=H/L 16 ns
wl0
XLAT pulse duration XLAT=H 20 ns
SIN - SCLK ↑ 10 ns
Setup time
SCLK ↑ -XLAT ↓ 10 ns
MODE ↑ ↓ -SCLK ↑ 10 ns
MODE ↑ ↓ -XLAT ↑ 10 ns
SCLK ↑ -SIN 10 ns
Hold time
XLAT ↓-SCLK ↑ 10 ns
SCLK ↑-MODE ↑ ↓ 10 ns
XLAT ↓-MODE ↑ ↓ 10 ns
ELECTRICAL CHARACTERISTICS
V
= 3 V to 5.5 V, TA= –40 ° C to 85 ° C (unless otherwise noted)
CC
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
V
I
I
I
I
I
∆ I
∆ I
∆ I
∆ I
T
V
V
(1) Measured at device start-up temperature. Once the IC is operating (self heating), lower ICCvalues will be seen. See Figure 15 .
(2) Not tested. Specified by design.
High-level output voltage IOH= –1 mA, SOUT VCC– 0.5 V
OH
Low-level output voltage IOL= 1 mA, SOUT 0.5 V
OL
Input current VI= V
I
No data transfer, All output OFF, VO= 1 V, R
No data transfer, All output OFF, VO= 1 V, R
k Ω
Supply current mA
CC
Data transfer 30 MHz, All output ON, VO= 1 V,
R
or GND, BLANK, XLAT, SCLK, SIN, MODE –1 1 µ A
CC
= 10 k Ω 6
(IREF)
= 1.3
(IREF)
= 1.3 k Ω
(IREF)
Data transfer 30 MHz, All output ON, VO= 1 V,
R
= 600 Ω
(IREF)
Constant output current All output ON, VO= 1 V, R
OLC
LO0
Leakage output current
LO1
Constant current error All output ON, VO= 1 V, R
OLC0
Constant current error ± 4% ± 8.5%
OLC1
Power supply rejection ratio All output ON, VO= 1 V, R
OLC2
Load regulation ± 2 ± 6 %/V
OLC3
Thermal error flag threshold Junction temperature, rising temperature
(TEF)
LED open detection threshold 0.3 0.4 V
(LOD)
Reference voltage output R
(IREF)
All output OFF, VO= 15 V, R
OUT15
V
= 5.5 V, No TEF and LOD 10 µ A
XERR
device to device, averaged current from OUT0 to OUT15,
R
= 600 Ω
(IREF)
All output ON, VO= 1 V to 3 V, R
OUT0 to OUT15
= 600 Ω 1.20 1.24 1.28 V
(IREF)
= 600 Ω 70 80 90 mA
(IREF)
= 600 Ω , OUT0 to
(IREF)
= 600 Ω , OUT0 to OUT15 ± 1% ± 4%
(IREF)
= 600 Ω , OUT0 to OUT15 ± 1 ± 4 %/V
(IREF)
= 600 Ω ,
(IREF)
(2)
150 160 180 ° C
36 65
0.1 µ A
TLC5923
15
32
(1)
3
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1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
GND
BLANK
XLAT
SCLK
SIN
PGND
OUT0
OUT1
PGND
OUT2
OUT3
OUT4
OUT5
PGND
OUT6
OUT7
VCC
IREF
MODE
XERR
SOUT
PGND
OUT15
OUT14
PGND
OUT13
OUT12
OUT11
OUT10
PGND
OUT9
OUT8
THERMAL
PAD
SOUT24
PGND23
OUT1522
OUT1421
PGND20
OUT1319
OUT1218
OUT1117
OUT1016
PGND15
OUT914
OUT813
OUT712
OUT611
PGND10
OUT59
OUT4
8
OUT3
7
OUT2
6
PGND
5
OUT1
4
OUT0
3
PGND
2
SIN
1
XERR 25
MODE 26
IREF 27
VCC 28
GND 29
BLANK 30
XLAT 31
SCLK 32
RHB PACKAGE
(TOP VIEW)
(QFN)
DAP PACKAGE
(TOP VIEW)
TLC5923
SLVS550A – DECEMBER 2004 – REVISED NOVEMBER 2005
DISSIPATION RATINGS
PACKAGE
32-pin HTSSOP with PowerPAD
32-pin HTSSOP with PowerPAD
(1) The PowerPAD is soldered to the PCB with a 2 oz. copper trace. See SLMA002 for further information.
soldered
unsoldered
32-pin QFN 3482 mW 27.86 mW/ ° C 2228 mW 1811 mW
SWITCHING CHARACTERISTICS
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
r0
Rise time ns
t
r1
t
f0
Fall time ns
t
f1
t
pd0
t
pd1
t
pd2
Propagation delay time ns
t
pd3
t
pd4
t
pd5
t
Output delay time OUTn ↑ ↓ -OUT(n+1) ↑ ↓ (see
d
POWER RATING DERATING FACTOR POWER RATING POWER RATING
TA< 25 ° C ABOVE TA = 25 ° C TA= 70 ° C TA= 85 ° C
(1)
(1)
SOUT(see
OUTx, V
SOUT (see
OUTx, V
SCLK ↑ - SOUT ↑ ↓ (see
MODE ↑↓ - SOUT ↑ ↓ (see
BLANK ↓ - OUT0 ↑ ↓ (see
XLAT ↑ - OUT0 ↑ ↓ (see
OUTx ↑ ↓ -XERR ↑ ↓ (see
XLAT ↑ -I
5318 mW 42.54 mW/ ° C 3403 mW 2765 mW
2820 mW 22.56 mW/ ° C 1805 mW 1466 mW
(1)
= 5 V, TA= 60 ° C, DCx = 7F (see
CC
(1)
= 5 V, TA= 60 ° C, DCx = 7F (see
CC
(dot-correction) (see
OUT
) 16
) 16
(3)
) 30
(3)
) 30
(4)
) 60
(4)
) 60
(5)
) 1000
(6)
) 1000
(4)
) 14 22 30 ns
(2)
) 10 30
(2)
) 10 30
(1) See Figure 4 . Defined as from 10% to 90%
(2) See Figure 5 . Defined as from 10% to 90%
(3) See Figure 4 , Figure 11
(4) See Figure 5 and Figure 11
(5) See Figure 5 , Figure 6 , and Figure 11
(6) See Figure 5
4
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VCC
INPUT
GND
400
Terminal Functions
TERMINAL
NAME
BLANK 2 30 I
GND 1 29 Ground
IREF 31 27 I/O Reference current terminal
MODE 30 26 I
OUT0 7 3 O Constant current output
OUT1 8 4 O Constant current output
OUT2 10 6 O Constant current output
OUT3 11 7 O Constant current output
OUT4 12 8 O Constant current output
OUT5 13 9 O Constant current output
OUT6 15 11 O Constant current output
OUT7 16 12 O Constant current output
OUT8 17 13 O Constant current output
OUT9 18 14 O Constant current output
OUT10 20 16 O Constant current output
OUT11 21 17 O Constant current output
OUT12 22 18 O Constant current output
OUT13 23 19 O Constant current output
OUT14 25 21 O Constant current output
OUT15 26 22 O Constant current output
PGND Power ground
SCLK 4 32 I
SIN 5 1 I Data input of serial I/F
SOUT 28 24 O Data output of serial I/F
VCC 32 28 Power supply voltage
XERR 29 25 O
XLAT 3 31 I
TSSOP QFN
6, 9, 14, 2, 5, 10,
19, 24, 27 15, 20, 23
NO. I/O DESCRIPTION
Blank (Light OFF). When BLANK=H, All OUTx outputs are forced OFF. When BLANK=L,
ON/OFF of OUTx outputs are controlled by input data.
Mode select. When MODE=L, SIN, SOUT, SCLK, XLAT are connected to ON/OFF control
logic. When MODE=H, SIN, SOUT, SCLK, XLAT are connected to dot-correction logic.
Data shift clock. Note that the internal connections are switched by MODE (pin #30). At
SCLK ↑ , the shift-registers selected by MODE shift the data.
Error output. XERR is open drain terminal. XERR transistions from H to L when LOD or TEF
detected.
Data latch. Note that the internal connections are switched by MODE (pin #30). At XLAT ↑ ,
the latches selected by MODE get new data.
TLC5923
SLVS550A – DECEMBER 2004 – REVISED NOVEMBER 2005
PIN EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
(Note: Resistor values are equivalent resistance and not tested).
Figure 1. Input Equivalent Circuit (BLANK, XLAT, SCLK, SIN, MODE)
5
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SOUT
GND
10
XERR
GND
20
SOUT
15 pF
OUTn
51 Ω
15 pF
XDOWN
470 kΩ
TLC5923
SLVS550A – DECEMBER 2004 – REVISED NOVEMBER 2005
PIN EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS (continued)
Figure 3. Output Equivalent Circuit (XERR)
PARAMETER MEASUREMENT INFORMATION
Figure 2. Output Equivalent Circuit
Figure 4. Test Circuit for tr0, tf0, td0, t
Figure 5. Test Circuit for tr1, tf1, t
Figure 6. Test Circuit for t
d1
, t
, t
pd2
pd3
pd4
, t
pd5
pd6
6
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I
MAX
V
IREF
R
IREF
40
I
Outn
I
MAX
DC
n
127
DC 15.6
111
DC 14.6
104
DC 0.6
6
DC 0.0
0
DC 15.0
105
DC 1.0
7
LSB MSB
DC OUT0 DC OUT15
DC OUT2 − DC OUT14
TLC5923
SLVS550A – DECEMBER 2004 – REVISED NOVEMBER 2005
PRINCIPLES OF OPERATION
Setting Maximum Channel Current
The maximum output current per channel is set by a single external resistor, R
IREF and GND. The voltage on IREF is set by an internal band gap V
maximum channel current is equivalent to the current flowing through R
with a typical value of 1.24V. The
(IREF)
(IREF)
maximum output current can be calculated by Equation 1 :
where:
V
= 1.24V typ.
IREF
R
= User selected external resistor (R
IREF
Figure 12 shows the maximum output current, I
resistor between IREF terminal to ground, and I
should not be smaller than 600 Ω)
IREF
, versus R
O(LC)
is the constant output current of OUT0,.....OUT15.
O(LC)
(IREF)
. In Figure 12 , R
Setting Dot-Correction
The TLC5923 has the capability to fine adjust the current of each channel, OUT0 to OUT15 independently. This
is also called dot correction. This feature is used to adjust the brightness deviations of LED connected to the
output channels OUT0 to OUT15. Each of the 16 channels can be programmed with a 7-bit word. The channel
output can be adjusted in 128 steps from 0% to 100% of the maximum output current I
determines the output current for each OUTn:
, which is placed between
(IREF)
multiplied by a factor of 40. The
is the value of the
(IREF)
. Equation 2
MAX
(1)
where:
I
= the maximum programmable current of each output
Max
DCn = the programmed dot-correction value for output n (DCn = 0, 1, 2 ...127)
n = 0, 1, 2 ... 15
Dot correction data are entered for all channels at the same time. The complete dot correction data format
consists of 16 x 7-bit words, which forms a 112-bit wide serial data packet. The channel data is put one after
another. All data is clocked in with MSB first. Figure 7 shows the DC data format.
Figure 7. DC Data Format
To input data into dot correction register, MODE must be set to high. The internal input shift register is then set to
112 bit width. After all serial data is clocked in, a rising edge of XLAT latch the data to the dot correction register
(Figure 11 ).
Output Enable
All OUTn channels of TLC5923 can switched off with one signal. When BLANK signal is set to high, all OUTn are
disabled, regardless of On/Off status of each OUTn. When BLANK is the to low, all OUTn work under normal
conditions.
(2)
7
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150
MSBLSB
On/Off Data
On/Off
OUT0
On/Off
OUT1
On/Off
OUT2
On/Off
OUT3
On/Off
OUT4
On/Off
OUT5
On/Off
OUT6
On/Off
OUT7
On/Off
OUT8
On/Off
OUT9
On/Off
OUT10
On/Off
OUT11
On/Off
OUT12
On/Off
OUT13
On/Off
OUT14
On/Off
OUT15
TLC5923
SLVS550A – DECEMBER 2004 – REVISED NOVEMBER 2005
Table 1. BLANK Signal Truth Table
BLANK OUT0 - OUT15
LOW Normal condition
HIGH Disabled
Setting Channel On/Off Status
All OUTn channels of TLC5923 can be switched on or off independently. Each of the channels can be
programmed with a 1-bit word. On/Off data are entered for all channels at the same time. The complete On/Off
data format consists of 16 x 1-bit words, which form a 16-bit wide data packet. The channel data is put one after
another. All data is clocked in with MSB first. Figure 8 shows the On/Off data format.
Figure 8. On/Off Data
To input On/Off data into On/Off register MODE must be set to low. The internal input shift register is then set to
16 bit width. After all serial data is clocked in, a rising edge of XLAT is used to latch data into the On/Off register.
Figure 11 shows the On/Off data input timing chart.
With the falling edge of XLAT signal all data in input shift register is replaced with LOD channel data. These data
is clocked out to SOUT when new On/Off data is clocked in.
Delay Between Outputs
The TLC5923 has graduated delay circuits between outputs. These delay circuits can be found in the constant
current block of the device (see Functional Block Diagram). The fixed delay time is 20 ns (typical), OUT0 has no
delay, OUT1 has 20 ns delay, OUT2 has 40 ns delay, etc. This delay prevents large inrush currents, which
reduce power supply bypass capacitor requirements when the outputs turn on. The delay works during switch on
and switch off of each output channel. LEDs that have not turned on before BLANK is pulled high will still turn on
and off at the determined delayed time regardless of the state of BLANK. Therefore, every LED will be
illuminated for the amount of time BLANK is low.
Serial Interface Data Transfer Rate
The TLC5923 includes a flexible serial interface, which can be connected to microcontroller or digital signal
processor. Only 3 pins are in required to input data into the device. The rising edge of SCLK signal shifts the
data from SIN pin to internal shift register. After all data is clocked in, a rising edge of XLAT latches the serial
data to the internal registers. All data is clocked in with MSB first. Multiple TLC5923 devices can be cascaded by
connecting SOUT pin of one device with SIN pin of following device. The SOUT pin can also be connected to
controller to receive LOD information from TLC5923.
8
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TLC5923
SIN SOUT
OUT0 OUT15
SCLK
MODE
XLAT
BLANK
IREF
XERR
TLC5923
SIN SOUT
OUT0 OUT15
SCLK
MODE
XLAT
BLANK
IREF
XERR
IC 0 IC n
5
SIN
SCLK
MODE
XLAT
BLANK
XERR
Controller
SOUT
100 k
100 nF
V
(LED)
V
(LED)
V
(LED)
V
(LED)
V
CC
100 nF
V
CC
V
CC
f_(SCLK) 112 f_(update) n
TLC5923
SLVS550A – DECEMBER 2004 – REVISED NOVEMBER 2005
Figure 9. Cascading Devices
Figure 9 shows a example application with n cascaded TLC5923 devices connected to a controller. The
maximum number of cascaded TLC5923 devices depends on application system and data transfer rate.
Equation 3 calculates the minimum data input frequency needed.
where:
f_(SCLK): The minimum data input frequency for SCLK and SIN.
f_(update): The update rate of the whole cascaded system.
n: The number of cascaded TLC5923 devices.
Operating Modes
The TLC5923 has different operating modes depending on MODE signal. Table 2 shows the available operating
modes.
Table 2. TLC5923 Operating Modes Truth Table
MODE SIGNAL INPUT SHIFT REGISTER MODE
LOW 16 bit On/Off Mode
HIGH 112 bit Dot Correction Data Input Mode
(3)
9
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LOD
OUT15
150
MSBLSB
LOD Data
LOD
OUT14
LOD
OUT13
LOD
OUT12
LOD
OUT11
LOD
OUT10
LOD
OUT9
LOD
OUT8
LOD
OUT7
LOD
OUT6
LOD
OUT5
LOD
OUT4
LOD
OUT3
LOD
OUT2
LOD
OUT1
LOD
OUT0
TLC5923
SLVS550A – DECEMBER 2004 – REVISED NOVEMBER 2005
Error Information Output
The open-drain output XERR is used to report both of the TLC5923 error flags, TEF and LOD. During normal
operating conditions, the internal transistor connected to the XERR pin is turned off. The voltage on XERR is
pulled up to V
and XERR is pulled to GND. Since XERR is an open-drain output, multiple ICs can be OR'ed together and pulled
up to V
with a single pullup resistor. This reduces the number of signals needed to report a system error.
CC
To differentiate LOD and TEF signal from XERR pin, LOD can be masked out with BLANK = HIGH.
TEMPERATURE OUNTn VOLTAGE TEF LOD BLANK XERR
TEF: Thermal Error Flag
The TLC5923 provides a temperature error flag (TEF) circuit to indicate an overtemperature condition of the IC. If
the junction temperature exceeds the threshold temperature T
XERR to ground.
through a external pullup resistor. If TEF or LOD is detected, the internal transistor is turned on,
CC
Table 3. XERR Truth Table
ERROR CONDITION ERROR INFORMATION SIGNALS
TJ< T
TJ> T
TJ< T
TJ> T
(TEF)
(TEF)
(TEF)
(TEF)
Don't Care L X H H
Don't Care H X L
OUTn > V
OUTn < V
OUTn > V
OUTn < V
(LOD)
(LOD)
(LOD)
(LOD)
L L L H
L H L
H L L
H H L
(160°C typical), the TEF circuit trips and pulls
(TEF)
LOD: LED Open Detection
The TLC5923 provides an LED open-detection circuit (LOD). This circuit reports an error if any one of the 16
LEDs is open or disconnected from the circuit. The LOD circuit trips when the following two conditions are met
simultaneously:
1. BLANK is set to LOW
2. When the voltage at OUTn is less than V
after being turned on).
The LOD circuit also pulls XERR to GND when tripped.
The LOD status of each channel can also be read out from the TLC5923 SOUT pin. When MODE is low and
On/Off data is latched with rising edge of XLAT, LOD data is written to the input shift register with the falling edge
of XLAT. These LOD data is clocked out to SOUT when new On/Off data is clocked in. These allow to control the
LOD status of each OUTn channel. Figure 10 shows the LOD data format.
(0.3 V typ.) (Note: the voltage at each OUTn is sampled 1 µ s
(LOD)
Figure 10. LOD Data
10
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SCLK
SOUT
SIN
MODE
XLAT
On/Off Mode Data
Input Cycle
DC Mode Data Input Cycle
BLANK
XERR
OUT0
OUT1
DC Mode Data Input
Cycle
On/Off Mode Data
Input Cycle
On/Off Mode Data
Input Cycle
t
wh1
f
CLK
t
wl0
t
su1
t
wh0
t
h0
t
pd0
t
h2
t
su2
t
h1
t
h3
t
pd1
t
pd1
t
su3
t
h3
t
su3
t
pd2
t
pd4
t
d
t
pd5
t
pd2
t
pd5
t
pd3
On/Off
LSB
On/Off
MSB
DC
MSB
MSB
DC
LSB
DC
MSB
DC
MSB
DC
LSB
DC
MSB
On/Off
MSB
On/Off
MSB
LSB
On/Off
MSB
On/Off
MSB
On/Off
MSB
On/Off
DC
LSB
DC
LSB
On/Off
LSB
DC
On/Off
MSB−1
t
su0
(current)
(current)
t
d
TLC5923
SLVS550A – DECEMBER 2004 – REVISED NOVEMBER 2005
Figure 11. Timing Chart Example for ON/OFF Setting to Dot-Correction
11
www.ti.com
827
100
1 k
10 k
100 k
0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.080
49.6 k
9.92 k
4.96 k
2.48 k
1.65 k
1.24 k
709
− Reference Resistor −
I
OLC
− Output Current − mA
R
IREF
Ω
V
Outn
= 1 V
DC = 127
992
0
10
20
30
40
50
60
70
80
90
100
0 0.50 1 1.50 2 2.50 3
I
O
− Output Current − mA
VO − Output Voltage − V
I
MAX
= 60 mA
I
MAX
= 40 mA
I
MAX
= 20 mA
3 k
2 k
1 k
0
−40 −20 0 20 40
4 k
5 k
6 k
60 80 100
TA − Free-Air Temperature − °C
− Power Dissipation − mW
P
D
TLC5923DAP
PowerPAD Soldered
TLC5923RHB
TLC5923DAP
PowerPAD Unsoldered
0
10
20
30
40
50
60
70
−50 −30 −10 10 30 50 70 90 110 130 150
I
CC
− Supply Current − mA
TA − Free-Air Temperature − °C
TLC5923
SLVS550A – DECEMBER 2004 – REVISED NOVEMBER 2005
TYPICAL CHARACTERISTICS
Power Rating – Free-Air Temperature
Figure 14 shows total power dissipation. Figure 15 shows supply current versus free-air temperature.
12
Figure 12. Reference Resistor vs Output Current Figure 13. Output Current vs Output Voltage
Power Dissipation Supply Current
vs vs
Temperature Free-Air Temperature
Figure 14.
A. Data Transfer = 30 MHz / All Outputs,
ON/V
O
= 1 V / R
IREF
= 600 Ω / AV
Figure 15.
(A)
= 5 V
DD
PACKAGE OPTION ADDENDUM
www.ti.com
22-Sep-2006
PACKAGING INFORMATION
Orderable Device Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
TLC5923DAP ACTIVE HTSSOP DAP 32 46 Green (RoHS &
no Sb/Br)
TLC5923DAPG4 ACTIVE HTSSOP DAP 32 46 Green (RoHS &
no Sb/Br)
TLC5923DAPR ACTIVE HTSSOP DAP 32 2000 Green (RoHS &
no Sb/Br)
TLC5923DAPRG4 ACTIVE HTSSOP DAP 32 2000 Green (RoHS &
no Sb/Br)
TLC5923RHBR ACTIVE QFN RHB 32 3000 Green (RoHS &
no Sb/Br)
TLC5923RHBRG4 ACTIVE QFN RHB 32 3000 Green (RoHS &
no Sb/Br)
TLC5923RHBT ACTIVE QFN RHB 32 250 Green (RoHS &
no Sb/Br)
TLC5923RHBTG4 ACTIVE QFN RHB 32 250 Green (RoHS &
no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Lead/Ball Finish MSL Peak Temp
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
(3)
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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