Texas Instruments TLC5910PZP Datasheet

D

Drive Capability and Output Counts – 80 mA (Current Sink) x 16 Bits

D

Constant Current Output Range – 5 to 80 mA (Current Value Setting for All

Output Terminals Using External Resistor and Internal Brightness Control Register)

D

Constant Current Accuracy – ±4% (Maximum Error Between Bits)

D

Voltage Applied to Constant Current Output Terminals – Minimum 0.4 V (Output Current 5 to

40 mA)

– Minimum 0.7 V (Output Current 40 to

80 mA)

D

1024 Gray Scale Display – Pulse Width Control 1024 Steps

D

Brightness Adjustment – All Output Current Adjustment for 64

Steps (Adjustment for Brightness Deviation Between LED Modules)

– Output Current Adjustment by Output

(OUT0 to OUT15) for 64 Steps (Adjustment for Brightness Deviation Between Dots)

– Brightness Control by 16 Steps

Frequency Division Gray Scale Control Clock (Brightness Adjustment for Panel)

D

Gray Scale Clock Generation – Gray Scale Control Clock Generation by

Internal PLL or External Input Selectable

D

Clock Invert/Noninvert Selectable – Clock Invert Selectable to Reduce

Changes in Duty Ratio at Cascade Operation

†

LED DRIVER

SLLS392 – NOVEMBER 1999

D

Protection – WDT (Watchdog Timer) Function (Turn

Output Off When Scan Signal Stopped)

– TSD (Thermal Shutdown) Function (Turn

Output Off When Junction Temperature Exceeds Limit)

D

LOD – LED Open Detection (Detection for LED

Disconnection)

D

Data Input/Output – Port A (for Data Display)

– Clock Synchronized 10 Bit Parallel

Input (Schmitt Triggered Input)

– Clock Synchronized 10 Bit Parallel

Output (3-State Output)

– Port B (for Dot Correction Data)

– Clock Synchronized 6 Bit Parallel

Input (Schmitt-Triggered Input)

– Clock Synchronized 6 Bit Parallel

Output

D

Input/Output Signal Level – CMOS Level

D

Power Supply Voltage – 4.5 V to 5.5 V (Logic, Analog and

Constant Current)

– 3 V to 5.5 V (Interface)

D

Maximum Output Voltage . . . 15 V (Max)

D

Data Transfer Rate . . . 20 MHz (Max)

D

Gray Scale Clock Frequency – 16 MHz (Max) Using Internal PLL – 8 MHz (Max) Using External Clock

D

Operating Free-Air Temperature Range –20°C to 85°C

D

100-Pin HTQFP Package (PD=4.7 W, T

= 25°C)

A

‡

TLC5910

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

†

These functions are adjustable independently.

‡

Allows the writting of all the data at port A by setting the logic to 1.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1999, Texas Instruments Incorporated

1

TLC5910 LED DRIVER

SLLS392 – NOVEMBER 1999

description

The TLC5910 is a constant current driver, incorporating a shift register , data latch, and constant current circuitry with current value adjustable, PLL circuitry for gray scale control clock generation, and 1024 gray scale display using pulse width control. The output current is a maximum of 80 mA with 16 bits, and the current value of constant current output can be set by one external resistor. The device has two channel I/O ports. The brightness deviation between LED modules (ICs) can be adjusted by external data input from a display data port. The brightness control for the panel can be accomplished by the brightness adjustment circuitry. Independently of these functions, the device incorporates the shift register and data latch to correct the deviation between LEDs adjusting output current using data from a dot correction data port. Moreover, the device incorporates watchdog timer (WDT) circuitry , which turns the constant current output off when a scan signal is stopped at the dynamic scanning operation. It incorporates thermal shutdown (TSD) circuitry, which turns constant current output off when the junction temperature exceeds the limit. It also incorporates LOD (LED open detection) circuitry, which creates an error signal output when LED disconnection occurs and test mode functions detect LED open or short conditions.

PZP PACKAGE

(TOP VIEW)

GNDLED

OUT0 OUT1

GNDLED

OUT2 OUT3

GNDLED

OUT4 OUT5

GNDLED

OUT6 OUT7

GNDLED

OUT8 OUT9

GNDLED

OUT10

OUT11

GNDLED

OUT12 OUT13

GNDLED

OUT14 OUT15

GNDLED

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

TEST4

TEST3

99

100

27

26

GNDLOG

TEST2

DPOL

96

97

98

30

29

28

DCENA

BCENA

VCCLOG

93

94

95

33

32

31

VCCIF

DCDIN5

91

92

35

34

DCDIN4

DCDIN3

DCDIN2

88

89

90

38

37

36

DCDIN1

DCDIN0

DIN9

85

86

87

41

40

39

DIN8

DIN7

83

84

43

42

DIN6

DIN5

81

82

45

44

DIN4

DIN3

79

80

47

46

DIN2

DIN1

77

78

49

48

DIN0

76

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

50

VCOIN RBIAS MAG0 MAG1 MAG2 PDOUT GSPOL GSCLK BLANK XENABLE XOE DCLK XLA TCH DCCLK XDCLAT RSEL0 RSEL1 LEDCHK OPEN WDTRG XDOWN1 XDOWN2 BOUT XGSOUT XPOUT

IREF

TEST1

TSENA

VCCLED

WDCAP

GNDANA

XDWN2TST

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

XRST

VCCANA

DCDOUT5

DCDOUT4

DCDOUT3

DCDOUT2

DCDOUT1

DOUT9

DOUT8

DOUT7

DCDOUT0

DOUT6

DOUT5

DOUT4

DOUT3

DOUT2

DOUT1

DOUT0

functional block diagram

XOE BCENA

DCLK

DPOL XENABLE

DCLK

Control

TLC5910

LED DRIVER

SLLS392 – NOVEMBER 1999

DOUTt0–9

u

DINt0–9u,

XLATCH

RSELt0–1

DCDINt0–5u,

MAGt0–2u, GSPOL,

BLANK

XRST

WDCAP

WDTRG

LEDCHK

XDOWN2TST

TSENA

IREF

DCENA

u

XDCLAT,

DCCLK

GSCLK, RBIAS,

VCOIN, PDOUT

1 x 10 bit B.C.

Data Shift Register

Data Latch

8

PLL

WDT

TSD

10 bit

Clock Countor

16 x 10 bit

Data Shift Register

..........

16 x 10 bit

Data Latch

..........

16 x 10 bit

Data Comparator

..........

16 bit

LED Driver+LOD

..........

16 bit

Current Controller

..........

16 x 6 bit

D.C. Data Latch

XPOUT XGSOUT

BOUT OUT0

· · ·

OUT15 XDOWN1

XDOWN2

..........

16 x 6 bit

D.C. Data Shift Register

B.C. (brightness control) : Adjustment for brightness deviation between LED modules, and between panels. D.C (Dot Control) : Adjustment for brightness deviation between dots.

NOTE: All the input terminals are with Schmitt-triggered inverters except RBIAS, VCOIN, PDOUT, IREF, and WDCAP.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DCDOUTt0–5

u

3

TLC5910

CONNECTION

LED DRIVER

SLLS392 – NOVEMBER 1999

functional block diagram for shift register and data latch

XOE

DCLK DPOL

XENABLE

DCCLK

DIN<0–9>

DCDIN<0–5>

XLATCH

XDCLAT

RSEL<0–1>

DCLK

Controller

10

6

DATA

10

a

A

b

B

c

a

A

b

B

c

a

A

b

B

c

S/R

B.C.

S/R

6

D.C.

S/R

10 16 10 16

†

1

‡

2

6 16

DATA

LATCH

10 10

10 1010

B.C.

LATCH

6

D.C.

LATCH

6 16

a b

c

HI–Z

DATA Comparator

A

1

0

1

10

Clock Counter Current Controller

6 16

10

DOUT<0–9>

DCDOUT<0–5>

DATA Comparator

6 16

BCENA

DCENA

†

1 : Connect to 16th 10 bit bus

‡

2 : Connect to 16th 6 bit bus B.C. (brightness control) : Adjustment for brightness deviation between LED modules, and between panels. D.C. (dot control) : Adjustment for brightness deviation between dots.

RSEL

RSEL1 RSEL0

0 0 A – a, B – c 0 1 A – b, B – c 1 0 A – c 1 1 INHIBIT

Default

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

schematic

TLC5910

LED DRIVER

SLLS392 – NOVEMBER 1999

Input

DOUT0–9, DCDOUT0–5, XGSOUT, XPOUT, BOUT

XDOWN1, XDOWN2

VCCIF

INPUT

GNDLOG

XDOWN1, XDOWN2

VCCLOG

OUTPUT

GNDLOG

OUTn

GNDLOG

OUTn

GNDLED

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

TLC5910

I/O

DESCRIPTION

Á

LED DRIVER

SLLS392 – NOVEMBER 1999

TERMINAL

NAME NO.

ÁÁÁÁ

BCENA

ÁÁÁÁ

BLANK

ÁÁÁÁ

BOUT

DCCLK

ÁÁÁÁ

DCDIN0 – DCDIN5

DCDOUT0 –

ÁÁÁÁ

DCDOUT5 DCENA

ÁÁÁÁ

DCLK

ÁÁÁÁ

DIN0 – DIN9

ÁÁÁÁ

DOUT0 – DOUT9

ÁÁÁÁ

DPOL

ÁÁÁÁ

GNDANA GNDLOG

GNDLED

ÁÁÁÁ

GSCLK

ÁÁÁÁ

GSPOL

ÁÁÁÁ

IREF

ÁÁÁÁ

LEDCHK MAG0 – MAG2

OPEN

ÁÁÁÁ

76,77,78,79,80,

81,82,83,84,85

ÁÁÁÁ

50,49,48,47,46,

45,44,43,42,41

ÁÁÁÁ

94

67

53

62

86,87,88,

89,90,91

40,39,38,

37,36,35

95

64

96 28

98

1,4,7,10,13, 16,19,22,25

68

69

32

58

73,72,71

57

Terminal Functions

Brightness control enable. When BCENA is low, brightness control latch is set to the default

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value. The output current value in this status is 100% of setting the value by an external resistor.

I

The frequency division ratio of GSCLK is 1/1. When BCENA is high, writing to brightness control

БББББББББББББББББББББ

latch is enabled. Blank(light off). When BLANK is high, all outputs of the constant current driver are turned off.

When GSPOL is high, the output is turned on (LED on), synchronizing to the falling edge of

БББББББББББББББББББББ

GSCLK after the next rising edge of GSCLK, when BLANK goes from high to low. When GSPOL

I

БББББББББББББББББББББ

is low, the output is turned on (LED on), synchronizing to the rising edge of GSCLK after the next falling edge of GSCLK, when BLANK goes from high to low.

БББББББББББББББББББББ

O

BLANK buffered output Clock input for data transfer. The input data is from DCDIN (port B) , output data at DCDOUT,

and all data on the shift register for dot correction data, from DCDIN, is shifted by 1 bit

I

БББББББББББББББББББББ

synchronizing to the rising edge of DCCLK. Input for 6 bit parallel data (port B). These terminals are used as a shift register input for dot

I

correction data. Output for 6 bit parallel data (port B). These terminals are used as a shift register output for dot

O

БББББББББББББББББББББ

correction data. Latch enable for dot correction data. When DCENA is low, the latch is set to the default value.

I

At this time, the output current value is 100% of the value set by an external resistor. Clock input for data transfer. The input data is from DIN (port A) , all data on the shift register

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selected by RSEL, 1 and output data at DOUT is shifted by 1 bit synchronizing to DCLK. Note

I

that synchronizing to either the rising or falling edge of DCLK depends on the value of DPOL.

БББББББББББББББББББББ

Input for 10 bit parallel data (port A). These terminals are inputs to the shift register for gray scale data, brightness control, and dot correction data. The register selected is determined by RSEL0,

I

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1. Output for 10 bit parallel data (port A). These terminals are outputs to the shift register for gray

scale data, brightness control, and dot correction data. The register selected is determined by

O

БББББББББББББББББББББ

RSEL0, 1. Select the valid edge of DCLK. When DPOL is high, the rising edge of DCLK is valid. When

I

DPOL is low, the falling edge of DCLK is valid.

БББББББББББББББББББББ

Analog ground (internally connected to GNDLOG and GNDLED) Logic ground (internally connected to GNDANA and GNDLED)

LED driver ground (internally connected to GNDANA and GNDLED)

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Clock input for gray scale. When MAG0 to MAG2 are all low, GSCLK is used for pulse width control, and GSCLK is used for PLL timing control when either MAG is not low. The gray scale

БББББББББББББББББББББ

I

display is accomplished by lighting LEDs on until the number of GSCLK or PLL clocks counted

БББББББББББББББББББББ

is equal to data latched. Select the valid edge of GSCLK. When GSPOL is high, the rising edge of GSCLK is valid. When

I

GSPOL is low, the falling edge of GSCLK is valid. Constant current value setting. LED current is set to the desired value by connecting an external

БББББББББББББББББББББ

resistor between IREF and GND. The 38 times current compares current across the external

I/O

resistor sink on the output terminal.

БББББББББББББББББББББ

LED disconnection detection enable. When LEDCHK is high, LED disconnection detection is

I

enabled and XDOWN2 is valid. When LEDCHK is low, LED disconnection detection is disabled.

I

PLL multiple ratio setting. The clock frequency generated by PLL referenced to GSCLK is set. TEST. Factory test terminal. OPEN should be opened.

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

I/O

DESCRIPTION

Á

ББББББ

Á

TERMINAL

NAME NO.

ÁÁÁÁ

OUT0–DOUT15

ÁÁÁÁ

PDOUT RBIAS

ÁÁÁÁ

RSEL0 RSEL1

ÁÁÁÁ

TEST1–TEST4 THERMAL PAD

TSENA VCOIN

VCCANA VCCLOG VCCIF VCCLED

WDTRG

ÁÁÁÁ

WDCAP

ÁÁÁÁ

XDCLAT

ÁÁÁÁ

XDOWN1

ÁÁÁÁ

XDOWN2

XDWN2TST

ÁÁÁÁ

XENABLE

XGSOUT

ÁÁÁÁ

XLATCH

ÁÁÁÁ

XOE

ÁÁÁÁ

XPOUT XRST

2,3,5,6,8,9,11,12,

ÁÁÁÁ

14,15,17,18,20,21,

23,24

ÁÁÁÁ

70 74

ÁÁÁÁ

60 59

ÁÁÁÁ

29,97,99,100

package bottom

31 75

33 93 92 26

56

ÁÁÁÁ

30

ÁÁÁÁ

61

ÁÁÁÁ

55

ÁÁÁÁ

54

27

ÁÁÁÁ

66

52

ÁÁÁÁ

63

ÁÁÁÁ

65

ÁÁÁÁ

51 34

LED DRIVER

SLLS392 – NOVEMBER 1999

Terminal Functions (Continued)

I/O I/O

I/O

Á

O

Á

I

Á

I

Á

I

Á

O

Á

O

I

Á

I

O

Á

I

Á

I

Á

O

I

БББББББББББББББББББ

Constant current output

БББББББББББББББББББ

Resistor connection for PLL feedback adjustment Resistor connection for PLL oscillation frequency setting Input/output port selection and shift register data latch switching.

БББББББББББББББББББ

When RSEL1 is low and RSEL0 is low, the gray scale data shift register latch is selected to port A and the dot correction register latch is selected to port B.

БББББББББББББББББББ

When RSEL1 is low and RSEL0 is high, the brightness control register latch is selected to

БББББББББББББББББББ

port A and the dot correction register latch is selected to port B. When RSEL1 is high and RSEL0 is low, the dot correction register latch is selected to port

БББББББББББББББББББ

A and no register latch is selected to port B. TEST. Factory test terminal. These terminals should be connected to GND. Heat sink pad. This pad is connected to the lowest potential IC or thermal layer. TSD(thermal shutdown) enable. When TSENA is high, TSD is enabled. When TSENA is

low, TSD is disabled. Capacitance connection for PLL feedback adjustment Analog power supply voltage Logic power supply voltage Interface power supply voltage LED driver power supply voltage WDT (watchdog timer) trigger input. By applying a scan signal to this terminal, the scan

signal can be monitored by turning the constant current output off and protecting the LED

БББББББББББББББББББ

from damage when the scan signal stopped during the constant period designed. WDT detection time adjustment. WDT detection time is adjusted by connecting a capacitor

between WDCAP and GND. When WDCAP is directly connected to GND, WDT function

БББББББББББББББББББ

is disabled. In this case, WDTRG should be tied to a high or low level. Data latch for dot correction. When XDCLAT is high, data on the shift register for dot

БББББББББББББББББББ

correction data from DCDIN (port B) goes through latch. When XDCLAT is low, data is latched. Accordingly , if data on the shift register is changed during XDCLAT high, this new

БББББББББББББББББББ

value is latched (level latch). Shutdown. XDOWN1 is configured as an open collector. It goes low when constant current

output is shut down by WDT or TSD function.

БББББББББББББББББББ

LED disconnection detection output. XDOWN2 is configured as an open collector. XDOWN2 goes low when an LED disconnection is detected.

T est for XDOWN2. When XDWN2TST is low, XDOWN2 goes low . (This terminal is internally

БББББББББББББББББББ

pulled up with 50 kΩ) DCLK enable. When XENABLE is low, data transfer is enabled. Data transfer starts on the

valid edge of DCLK after XENABLE goes low. During XENABLE high, no data is transferred. Clock output for gray scale. When MAG0 to MAG2 are all low, the clock with GSCLK inverted

БББББББББББББББББББ

appears on this terminal. When either MAG is not low, PLLCLK appears on this terminal. Latch. When XLATCH is high, data on the shift register from DIN (port A) goes through latch.

When XLATCH is low, data is latched. Accordingly, if data on the shift register is changed

БББББББББББББББББББ

during XLATCH high, this new value is latched (level latch). Data output enable. When XOE is low, DOUT0–9 terminals are driven. When XOE is high,

DOUT0–9 terminals go to a high

БББББББББББББББББББ

-impedance state.

GSPOL output inverted Blank (Light off). When XRST is low, all the output of the constant current driver is turned

off. (This terminal is internally pulled up with 50 kΩ)

TLC5910

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7

TLC5910

Á

mA

LED DRIVER

SLLS392 – NOVEMBER 1999

absolute maximum ratings (see Note 1)

†

Logic supply voltage, VCCLOG – 0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Supply voltage for interface circuit, VCCIF – 0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Supply voltage for constant current circuit, VCCLED – 0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Analog supply voltage, VCCANA – 0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output current (dc), I

85 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O(LC)

Input voltage range, VI – 0.3 V to VCCLOG + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, V

and V

XGSOUT

Output voltage range, V

O(DOUT)

– 0.3 V to VCCLOG + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O(OUT)

Storage temperature range, T

, V

O(DCDOUT)

and V

O(XDOWNn)

–40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

str

, V

BOUT

, V

XPOUT

– 0.3 V to 16 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous total power dissipation at (or below) TA = 25°C 4.7 W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power dissipation rating at (or above) T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to the GNDLOG terminal.

= 25°C 38.2 mW/°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A

recommended operating conditions

dc characteristics

PARAMETER

Logic supply voltage, VCCLOG Supply voltage for interface circuit,

VCCIF Supply voltage for constant current

БББББББББ

circuit, VCCLED Analog power supply, VCCANA

Voltage between VCC, V

БББББББББ

Voltage between GND, V

БББББББББ

DIFF1

DIFF2

Voltage applied to constant current

БББББББББ

output, V High-level input voltage, V Low-level input voltage, V

High–level output current, I

БББББББББ

Low–level output current, I

Constant output current, I

OUT

IH

IL

OH

OL

OLC

Operating free-air temperature range, T

A PLL capacitance, C PLL resistor, R PLL resistor, R

VCO BIAS PD

ББББББББББÁÁÁÁ

V

DIFF1

VCCLOG – VCCLED

ББББББББББ

VCCANA – VCCLED V

DIFF2

GNDLOG – GNDLED

ББББББББББ

GNDANA – GNDLED OUT0 to OUT15 off

ББББББББББ

VCCLOG = 4.5 V, DOUT0 to DOUT9, DCDOUT0 to DCDOUT5, BOUT, XGSOUT, XPOUT

ББББББББББ

VCCLOG = 4.5V, DOUT0 to DOUT9, DCDOUT0 to DCDOUT5,

ББББББББББ

BOUT, XGSOUT, XPOUT VCCLOG = 4.5 V, XDOWN1, XDOWN2 OUT0 to OUT15

At 16 MHz oscillation

TEST CONDITIONS

= VCCLOG – VCCANA

= GNDLOG – GNDANA

MIN

ÁÁÁ

ÁÁÁÁÁÁÁÁÁ

0.8 VCCLOG GNDLOG

4.5

3.0

4.5

– 0.3

NOM

Á

5

ÁÁÁ

5

0

ÁÁÁ

0

ÁÁÁ

0.2 VCCLOG

MAX

5.5

0.3

15

VCCLOG

– 1.0

ÁÁÁÁÁÁÁÁÁ

5

– 20

1.0

80

85

1 22 30

UNIT

V V

V

Á

V

Á

V

Á

V

Á

V V

Á

5

mA mA

°C

µF kΩ kΩ

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DCLK, DCCLK clock frequenc

f

MH

Á

TLC5910

LED DRIVER

SLLS392 – NOVEMBER 1999

ac characteristics, VC CLOG= VCCANA = VCCLED = 4.5 V to 5.5 V, T

PARAMETER

y,

DCLK, DCCLK pulse duration (high or low level), twh/t GSCLK clock frequency, f

GSCLK

GSCLK pulse duration (high or low level), twh/t WDT clock frequency, f

WDT

WDT pulse duration (high or low level), twh/t XLATCH, XDCLAT pulse duration (high level), t Rise / fall time, tr/t

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Setup time, t

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Hold time, t

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f

su

h

DCLK,

DCCLK

wl

wh

TEST CONDITIONS

At single operation At cascade operation

DINn – DCLK

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DCDINn – DCCLK BLANK – GSCLK

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XENABLE – DCLK

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XLATCH – DCLK XLATCH – GSCLK

БББББББ

XDCLAT – DCCLK RSEL – DCLK

БББББББ

RSEL – DCCLK

БББББББ

RSEL – XLATCH RSEL – XDCLAT

БББББББ

DINn – DCLK DCDINn – DCCLK

БББББББ

XENABLE – DCLK XLATCH – DCLK

БББББББ

XDCLAT – DCCLK

БББББББ

RSEL – DCLK RSEL – DCCLK

БББББББ

RSEL – XLATCH

БББББББ

RSEL – XDCLAT

= – 20 to 85°C (unless otherwise noted)

A

MIN

TYP

MAX

UNIT

20 15

20

8

40

8 40 30

100

5

Á

10 15 10 10 10 10 15 30 15

Á

5

Á

15 15

Á

20 30 20 20 20 20 10

Á

z

ns

MHz

ns

MHz

ns ns ns

ns

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9

Texas Instruments TLC5910PZP Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual