Texas Instruments TLC5618AQDR, TLC5618AQD, TLC5618AMJGB, TLC5618AMJG, TLC5618AMFKB Datasheet

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TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156E – JULY 1997 – REVISED SEPTEMBER 1999
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
D
Programmable Settling Time to 0.5 LSB
D
Two 12-Bit CMOS Voltage Output DACs in an 8-Pin Package
D
Simultaneous Updates for DAC A and DAC B
D
Single Supply Operation
D
3-Wire Serial Interface
D
High-Impedance Reference Inputs
D
Voltage Output Range ... 2 Times the Reference Input Voltage
D
Software Powerdown Mode
D
Internal Power-On Reset
D
TMS320 and SPI Compatible
D
Low Power Consumption:
3 mW Typ in Slow Mode, 8 mW Typ in Fast Mode
D
Input Data Update Rate of 1.21 MHz
D
Monotonic Over Temperature
D
Available in Q-Temp Automotive
HighRel Automotive Applications Configuration Control / Print Support Qualification to Automotive Standards
applications
D
Battery Powered Test Instruments
D
Digital Offset and Gain Adjustment
D
Battery Operated/Remote Industrial Controls
D
Machine and Motion Control Devices
D
Cellular Telephones
description
The TLC5618 is a dual 12-bit voltage output digital-to-analog converter (DAC) with buffered reference inputs (high impedance). The DACs have an output voltage range that is two times the reference voltage, and the DACs are monotonic. The device is simple to use, running from a single supply of 5 V. A power-on reset function is incorporated in the device to ensure repeatable start-up conditions.
Digital control of the TLC5618 is over a 3-wire CMOS-compatible serial bus. The device re­ceives a 16-bit word for programming and producing the analog output. The digital inputs feature Schmitt triggers for high noise immunity. Digital communication protocols include the SPI, QSPI, and Microwire standards.
Two versions of the device are available. The TLC5618 does not have an internal state machine and is dependent on all external timing signals. The TLC5618A has an internal state machine that counts the number of clocks from the falling edge of CS
and then updates and disables the device from accepting further data inputs. The TLC5618A is recommended for TMS320 and SPI processors, and the TLC5618 is recommended only for SPI or 3-wire serial port processors. The TLC5618A is backward-compatible and designed to work in TLC5618 designed systems.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corporation.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
1 2 3 4
8 7 6 5
DIN
SCLK
CS
OUT A
V
DD
OUT B REFIN AGND
D, P, OR JG PACKAGE
(TOP VIEW)
1920132
17
18
16 15 14
1312119 10
5
4
6 7 8
NC OUTB NC REFIN NC
NC
SCLK
NC CS NC
NC
DINNCV
NC
OUTA
NC
AGND
NC
NC
FK PACKAGE
(TOP VIEW)
DD
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
TLC5618, TLC5618A PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156E – JULY 1997 – REVISED SEPTEMBER 1999
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
description (continued)
The 8-terminal small-outline D package allows digital control of analog functions in space-critical applications. The TLC5618C is characterized for operation from 0°C to 70°C. The TLC5618I is characterized for operation from –40°C to 85°C. The TLC5618Q is characterized for operation from –40°C to 125°C. The TLC5618M is characterized for operation from –55°C to 125°C.
AVAILABLE OPTIONS
PACKAGE
T
A
SMALL OUTLINE
(D)
PLASTIC DIP
(P)
CERAMIC DIP
(JG)
20 PAD LCC
(FK)
0°C to 70°C
TLC5618CD TLC5618ACD
TLC5618CP TLC5618ACP
— —
— —
–40°C to 85°C
TLC5618ID TLC5618AID
TLC5618IP TLC5618AIP
— —
— –40°C to 125°C TLC5618AQD –55°C to 125°C TLC5618AMJG TLC5618AMFK
The D package is available in tape and reel by adding R to the part number (e.g., TLC5618CDR)
DEVICE
COMPATIBILITY
TLC5618 SPI, QSPI and Microwire TLC5618A TMS320Cxx, SPI, QSPI, and Microwire
TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156E – JULY 1997 – REVISED SEPTEMBER 1999
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
functional block diagram
_
+
DAC
12-Bit DAC Register Latch A
Power-Up
Reset
Control
Logic
16-Bit Shift Register
4
Program
Bits
12 Data Bits
(LSB) (MSB)
REFIN
AGND
CS
SCLK
DIN
OUT A (Voltage Output)
_ +
RR
DAC A
×2
Double
Buffer Latch
_ +
_
+
OUT B (Voltage Output)
DAC B
DAC
R
×2
R
12-Bit DAC Register Latch B
7
4
6
5
3 2 1
Terminal Functions
TERMINAL
NAME NO.
I/O
DESCRIPTION
AGND 5 Analog ground CS 3 I Chip select, active low DIN 1 I Serial data input OUT A 4 O DAC A analog output OUT B 7 O DAC B analog output REFIN 6 I Reference voltage input SCLK 2 I Serial clock input V
DD
8 Positive power supply
TLC5618, TLC5618A PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156E – JULY 1997 – REVISED SEPTEMBER 1999
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage (VDD to AGND) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital input voltage range to AGND – 0.3 V to VDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference input voltage range to AGND – 0.3 V to V
DD
+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage at OUT from external source V
DD
+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current at any terminal ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA: TLC5618C, TLC5618AC 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . .
TLC5618I, TLC5618AI –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . .
TLC5618AQ –40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TLC5618AM –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE
T
25°C DERATING FACTOR T
= 70°C T
= 85°C T
= 125°C
PACKAGE
A
POWER RATING ABOVE TA = 25°C
A
POWER RATINGAPOWER RATINGAPOWER RATING
D 635 mW 5.08 mW/°C 407 mW 330 mW — FK 1375 mW 11.00 mW/°C 880 mW 715 mW 275 mW JG 1050 mW 8.40 mW/°C 672 mW 546 mW 210 mW
P 1202 mW 9.61 mW/°C 769 mW 625 mW
This is the inverse of the traditional Junction-to-Ambient thermal Resistance (RΘJA). Thermal Resistances are not production tested and are for informational purposes only.
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, V
DD
4.5 5 5.5 V
High-level digital input voltage, V
IH
VDD = 5 V 0.7 V
DD
V
Low-level digital input voltage, V
IL
VDD = 5 V 0.3 V
DD
V
Reference voltage, V
ref
to REFIN terminal 2 2.048 VDD–1.1 V
Load resistance, R
L
2 k
TLC5618C, TLC5618AC 0 70
p
p
TLC5618I, TLC5618AI –40 85
°
Operating free-air temperature, T
A
TLC5618AQ –40 125
°C
TLC5618AM –55 125
TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156E – JULY 1997 – REVISED SEPTEMBER 1999
5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range, VDD = 5 V ±5%, V
ref(REFIN)
= 2.048 V (unless otherwise noted)
static DAC specifications
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution 12 bits Integral nonlinearity (INL), end point adjusted V
ref(REFIN)
= 2.048 V , See Note 1 ±4 LSB
Differential nonlinearity (DNL) V
ref(REFIN)
= 2.048 V , See Note 2 ±0.5 ± 1 LSB
E
ZS
Zero-scale error (offset error at zero scale) V
ref(REFIN)
= 2.048 V , See Note 3 ±12 mV
Zero-scale-error temperature coefficient V
ref(REFIN)
= 2.048 V , See Note 4 3 ppm/°C
E
G
Gain error V
ref(REFIN)
= 2.048 V , See Note 5 ±0.29
% of FS
voltage
Gain error temperature coefficient V
ref(REFIN)
= 2.048 V , See Note 6 1 ppm/°C
Zero scale
65
pp
Gain
Slo
w
65
PSRR
Power-su ly rejection ratio
Zero scale
See Notes 7 and 8
65
dB
Gain
Fast
65
NOTES: 1. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output
from the line between zero and full scale excluding the effects of zero code and full-scale errors.
2. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code.
3. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.
4. Zero-scale-error temperature coefficient is given by: EZSTC = [EZS(T
max
) – EZS(T
min
)]/V
ref
× 106/(T
max
– T
min
).
5. Gain error is the deviation from the ideal output (V
ref
– 1 LSB) with an output load of 10 kexcluding the effects of the zero-error.
6. Gain temperature coefficient is given by: EGTC = [EG(T
max
) – EG (T
min
)]/V
ref
× 106/(T
max
– T
min
).
7. Zero-scale-error rejection ratio (EZS-RR) is measured by varying the VDD from 4.5 V to 5.5 V dc and measuring the proportion of this signal imposed on the zero-code output voltage.
8. Gain-error rejection ratio (EG-RR) is measured by varying the VDD from 4.5 V to 5.5 V dc and measuring the proportion of this signal imposed on the full-scale output voltage after subtracting the zero scale change.
OUT A and OUT B output specifications
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
O
Voltage output range RL = 10 k 0 VDD–0.4 V Output load regulation accuracy V
O(OUT)
= 4.096 V , RL = 2 k ±0.29
% of FS
voltage
p
V
O(A OUT)
= VDD,
Fast 38
I
OSC(sink)
Out ut short circuit sink current
V
O(B OUT)
=
V
DD
,
Input code zero
Slow 23
mA
p
V
O(A OUT)
= 0 V,
Fast –54
I
OSC(
source
)
Out ut short circuit source current
V
O(B OUT)
= 0 V,
Full-scale code
Slow –29
mA
I
O(sink)
Output sink current V
O(OUT)
= 0.25 V 5 mA
I
O(source)
Output source current V
O(OUT)
= 4.2 V 5 mA
TLC5618, TLC5618A PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156E – JULY 1997 – REVISED SEPTEMBER 1999
6
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range, VDD = 5 V ±5%, V
ref(REFIN)
= 2.048 V (unless otherwise noted) (continued)
reference input (REFIN)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIInput voltage range 0 VDD–2 V RiInput resistance 10 M CiInput capacitance 5 pF
Reference feedthrough REFIN = 1 Vpp at 1 kHz + 1.024 V dc (see Note 9) –60 dB
p
Slow 0.5
Reference input bandwidth (f
– 3
dB)
REFIN
= 0.2
V
pp
+ 1.
024 V dc
Fast 1
MH
z
NOTE 9: Reference feedthrough is measured at the DAC output with an input code = 000 hex and a V
ref(REFIN)
input = 1.024 V dc + 1 V
pp
at 1 kHz.
digital inputs (DIN, SCLK, CS)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I
IH
High-level digital input current VI = V
DD
±1 µA
I
IL
Low-level digital input current VI = 0 V ±1 µA
C
i
Input capacitance 8 pF
power supply
PARAMETER TEST CONDITIONS MIN TYP MAX
UNIT
pp
VDD = 5.5 V,
Slow 0.6 1
IDDPower supply current
No load
,
All inputs = 0 V or V
DD
Fast 1.6 2.5
mA
Power down supply current D13 = 0 (see Table 2) 1 µA
operating characteristics over recommended operating free-air temperature range, VDD = 5 V ±5%, V
ref(REFIN)
= 2.048 V (unless otherwise noted)
analog output dynamic performance
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
p
p
CL = 100 pF,
V
ref(REFIN)
= 2.048 V ,
°
Slow 0.3 0.5
SR+Output slew rate, positive
R
L
= 10 k,
Code 32 to Code 4096,
T
A
=
25°C
,
VO from 10% to 90%
Fast
2.4 3
V/µs
p
CL = 100 pF,
V
ref(REFIN)
= 2.048 V ,
°
Slow 0.15 0.25
SR–Output slew rate, negative
R
L
= 10 k,
Code 4096 to Code 32,
T
A
=
25°C
,
VO from 10% to 90%
Fast
1.2 1.5
V/µs
p
To ±0.5 LSB,
CL = 100 pF,
Slow 12.5
tsOutput settling time
,
RL = 10 kΩ,
See Note 10
Fast
2.5
µ
s
Output settling time, To ±0.5 LSB,
CL = 100 pF,
Slow 2
t
s(c)
g,
code-to-code
,
RL = 10 kΩ,
See Note 11
Fast
2
µ
s
Glitch energy
DIN = All 0s to all 1s, f
(SCLK)
= 100 kHz
CS = VDD,
5 nV–s
S/(N+D) Signal to noise + distortion
V
ref(REFIN)
= 1 Vpp at 1 kHz and 10 kHz + 1.024 V dc,
Input code = 10 0000 0000
78 dB
NOTES: 10. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change
of 020 hex to 3FF hex or 3FF hex to 020 hex.
11. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change of one count.
TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156E – JULY 1997 – REVISED SEPTEMBER 1999
7
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
operating characteristics over recommended operating free-air temperature range, VDD = 5 V ±5%, V
ref(REFIN)
= 2.048 V (unless otherwise noted) (continued)
digital input timing requirements
MIN NOM MAX UNIT
t
su(DS)
Setup time, DIN before SCLK low 5 ns
t
h(DH)
Hold time, DIN valid after SCLK low 5 ns
t
su(CSS)
Setup time, CS low to SCLK low 5 ns
t
su(CS1)
Setup time, SCLK to CS , external end-of-write 10 ns
t
su(CS2)
Setup time, SCLK to CS , start of next write cycle 5 ns
t
w(CL)
Pulse duration, SCLK low 25 ns
t
w(CH)
Pulse duration, SCLK high 25 ns
t
d(CS1)
Delay time, CLK to data disable (TLC5618A only) 5 20 ns
NOTE A: The input clock, applied at the SCLK terminal, should be inhibited high when CS is high to minimize clock feedthrough.
t
su(CSS)
t
w(CL)
t
w(CH)
CS
SCLK
DIN
t
su(DS)
t
h(DH)
D15 D14 D13 D12 D11 D0
t
s
DAC A/B
OUT
Final Value ±0.5 LSB
(see Note A)
Program Bits (4)
DAC Data
Bits (12)
t
su(CS1)
t
su(CS2)
Figure 1. Timing Diagram for the TLC5618
TLC5618, TLC5618A PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS156E – JULY 1997 – REVISED SEPTEMBER 1999
8
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
NOTE A: The input clock, applied at the SCLK terminal, should be inhibited high when CS is high to minimize clock feedthrough.
t
su(CSS)
t
w(CL)
t
w(CH)
CS
SCLK
DIN
t
su(DS)
t
h(DH)
D15 D14 D13 D12 D11 D0
t
s
DAC A/B
OUT
Final Value ±0.5 LSB
(see Note A)
Program Bits (4)
DAC Data
Bits (12)
t
su(CS1)
t
su(CS2)
16th Falling Edge
t
d(CS1)
Internally Generated Disable at This Time
Internal
Latch
Control
(see Note A)
Figure 2. Timing Diagram for TLC5618A Only
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