Texas Instruments TL 16 C 2752 INSTALLATION INSTRUCTIONS

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1.8-V to 5-V DUAL UART WITH 64-BYTE FIFOS

TL16C2752

SLWS188 – JUNE 2006

FEATURES

• Larger FIFOs Reduce CPU Overhead

• Programmable Auto-RTS and Auto-CTS

• In Auto-CTS Mode, CTS Controls the

Transmitter

• In Auto-RTS Mode, RCV FIFO Contents, and

• Fully Programmable Serial Interface

Characteristics:
– 5-, 6-, 7-, or 8-Bit Characters
– Even-, Odd-, or No-Parity Bit Generation

and Detection

– 1-, 1 ½-, or 2-Stop Bit Generation

Threshold Control RTS – Baud Generation (dc to 1 Mbit/s)

• Serial and Modem Control Outputs Drive a • False-Start Bit Detection

RJ11 Cable Directly When Equipment is on
the Same Power Drop

• Capable of Running With All Existing

TL16C450 Software

• After Reset, All Registers Are Identical to the

TL16C450 Register Set

• Up to 48 MHz Clock Rate for up to 3-Mbps

(standard 16X sampling) Operation, or up to
6-Mbps (optional 8X sampling) Operation
With V

= 5 V Nominal

CC

• Up to 32 MHz Clock Rate for up to 2-Mbps

(standard 16X sampling) Operation, or up to
4-Mbps (optional 8X sampling) Operation
With V

= 3.3 V Nominal • Available in 44-Pin PLCC (FN) or 32-Pin QFN

CC

• Up to 24 MHz Clock Rate for up to 1.5-Mbps

• Complete Status Reporting Capabilities

• 3-State Output TTL Drive Capabilities for

Bidirectional Data Bus and Control Bus

• Line Break Generation and Detection

• Internal Diagnostic Capabilities:

– Loopback Controls for Communications

Link Fault Isolation

– Break, Parity, Overrun, and Framing Error

Simulation

• Fully Prioritized Interrupt System Controls

• Modem Control Functions ( CTS, RTS, DSR,

DTR, RI, and DCD)

(RHB) Packages

(standard 16X sampling) Operation, or up to • Each UART's Internal Register Set May Be
3-Mbps (optional 8X sampling) Operation Written Concurrently to Save Setup Time
With V

= 2.5 V Nominal

CC

• Multi-Function Output ( MF) Allows Users to

• Up to 16 MHz Clock Rate for up to 1-Mbps Select Among Several Functions, Saving

(standard 16X sampling) Operation, or up to Package Pins
2-Mbps (optional 8X sampling) Operation
With V

= 1.8 V Nominal

CC

• In the TL16C450 Mode, Hold and Shift

Registers Eliminate the Need for Precise
Synchronization Between the CPU and Serial
Data

• Programmable Baud Rate Generator Allows

Division of Any Input Reference Clock by 1 to

16

(2

- 1) and Generates an Internal 16 × Clock

APPLICATIONS

• Point-of-Sale Terminals

• Gaming Terminals

• Portable Applications

• Router Control

• Cellular Data

• Factory Automation

• Standard Asynchronous Communication Bits

(Start, Stop, and Parity) Added to or Deleted
From the Serial Data Stream

• 5-V, 3.3-V, 2.5-V, and 1.8 V Operation

• Independent Receiver Clock Input

• Transmit, Receive, Line Status, and Data Set

Interrupts Independently Controlled

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.

Copyright © 2006, Texas Instruments Incorporated

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PRODUCT PREVIEW

RXA

MFA

D5
D6

RIB

DSRB

CDB

TXRDYB

V

CC

INTA

RTSA

DTRA

TXA

39

35

31

29

30

32

33

34

36

37

38

246 1 42 4041434435

7
8

9
10
11
12
13
14
15
16
17

1918 26 2820 21 22 23 24 25 27

A0

XTAL1

GND

XTAL2

A1
A2

CHSEL

INTB

D7

IOW

CS

MFB

RESET

GND

RTSB

IOR

RXB

TXB

DTRB

CTSB

D4

D0

CDA

CTSA

DSRA

RIA

V

CC

TXRDYA

D1

D2

D3

TL16C2752FN

FN PACKAGE

(TOP VIEW)

TL16C2752

SLWS188 – JUNE 2006

DESCRIPTION

The TL16C2752 is a speed and functional upgrade
of the TL16C2552. Since they are pinout and
software compatible, designs can easily migrate from
the TL16C2552 to the TL16C2752 if needed. The
additional functionality within the TL16C2752 is
accessed via an extended register set. Some of the
key new features are larger receive and transmit
fifos, embedded IrDA encoders and decoders,
RS-485 transceiver controls, software flow control
(Xon/Xoff) modes, programmable transmit fifo
thresholds, extended receive and transmit threshold
levels for interrupts, and extended receive threshold
levels for flow control halt/resume operation.

The TL16C2752 is a dual universal asynchronous
receiver and transmitter (UART). It incorporates the
functionality of two independent UARTs, each UART
having its own register set and transmit and receive
FIFOs. The two UARTs share only the data bus
interface and clock source, otherwise they operate
independently. Another name for the UART function
is Asynchronous Communications Element (ACE),
and these terms will be used interchangeably. The
bulk of this document describes the behavior of each
ACE, with the understanding that two such devices
are incorporated into the TL16C2752.

Functionally equivalent to the TL16C450 on power
up or reset (single character or TL16C450 mode),
each ACE can be placed in an alternate FIFO mode.
This relieves the CPU of excessive software
overhead by buffering received and to be transmitted
characters. Each receiver and transmitter store up to
64 bytes in their respective FIFOs, with the receive
FIFO including three additional bits per byte for error
status. In the FIFO mode, selectable hardware or
software autoflow control features can significantly
reduce program overload and increase system
efficiency by automatically controlling serial data
flow.

Each ACE performs serial-to-parallel conversions on
data received from a peripheral device or modem
and stores the parallel data in its receive buffer or
FIFO, and each ACE performs parallel-to-serial
conversions on data sent from its CPU after storing
the parallel data in its transmit buffer or FIFO. The
CPU can read the status of either ACE at any time.
Each ACE includes complete modem control
capability and a processor interrupt system that can
be tailored to the application.

2

Each ACE includes a programmable baud rate
generator capable of dividing a reference clock with
divisors of from 1 to 65535, thus producing a 16× or
8× internal reference clock for the transmitter and
receiver logic. Each ACE accommodates up to a
3-Mbaud serial data rate (48-MHz input clock). As a
reference point, that speed would generate a 333-ns
bit time and a 3.33-µs character time (for 8,N,1 serial
data), with the internal clock running at 48 MHz and
16× sampling.

Each ACE has a TXRDY and RXRDY (via MF)
output that can be used to interface to a DMA
controller.

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INTB

CS

IOW

RESET

RTSB

IOR

RXB

TXB

1
2
3
4
5
6
7
8

9

10

11

12

13

14

15

16

24
23
22
21
20
19
18
17

D6
D7

A0
XTAL1
XTAL2

A1

A2

CHSEL

RXA
TXA
RTSA
INTA
GND
NC
NC
CTSB

32

31

30

29

28

27

26

25

D5D4D3D2D1D0V

CC

CTSA

RHB PACKAGE

(TOP VIEW)

NC − No internal connection
NOTE: The 32-pin RHB package does not provide access to DSRA

,
DSRB, RIA, RIB, CDA, CDB inputs and MFA, MFB, DTRA , DTRB,
TXRDYA

, TXRDYB outputs.

TL16C2752RHB

TL16C2752

SLWS188 – JUNE 2006

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PRODUCT PREVIEW

Crystal

OSC

Buffer

Data Bus

Interface

A2 − A0
D7 − D0

CS

CHSEL

IOR

IOW

INTA
INTB

TXRDYA
TXRDYB

MFA
MFB

RESET

XTAL1
XTAL2

BAUD

Rate

Gen

64 Byte Tx FIFO

64 Byte Rx FIFO

Tx

IR ENC

UART Channel A

BAUD

Rate

Gen

64 Byte Tx FIFO

64 Byte Rx FIFO

UART Channel B

CTSA
DTRA
DSRA, RIA, CDA
RTSA

CTSB
DTRB
DSRB, RIB, CDB
RTSB

V

CC

GND

TXA

RXA

TXB

RXB

UART Regs

UART Regs

Rx

IR DEC

Tx

IR ENC

Rx

IR DEC

TL16C2752

SLWS188 – JUNE 2006

TL16C2752 Block Diagram

A. MF output allows selection of OP, BAUDOUT, or RXRDY per channel.

TERMINAL

NAME FN NO. RHB NO.

A0 10 3 I Address 0 select bit. Internal registers address selection
A1 14 6 I Address 1 select bit. Internal registers address selection
A2 15 7 I Address 2 select bit. Internal registers address selection

CDA, CDB 42, 30 – I

CHSEL 16 8 I

CS 18 10 I

CTSA, data from the 2552. Status can be tested by reading MSR bit 4. These pins only affect the
CTSB transmit and receive operations when auto CTS function is enabled through the enhanced

40, 28 25, 17 I

DEVICE INFORMATION

TERMINAL FUNCTIONS

I/O DESCRIPTION

Carrier detect (active low). These inputs are associated with individual UART channels A and
B. A low on these pins indicates that a carrier has been detected by the modem for that
channel. The state of these inputs is reflected in the modem status register (MSR). These
inputs should be pulled high if unused.

Channel select. UART channel A or B is selected by the state of this pin when CS is a logic 0.
A logic 0 on the CHSEL selects the UART channel B while a logic 1 selects UART channel A.
CHSEL could just be an address line from the user CPU such as A3. Bit 0 of the alternate
function register (AFR) can temporarily override CHSEL function, allowing the user to write to
both channel register simultaneously with one write cycle when CS is low. It is especially
useful during the initialization routine.

UART chip select (active low). This pin selects channel A or B in accordance with the state of
the CHSEL pin. This allows data to be transferred between the user CPU and the 2552.

Clear to send (active low). These inputs are associated with individual UART channels A and
B. A logic low on the CTS pins indicates the modem or data set is ready to accept transmit

feature register (EFR) bit 7, for hardware flow control operation. These inputs should be
pulled high if unused.

4

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TL16C2752

SLWS188 – JUNE 2006

DEVICE INFORMATION (continued)

TERMINAL FUNCTIONS (continued)

TERMINAL

NAME FN NO. RHB NO.

D0-D4 2 - 6 27 - 31 Data bus (bidirectional). These pins are the eight bit, 3-state data bus for transferring
D5-D7 7 - 9 32, 1, 2

DSRA, and B. A logic low on these pins indicates the modem or data set is powered on and is ready
DSRB for data exchange with the UART. The state of these inputs is reflected in the modem status

DTRA,
DTRB

GND 12, 22 20 Signal and power ground.

INTA, INTB 34, 17 21, 9 O the interrupt enable register (IER). Interrupt conditions include: receiver errors, available

IOR 24 14 I internal register defined by address bits A0-A2 onto the TL16C2552 data bus (D0-D7) for

IOW 20 11 I data bus (D0-D7) from the external CPU to an internal register that is defined by address bits

NC – 18, 19 No internal connection

MFA, MFB 35, 19 – O

RESET 21 12 I output and the receiver input will be disabled during reset time. See TL16C2552 external

RIA, RIB 43, 31 – I telephone line. A low to high transition on these input pins generates a modem status

RTSA, Writing a 1 in the modem control register (MCR bit 1) sets these pins to low, indicating data is
RTSB available. After a reset, these pins are set to high. These pins only affects the transmit and

RXA, RXB 39, 25 24, 15 I 2552. During the local loopback mode, these RX input pins are disabled and TX data is

TXA, TXB 38, 26 23, 16 O the 2552. During the local loopback mode, the TX input pin is disabled and TX data is

TXRDYA, Transmit ready (active low). TXRDY A and B go low when there are at least a trigger level
TXRDYB numbers of spaces available. They go high when the TX buffer is full.

41, 29 – I

37, 27 – O These pins can be controlled through the modem control register. Writing a 1 to MCR bit 0

36, 23 22, 13 O

1, 32 – O

I/O DESCRIPTION

I/O information to or from the controlling CPU. D0 is the least significant bit and the first data bit in

a transmit or receive serial data stream.
Data set ready (active low). These inputs are associated with individual UART channels A

register (MSR). These inputs should be pulled high if unused.
Data terminal ready (active low). These outputs are associated with individual UART channels

A and B. A logic low on these pins indicates that theTLl16C2552 is powered on and ready.
sets the DTR output to low, enabling the modem. The output of these pins is high after writing

a 0 to MCR bit 0, or after a reset.

Interrupt A and B (active high). These pins provide individual channel interrupts, INT A and B.
INT A and B are enabled when MCR bit 3 is set to a logic 1, interrupt sources are enabled in

receiver buffer data, available transmit buffer space or when a modem status flag is detected.
INTA-B are in the high-impedance state after reset.

Read input (active low strobe). A high to low transition on IOR will load the contents of an
access by an external CPU.

Write input (active low strobe). A low to high transition on IOW will transfer the contents of the
A0-A2 and CSA and CSB

Multi-function output. This output pin can function as the OP, BAUDOUT, or RXRDY pin. One
of these output signal functions can be selected by the user programmable bits 1-2 of the
alternate function register (AFR). These signal functions are described as follows:

1. OP - When OP (active low) is selected, the MF pin is a logic 0 when MCR bit 3 is set to
a logic 1 (see MCR bit 3). MCR bit 3 defaults to a logic 1 condition after a reset or
power-up.

2. BAUDOUT - When BAUDOUT function is selected, the 16× baud rate clock output is
available at this pin.

3. RXRDY - RXRDY (active low) is intended for monitoring DMA data transfers.
If it is not used, leave it unconnected.

Reset. RESET will reset the internal registers and all the outputs. The UART transmitter
reset conditions for initialization details. RESET is an active-high input.

Ring indicator (active low). These inputs are associated with individual UART channels A and
B. A logic low on these pins indicates the modem has received a ringing signal from the

interrupt, if enabled. The state of these inputs is reflected in the modem status register (MSR).
These inputs should be pulled high if unused.

Request to send (active low). These outputs are associated with individual UART channels A
and B. A low on the RTS pin indicates the transmitter has data ready and waiting to send.

receive operation when auto RTS function is enabled through the enhanced feature register
(EFR) bit 6, for hardware flow control operation.

Receive data input. These inputs are associated with individual serial channel data to the
internally connected to the UART RX input internally.

Transmit data. These outputs are associated with individual serial transmit channel data from
internally connected to the UART RX input.

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PRODUCT PREVIEW

RCV
FIFO

Serial to

Parallel

Flow

Control

XMT

FIFO

Parallel

to Serial

Flow

Control

Parallel

to Serial

Flow

Control

Serial to

Parallel

Flow

Control

XMT

FIFO

RCV
FIFO

ACE1 ACE2

D7−D0

RX TX

RTS CTS

TX RX

CTS RTS

D7−D0

TL16C2752

SLWS188 – JUNE 2006

DEVICE INFORMATION (continued)

TERMINAL FUNCTIONS (continued)

TERMINAL

NAME FN NO. RHB NO.

V

CC

XTAL1 11 4 I

XTAL2 13 5 O

33, 44 26 I Power supply inputs.

Detailed Description

Hardware Autoflow Control (see Figure 1 )

Hardware Autoflow control is comprised of auto- CTS and auto- RTS. With auto- CTS, the CTS input must be
active before the transmitter FIFO can emit data. With auto- RTS, RTS becomes active when the receiver needs
more data and notifies the sending serial device. When RTS is connected to CTS, data transmission does not
occur unless the receiver FIFO has space for the data; thus, overrun errors are eliminated using ACE1 and
ACE2 from a TLC16C2752 with the autoflow control enabled. If not, overrun errors can occur when the transmit
data rate exceeds the receiver FIFO read latency.

I/O DESCRIPTION

Crystal or external clock input. XTAL1 functions as a crystal input or as an external clock
input. A crystal can be connected between XTAL1 and XTAL2 to form an internal oscillator
circuit (see Figure 4 ). Alternatively, an external clock can be connected to XTAL1 to provide
custom data rates.

Output of the crystal oscillator or buffered clock. See also XTAL1. XTAL2 is used as a crystal
oscillator output or buffered a clock output.

Figure 1. Autoflow Control (Auto- RTS and Auto- CTS) Example

Auto- RTS (See Figure 2 and Figure 3 )

Auto- RTS data flow control originates in the receiver timing and control block (see functional block diagram) and
is linked to the programmed receiver FIFO trigger level. When the receiver FIFO level reaches the defined halt
trigger level 8 (see Figure 3 ), RTS is deasserted. The sending ACE may send an additional byte after the trigger
level is reached (assuming the sending ACE has another byte to send) because it may not recognize the
deassertion of RTS until after it has begun sending the additional byte. RTS is automatically reasserted once the
defined resume trigger level is reached.

Auto- CTS (See Figure 2 )

The transmitter circuitry checks CTS before sending the next data byte. When CTS is active, it sends the next
byte. To stop the transmitter from sending the following byte, CTS must be released before the middle of the last
stop bit that is currently being sent (see Figure 2 ). The auto- CTS function reduces interrupts to the host system.
When flow control is enabled, CTS level changes do not trigger host interrupts because the device automatically
controls its own transmitter. Without auto- CTS, the transmitter sends any data present in the transmit FIFO and
a receiver overrun error may result.

6

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Auto- CTS and Auto- RTS Functional Timing

Start Bits 0−7 Start Bits 0−7 Start Bits 0−7

Stop Stop Stop

SOUT

CTS

Start Byte N Start Byte N+1 Start Byte

Stop Stop Stop

SIN

RTS

RD

(RD RBR)

1 2

N N+1

Figure 2. CTS Functional Timing Waveforms

Figure 3. RTS Functional Timing Waveforms

TL16C2752

SLWS188 – JUNE 2006

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PRODUCT PREVIEW

Receiver

Buffer

Register

Divisor

Latch (LS)

Divisor

Latch (MS)

Baud

Generator

Receiver

FIFO

Line

Status

Register

Transmitter

Holding

Register

Modem

Control

Register

Modem

Status

Register

Line

Control

Register

Transmitter

FIFO

Interrupt

Enable

Register

Interrupt

Identification

Register

FIFO

Control

Register

Select

and

Control

Logic

Interrupt

Control

Logic

S
e

l
e
c

t

Data

Bus

Buffer

RXA, B

TXA, B

CTSA, B
DTRA, B
DSRA, b
CDA,B
RIA, B

INTA, B

40, 28
37, 27
41, 29
42, 30
43, 31

34, 17

38, 26

39, 25

A0

10

D(7−0)

9−2

Internal
Data Bus

14
15

18
16

13

21
24

20

11

1
35

A1
A2

CS

CHSEL

XTAL2

RESET

IOR

IOW

XTAL1

TXRDYA

MFA

S
e

l
e
c

t

Receiver

Shift

Register

IrDA Decoder

Receiver

Timing and

Control

Transmitter

Timing and

Control

Modem

Control

Logic

8

33, 44
12, 22

V

CC

GND

Power
Supply

RTSA, B

36, 23

Autoflow
Control
(AFE)

8

8

8

8

8

8

8

32
19

TXRDYB

MFB

Crystal

OSC

Buffer

Transmitter

Shift

Register

IrDA Encoder

TL16C2752

SLWS188 – JUNE 2006

A. Pin numbers shown are for 44-pin PLCC FN package.

8

Figure 4. Functional Block Diagram

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