Texas Instruments TL 16 C 2552 INSTALLATION INSTRUCTIONS

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1.8-V to 5-V DUAL UART WITH 16-BYTE FIFOS

TL16C2552

SLWS163A – SEPTEMBER 2005 – REVISED JUNE 2006

FEATURES

• False-Start Bit Detection

• Programmable Auto-RTS and Auto-CTS • Complete Status Reporting Capabilities

• In Auto-CTS Mode, CTS Controls the • 3-State Output TTL Drive Capabilities for

Transmitter Bidirectional Data Bus and Control Bus

• In Auto-RTS Mode, RCV FIFO Contents, and • Line Break Generation and Detection

Threshold Control RTS

• Serial and Modem Control Outputs Drive a

RJ11 Cable Directly When Equipment is on
the Same Power Drop

• Capable of Running With All Existing

TL16C450 Software

• After Reset, All Registers Are Identical to the

TL16C450 Register Set

• Up to 24-MHz Clock Rate for up to 1.5-Mbaud

Operation With V

= 5 V

CC

• Up to 20-MHz Clock Rate for up to

1.25-Mbaud Operation With V

= 3.3 V

CC

• Up to 16-MHz Clock Rate for up to 1-Mbaud

Operation With V

= 2.5 V

CC

• Up to 10-MHz Clock Rate for up to 625-kbaud

Operation With V

= 1.8 V

CC

• In the TL16C450 Mode, Hold and Shift

Registers Eliminate the Need for Precise
Synchronization Between the CPU and Serial
Data

• Programmable Baud Rate Generator Allows

Division of Any Input Reference Clock by 1 to

16

(2

- 1) and Generates an Internal 16 × Clock

• Internal Diagnostic Capabilities:

– Loopback Controls for Communications

Link Fault Isolation

– Break, Parity, Overrun, and Framing Error

Simulation

• Fully Prioritized Interrupt System Controls

• Modem Control Functions ( CTS, RTS, DSR,

DTR, RI, and DCD)

• Available in 44-Pin PLCC (FN) or 32-Pin QFN

(RHB) Packages

• Each UART's Internal Register Set May Be

Written Concurrently to Save Setup Time

• Multi-Function Output ( MF) Allows Users to

Select Among Several Functions, Saving
Package Pins

APPLICATIONS

• Point-of-Sale Terminals

• Gaming Terminals

• Portable Applications

• Router Control

• Cellular Data

• Factory Automation

• Standard Asynchronous Communication Bits

(Start, Stop, and Parity) Added to or Deleted

DESCRIPTION

From the Serial Data Stream

• 5-V, 3.3-V, 2.5-V, and 1.8 V Operation

• Independent Receiver Clock Input

• Transmit, Receive, Line Status, and Data Set

Interrupts Independently Controlled

• Fully Programmable Serial Interface

Characteristics:
– 5-, 6-, 7-, or 8-Bit Characters
– Even-, Odd-, or No-Parity Bit Generation

and Detection

– 1-, 1 ½-, or 2-Stop Bit Generation

The TL16C2552 is a dual universal asynchronous
receiver and transmitter (UART). It incorporates the
functionality of two TL16C550D UARTs, each UART
having its own register set and FIFOs. The two
UARTs share only the data bus interface and clock
source, otherwise they operate independently.
Another name for the UART function is
Asynchronous Communications Element (ACE), and
these terms will be used interchangeably. The bulk
of this document describes the behavior of each
ACE, with the understanding that two such devices
are incorporated into the TL16C2552.

– Baud Generation (dc to 1 Mbit/s)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Copyright © 2005–2006, Texas Instruments Incorporated

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RXA

MFA

D5
D6

RIB

DSRB

CDB

TXRDYB

V

CC

INTA

RTSA

DTRA

TXA

39

35

31

29

30

32

33

34

36

37

38

246 1 42 4041434435

7
8

9
10
11
12
13
14
15
16
17

1918 26 2820 21 22 23 24 25 27

A0

XTAL1

GND

XTAL2

A1
A2

CHSEL

INTB

D7

IOW

CS

MFB

RESET

GND

RTSB

IOR

RXB

TXB

DTRB

CTSB

D4

D0

CDA

CTSA

DSRA

RIA

V

CC

TXRDYA

D1

D2

D3

TL16C2552FN

FN PACKAGE

(TOP VIEW)

INTB

CS

IOW

RESET

RTSB

IOR

RXB

TXB

1
2
3
4
5
6
7
8

9

10

11

12

13

14

15

16

24
23
22
21
20
19
18
17

D6
D7

A0
XTAL1
XTAL2

A1

A2

CHSEL

RXA
TXA
RTSA
INTA
GND
NC
NC
CTSB

32

31

30

29

28

27

26

25

D5D4D3D2D1D0V

CC

CTSA

RHB PACKAGE

(TOP VIEW)

NC − No internal connection
NOTE: The 32-pin RHB package does not provide access to DSRA

,
DSRB, RIA, RIB, CDA, CDB inputs and MFA, MFB, DTRA , DTRB,
TXRDYA

, TXRDYB outputs.

TL16C2552RHB

TL16C2552

SLWS163A – SEPTEMBER 2005 – REVISED JUNE 2006

Each ACE is a speed and voltage range upgrade of
the TL16C550C, which in turn is a functional
upgrade of the TL16C450. Functionally equivalent to
the TL16C450 on power up or reset (single character
or TL16C450 mode), each ACE can be placed in an
alternate FIFO mode. This relieves the CPU of
excessive software overhead by buffering received
and to be transmitted characters. Each receiver and
transmitter store up to 16 bytes in their respective
FIFOs, with the receive FIFO including three
additional bits per byte for error status. In the FIFO
mode, a selectable autoflow control feature can
significantly reduce software overload and increase
system efficiency by automatically controlling serial
data flow using handshakes between the RTS output
and CTS input, thus eliminating overruns in the
receive FIFO.

Each ACE performs serial-to-parallel conversions on
data received from a peripheral device or modem
and stores the parallel data in its receive buffer or
FIFO, and each ACE performs parallel-to-serial
conversions on data sent from its CPU after storing
the parallel data in its transmit buffer or FIFO. The
CPU can read the status of either ACE at any time.
Each ACE includes complete modem control
capability and a processor interrupt system that can
be tailored to the application.

Each ACE includes a programmable baud rate
generator capable of dividing a reference clock with
divisors of from 1 to 65535, thus producing a 16×
internal reference clock for the transmitter and
receiver logic. Each ACE accommodates up to a

1.5-Mbaud serial data rate (24-MHz input clock). As
a reference point, that speed would generate a
667-ns bit time and a 6.7-µs character time (for 8,N,1
serial data), with the internal clock running at 24
MHz.

Each ACE has a TXRDY and RXRDY output that
can be used to interface to a DMA controller.

2

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TL16C2552 Block Diagram

Crystal

OSC

Buffer

Data Bus

Interface

A2 − A0
D7 − D0

CS

CHSEL

IOR

IOW

INTA
INTB

TXRDYA
TXRDYB

MFA
MFB

RESET

XTAL1
XTAL2

BAUD

Rate

Gen

16 Byte Tx FIFO

16 Byte Rx FIFO

Tx

Rx

UART Channel A

BAUD

Rate

Gen

16 Byte Tx FIFO

16 Byte Rx FIFO

Tx

Rx

UART Channel B

CTSA
DTRA
DSRA, RIA, CDA
RTSA

CTSB
DTRB
DSRB, RIB, CDB
RTSB

V

CC

GND

TXA

RXA

TXB

RXB

UART Regs

UART Regs

TL16C2552

SLWS163A – SEPTEMBER 2005 – REVISED JUNE 2006

A. MF output allows selection of OP, BAUDOUT, or RXRDY per channel.

DEVICE INFORMATION

TERMINAL FUNCTIONS

TERMINAL

NAME FN NO. RHB NO.

A0 10 3 I Address 0 select bit. Internal registers address selection
A1 14 6 I Address 1 select bit. Internal registers address selection
A2 15 7 I Address 2 select bit. Internal registers address selection

CDA, CDB 42, 30 – I B. A low on these pins indicates that a carrier has been detected by the modem for that

CHSEL 16 8 I

CS 18 10 I

CTSA,
CTSB

40, 28 25, 17 I data from the 2552. Status can be tested by reading MSR bit 4. These pins only affect the

I/O DESCRIPTION

Carrier detect (active low). These inputs are associated with individual UART channels A and
channel. The state of these inputs is reflected in the modem status register (MSR).

Channel select. UART channel A or B is selected by the state of this pin when CS is a logic 0.
A logic 0 on the CHSEL selects the UART channel B while a logic 1 selects UART channel A.
CHSEL could just be an address line from the user CPU such as A3. Bit 0 of the alternate
function register (AFR) can temporarily override CHSEL function, allowing the user to write to
both channel register simultaneously with one write cycle when CS is low. It is especially
useful during the initialization routine.

UART chip select (active low). This pin selects channel A or B in accordance with the state of
the CHSEL pin. This allows data to be transferred between the user CPU and the 2552.

Clear to send (active low). These inputs are associated with individual UART channels A and
B. A logic low on the CTS pins indicates the modem or data set is ready to accept transmit

transmit and receive operations when auto CTS function is enabled through the enhanced
feature register (EFR) bit 7, for hardware flow control operation.

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TL16C2552

SLWS163A – SEPTEMBER 2005 – REVISED JUNE 2006

DEVICE INFORMATION (continued)

TERMINAL FUNCTIONS (continued)

TERMINAL

NAME FN NO. RHB NO.

D0-D4 2 - 6 27 - 31 Data bus (bidirectional). These pins are the eight bit, 3-state data bus for transferring
D5-D7 7 - 9 32, 1, 2

DSRA, and B. A logic low on these pins indicates the modem or data set is powered on and is ready
DSRB for data exchange with the UART. The state of these inputs is reflected in the modem status

DTRA,
DTRB

GND 12, 22 20 Signal and power ground.

INTA, INTB 34, 17 21, 9 O the interrupt enable register (IER). Interrupt conditions include: receiver errors, available

IOR 24 14 I internal register defined by address bits A0-A2 onto the TL16C2552 data bus (D0-D7) for

IOW 20 11 I data bus (D0-D7) from the external CPU to an internal register that is defined by address bits

NC – 18, 19 No internal connection

MFA, MFB 35, 19 – O

RESET 21 12 I output and the receiver input will be disabled during reset time. See TL16C2552 external

RIA, RIB 43, 31 – I

RTSA, Writing a 1 in the modem control register (MCR bit 1) sets these pins to low, indicating data is
RTSB available. After a reset, these pins are set to high. These pins only affects the transmit and

RXA, RXB 39, 25 24, 15 I 2552. During the local loopback mode, these RX input pins are disabled and TX data is

TXA, TXB 38, 26 23, 16 O the 2552. During the local loopback mode, the TX input pin is disabled and TX data is

TXRDYA, Transmit ready (active low). TXRDY A and B go low when there are at least a trigger level
TXRDYB numbers of spaces available. They go high when the TX buffer is full.

V

CC

41, 29 – I

37, 27 – O These pins can be controlled through the modem control register. Writing a 1 to MCR bit 0

36, 23 22, 13 O

1, 32 – O

33, 44 26 I Power supply inputs.

I/O DESCRIPTION

I/O information to or from the controlling CPU. D0 is the least significant bit and the first data bit in

a transmit or receive serial data stream.
Data set ready (active low). These inputs are associated with individual UART channels A

register (MSR).
Data terminal ready (active low). These outputs are associated with individual UART channels

A and B. A logic low on these pins indicates that theTLl16C2552 is powered on and ready.
sets the DTR output to low, enabling the modem. The output of these pins is high after writing

a 0 to MCR bit 0, or after a reset.

Interrupt A and B (active high). These pins provide individual channel interrupts, INT A and B.
INT A and B are enabled when MCR bit 3 is set to a logic 1, interrupt sources are enabled in

receiver buffer data, available transmit buffer space or when a modem status flag is detected.
INTA-B are in the high-impedance state after reset.

Read input (active low strobe). A high to low transition on IOR will load the contents of an
access by an external CPU.

Write input (active low strobe). A low to high transition on IOW will transfer the contents of the
A0-A2 and CSA and CSB

Multi-function output. This output pin can function as the OP, BAUDOUT, or RXRDY pin. One
of these output signal functions can be selected by the user programmable bits 1-2 of the
alternate function register (AFR). These signal functions are described as follows:

1. OP - When OP (active low) is selected, the MF pin is a logic 0 when MCR bit 3 is set to
a logic 1 (see MCR bit 3). MCR bit 3 defaults to a logic 1 condition after a reset or
power-up.

2. BAUDOUT - When BAUDOUT function is selected, the 16× baud rate clock output is
available at this pin.

3. RXRDY - RXRDY (active low) is intended for monitoring DMA data transfers.
If it is not used, leave it unconnected.

Reset. RESET will reset the internal registers and all the outputs. The UART transmitter
reset conditions for initialization details. RESET is an active-high input.

Ring indicator (active low). These inputs are associated with individual UART channels A and
B. A logic low on these pins indicates the modem has received a ringing signal from the
telephone line. A low to high transition on these input pins generates a modem status
interrupt, if enabled. The state of these inputs is reflected in the modem status register (MSR)

Request to send (active low). These outputs are associated with individual UART channels A
and B. A low on the RTS pin indicates the transmitter has data ready and waiting to send.

receive operation when auto RTS function is enabled through the enhanced feature register
(EFR) bit 6, for hardware flow control operation.

Receive data input. These inputs are associated with individual serial channel data to the
internally connected to the UART RX input internally.

Transmit data. These outputs are associated with individual serial transmit channel data from
internally connected to the UART RX input.

4

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RCV
FIFO

Serial to

Parallel

Flow

Control

XMT

FIFO

Parallel

to Serial

Flow

Control

Parallel

to Serial

Flow

Control

Serial to

Parallel

Flow

Control

XMT

FIFO

RCV
FIFO

ACE1 ACE2

D7−D0

RX TX

RTS CTS

TX RX

CTS RTS

D7−D0

TL16C2552

SLWS163A – SEPTEMBER 2005 – REVISED JUNE 2006

DEVICE INFORMATION (continued)

TERMINAL FUNCTIONS (continued)

TERMINAL

NAME FN NO. RHB NO.

XTAL1 11 4 I

XTAL2 13 5 O

Detailed Description

Autoflow Control (see Figure 1 )

Autoflow control is comprised of auto- CTS and auto- RTS. With auto- CTS, the CTS input must be active before
the transmitter FIFO can emit data. With auto- RTS, RTS becomes active when the receiver needs more data
and notifies the sending serial device. When RTS is connected to CTS, data transmission does not occur unless
the receiver FIFO has space for the data; thus, overrun errors are eliminated using ACE1 and ACE2 from a
TLC16C2552 with the autoflow control enabled. If not, overrun errors occur when the transmit data rate exceeds
the receiver FIFO read latency.

I/O DESCRIPTION

Crystal or external clock input. XTAL1 functions as a crystal input or as an external clock
input. A crystal can be connected between XTAL1 and XTAL2 to form an internal oscillator
circuit (see Figure 5 ). Alternatively, an external clock can be connected to XTAL1 to provide
custom data rates.

Output of the crystal oscillator or buffered clock. See also XTAL1. XTAL2 is used as a crystal
oscillator output or buffered a clock output.

Figure 1. Autoflow Control (Auto- RTS and Auto- CTS) Example

Auto- RTS (See Figure 2 and Figure 3 )

Auto- RTS data flow control originates in the receiver timing and control block (see functional block diagram) and
is linked to the programmed receiver FIFO trigger level. When the receiver FIFO level reaches a trigger level of
1, 4, or 8 (see Figure 3 ), RTS is deasserted. With trigger levels of 1, 4, and 8, the sending ACE may send an
additional byte after the trigger level is reached (assuming the sending ACE has another byte to send) because
it may not recognize the deassertion of RTS until after it has begun sending the additional byte. RTS is
automatically reasserted once the RCV FIFO is emptied by reading the receiver buffer register.

When the trigger level is 14 (see Figure 5 ), RTS is deasserted after the first data bit of the 16th character is
present on the RX line. RTS is reasserted when the RCV FIFO has at least one available byte space.

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Start Bits 0−7 Start Bits 0−7 Start Bits 0−7

Stop Stop Stop

SOUT

CTS

Start Byte N Start Byte N+1 Start Byte

Stop Stop Stop

SIN

RTS

RD

(RD RBR)

1 2

N N+1

Byte 14 Byte 15

SIN

RTS

RD

(RD RBR)

Start Byte 18 StopStart Byte 16 Stop

RTS Released After the

First Data Bit of Byte 16

TL16C2552

SLWS163A – SEPTEMBER 2005 – REVISED JUNE 2006

Auto- CTS (See Figure 2 )

The transmitter circuitry checks CTS before sending the next data byte. When CTS is active, it sends the next
byte. To stop the transmitter from sending the following byte, CTS must be released before the middle of the last
stop bit that is currently being sent (see Figure 2 ). The auto- CTS function reduces interrupts to the host system.
When flow control is enabled, CTS level changes do not trigger host interrupts because the device automatically
controls its own transmitter. Without auto- CTS, the transmitter sends any data present in the transmit FIFO and
a receiver overrun error may result.

Enabling Autoflow Control and Auto- CTS

Autoflow control is enabled by setting modem control register bits 5 (autoflow enable or AFE) and 1 ( RTS) to a

1. Autoflow incorporates both auto- RTS and auto- CTS. When only auto- CTS is desired, bit 1 in the modem
control register should be cleared (this assumes that a control signal is driving CTS).

Auto- CTS and Auto- RTS Functional Timing

Figure 2. CTS Functional Timing Waveforms

Figure 3. RTS Functional Timing Waveforms, RCV FIFO Trigger Level = 1, 4, or 8 Bytes

Figure 4. RTS Functional Timing Waveforms, RCV FIFO Trigger Level = 14 Bytes

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Receiver

Buffer

Register

Divisor

Latch (LS)

Divisor

Latch (MS)

Baud

Generator

Receiver

FIFO

Line

Status

Register

Transmitter

Holding

Register

Modem

Control

Register

Modem

Status

Register

Line

Control

Register

Transmitter

FIFO

Interrupt

Enable

Register

Interrupt

Identification

Register

FIFO

Control

Register

Select

and

Control

Logic

Interrupt

Control

Logic

S
e

l
e
c

t

Data

Bus

Buffer

RXA, B

TXA, B

CTSA, B
DTRA, B
DSRA, b
CDA,B
RIA, B

INTA, B

40, 28
37, 27
41, 29
42, 30
43, 31

34, 17

38, 26

39, 25

A0

10

D(7−0)

9−2

Internal
Data Bus

14
15

18
16

13

21
24

20

11

1
35

A1
A2

CS

CHSEL

XTAL2

RESET

IOR

IOW

XTAL1

TXRDYA

MFA

S
e

l
e
c

t

Receiver

Shift

Register

Receiver

Timing and

Control

Transmitter

Timing and

Control

Transmitter

Shift

Register

Modem

Control

Logic

8

33, 44
12, 22

V

CC

GND

Power
Supply

RTSA, B

36, 23

Autoflow
Control
(AFE)

8

8

8

8

8

8

8

32
19

TXRDYB

MFB

Crystal

OSC

Buffer

TL16C2552

SLWS163A – SEPTEMBER 2005 – REVISED JUNE 2006

A. Pin numbers shown are for 44-pin PLCC FN package.

Figure 5. Functional Block Diagram

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TL16C2552

SLWS163A – SEPTEMBER 2005 – REVISED JUNE 2006

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V
Input voltage range at any input, V
Output voltage range, V
Operating free-air temperature, TA, TL16C2552 0°C to 70°C
Operating free-air temperature, TA, TL16C2552I -40°C to 85°C
Storage temperature range, T
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to VSS.

(2)

CC

I

O

stg

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

1.8 V ±10% MIN NOM MAX UNIT

V

CC

V

I

V

IH

V

IL

V

O

I

OH

I

OL

Supply voltage 1.62 1.8 1.98 V
Input voltage 0 V
High-level input voltage 1.4 1.98 V
Low-level input voltage -0.3 0.4 V
Output voltage 0 V
High-level output current (all outputs) 0.5 mA
Low-level output current (all outputs) 1 mA
Oscillator/clock speed 10 MHz

(1)

UNIT

-0.5 V to 7 V

-0.5 V to 7 V

-0.5 V to 7 V

-65°C to 150°C

CC

CC

V

V

2.5 V ±10% MIN NOM MAX UNIT

V

CC

V

I

V

IH

V

IL

V

O

I

OH

I

OL

Supply voltage 2.25 2.5 2.75 V
Input voltage 0 V

CC

High-level input voltage 1.8 2.75 V
Low-level input voltage -0.3 0.6 V
Output voltage 0 V

CC

High-level output current (all outputs) 1 mA
Low-level output current (all outputs) 2 mA
Oscillator/clock speed 16 MHz

3.3 V ±10% MIN NOM MAX UNIT

V

CC

V

I

V

IH

V

IL

V

O

I

OH

I

OL

Supply voltage 3 3.3 3.6 V
Input voltage 0 V
High-level input voltage 0.7V

CC

Low-level input voltage 0.3V
Output voltage 0 V

CC

CC
CC

High-level output current (all outputs) 1.8 mA
Low-level output current (all outputs) 3.2 mA
Oscillator/clock speed 20 MHz

5 V ±10% MIN NOM MAX UNIT

V

CC

V

I

Supply voltage 4.5 5 5.5 V
Input voltage 0 V

CC

V

V

V
V
V
V

V

8

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SLWS163A – SEPTEMBER 2005 – REVISED JUNE 2006

RECOMMENDED OPERATING CONDITIONS (continued)

over operating free-air temperature range (unless otherwise noted)

5 V ±10% MIN NOM MAX UNIT

V

IH

V

IL

V

O

I

OH

I

OL

High-level input voltage All except XTAL1, XTAL2 2 V

XTAL1, XTAL2 0.7V

CC

Low-level input voltage All except XTAL1, XTAL2 0.8 V

XTAL1, XTAL2 0.3V
Output voltage 0 V
High-level output current (all outputs) 4 mA
Low-level output current (all outputs) 4 mA
Oscillator/clock speed 24 MHz

ELECTRICAL CHARACTERISTICS

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

1.8 V Nominal
PARAMETER TEST CONDITIONS MIN TYP

V

High-level output voltage

OH

V

Low-level output voltage

OL

I

Input current V

I

I

High-impedance-state output V

OZ

current mode or chip deselected

I

Supply current V

CC

C

Clock input impedance 15 20 pF

i(CL

K)

C

Clock output impedance 20 30 pF

O(C

LK)

C

Input impedance 6 10 pF

I

C

Output impedance 10 20 pF

O

(1) All typical values are at V
(2) These parameters apply for all outputs except XTAL2.

(2)

(2)

IOH= -0.5 mA 1.3 V
IOL= 1 mA 0.5 V

CC

floating

CC

CC

CTSA, CTSB, RIA, and RIB at 1.4 V, All other inputs at 0.4 V,
XTAL1 at 10 MHz, No load on outputs

V

CC

TA= 25°C, All other terminals grounded

= 1.8 V and TA= 25°C.

CC

= 1.98 V, V

= 1.98 V, V

= 0, VI= 0 to 1.98 V, All other terminals 10 µA

SS

= 0, VI= 0 to 1.98 V, Chip selected in write ±20 µA

SS

= 1.98 V, TA= 0°C, RXA, RXB, DSRA, DSRB, CDA, CDB, 1.5 mA

= 0, V

= 0, f = 1 MHz,

SS

TL16C2552

CC
CC

(1)

V

MAX UNIT

ELECTRICAL CHARACTERISTICS

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

2.5 V Nominal
PARAMETER TEST CONDITIONS MIN TYP

V
V
I

I

I

OZ

I

CC

High-level output voltage

OH

Low-level output voltage

OL

Input current V

High-impedance-state output V
current write mode or chip deselected

Supply current V

(1) All typical values are at V
(2) These parameters apply for all outputs except XTAL2.

ADDED SPACE

(2)

IOH= -1 mA 1.8 V

(2)

IOL= 2 mA 0.5 V

floating

CDB, CTSA, CTSB, RIA, and RIB at 1.8 V, All other inputs at

0.6 V, XTAL1 at 16 MHz, No load on outputs

= 2.5 V and TA= 25°C.

CC

= 2.75 V, V

CC

= 2.75 V, V

CC

= 2.75 V, TA= 0°C, RXA, RXB, DSRA, DSRB, CDA, 2.5 mA

CC

= 0, VI= 0 to 2.75 V, All other terminals 10 µA

SS

= 0, VI= 0 to 2.75 V, Chip selected in ±20 µA

SS

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(1)

MAX UNIT

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TL16C2552

SLWS163A – SEPTEMBER 2005 – REVISED JUNE 2006

ELECTRICAL CHARACTERISTICS (continued)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

2.5 V Nominal
PARAMETER TEST CONDITIONS MIN TYP

C
C
C
C

ELECTRICAL CHARACTERISTICS

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

V
V
I

I

I

OZ

I

CC

C
C
C
C

(1) All typical values are at V
(2) These parameters apply for all outputs except XTAL2.

Clock input impedance 15 20 pF

i(CLK)

Clock output impedance 20 30 pF

O(CLK)

Input impedance 6 10 pF

I

Output impedance 10 20 pF

O

V

= 0, V

CC

TA= 25°C, All other terminals grounded

= 0, f = 1 MHz,

SS

3.3 V Nominal
PARAMETER TEST CONDITIONS MIN TYP

OH
OL

High-level output voltage
Low-level output voltage
Input current V

High-impedance-state output V
current write mode or chip deselected

Supply current V

(2)

IOH= -1.8 mA 2.4 V

(2)

IOL= 3.2 mA 0.5 V

= 3.6 V, V

CC

floating

= 3.6 V, V

CC

= 3.6 V, TA= 0°C, RXA, RXB, DSRA, DSRB, CDA, 4 mA

CC

CDB, CTSA, CTSB, RIA, and RIB at 2 V, All other inputs

= 0, VI= 0 to 3.6 V, All other terminals 10 µA

SS

= 0, VI= 0 to 3.6 V, Chip selected in ±20 µA

SS

at 0.8 V, XTAL1 at 20 MHz, No load on outputs

i(CLK)
O(CLK)
I
O

Clock input impedance 15 20 pF
Clock output impedance 20 30 pF
Input impedance 6 10 pF

V

= 0, V

CC

TA= 25°C, All other terminals grounded

= 0, f = 1 MHz,

SS

Output impedance 10 20 pF

= 3.3 V and TA= 25°C.

CC

(1)

MAX UNIT

(1)

MAX UNIT

10

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SLWS163A – SEPTEMBER 2005 – REVISED JUNE 2006

ELECTRICAL CHARACTERISTICS

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

5 V Nominal

PARAMETER TEST CONDITIONS MIN TYP

V
V
I

I

I

OZ

I

CC

C
C
C
C

High-level output voltage

OH

Low-level output voltage

OL

Input current V

High-impedance-state output V
current write mode or chip deselected

Supply current V

Clock input impedance 15 20 pF

i(CLK)

Clock output impedance 20 30 pF

O(CLK)

Input impedance 6 10 pF

I

Output impedance 10 20 pF

O

(1) All typical values are at V
(2) These parameters apply for all outputs except XTAL2.

(2)

(2)

= 5 V and TA= 25°C.

CC

IOH= -4 mA 4 V
IOL= 4 mA 0.4 V

= 5.5 V, V

CC

terminals floating

= 5.5 V, V

CC

= 5.5 V, TA= 0°C, RXA, RXB, DSRA, DSRB, 7.5 mA

CC

CDA, CDB, CTSA, CTSB, RIA, and RIB at 2 V, All

= 0, VI= 0 to 5.5 V, All other 10 µA

SS

= 0, VI= 0 to 5.5 V, Chip selected in ±20 µA

SS

other inputs at 0.8 V, XTAL1 at 24 MHz, No load on
outputs

V

= 0, V

CC

TA= 25°C, All other terminals grounded

= 0, f = 1 MHz,

SS

TL16C2552

(1)

MAX UNIT

TIMING REQUIREMENTS

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER FIGURE 1.8 V 2.5 V 3.3 V 5 V UNIT

t

Pulse duration, RESET t

w8

t

Pulse duration, clock high t

w1

t

Pulse duration, clock low t

w2

t

Cycle time, read (tw7+ td8+ th7) RC 8 115 80 62 57 ns

cR

t

Cycle time, write (tw6+ td5+ th4) WC 7 115 80 62 57 ns

cW

t

Pulse duration, IOW or CS t

w6

t

Pulse duration, IOR or CS t

w7

t

Setup time, data valid before IOW↑ or CS↑ t

SU3

t

Hold time, address valid after IOW↑ or CS↑ t

h4

t

Hold time, data valid after IOW↑ or CS↑ t

h5

t

Hold time, data valid after IOR↑ or CS↑ t

h7

t

Delay time, address valid before IOW↓ or CS↓ t

d5

t

Delay time, address valid to IOR↓ or CS↓ t

d8

t

Delay time, IOR↓ or CS↓ to data valid t

d10

t

Delay time, IOR↑ or CS↑ to floating data t

d11

t

Write cycle to write cycle delay 7 100 75 60 50 ns

d12

t

Read cycle to read cycle delay 8 100 75 60 50 ns

d13

ALT. TEST

SYMBOL CONDITIONS

RESET

XH

XL

IOW

IOR

DS

WA

DH

RA

AW

AR

RVD

HZ

6 40 25 20 18 ns

7 80 55 45 40 ns
8 80 55 45 40 ns
7 25 20 15 15 ns
7 20 15 10 10 ns
7 15 10 5 5 ns
8 20 15 10 10 ns
7 15 10 7 7 ns
8 15 10 7 7 ns
8 CL= 30 pF 55 35 25 20 ns
8 CL= 30 pF 40 30 20 20 ns

MIN MAX MIN MAX MIN MAX MIN MAX

1 1 1 1 µs

LIMITS

BAUD GENERATOR SWITCHING CHARACTERISTICS

over recommended ranges of supply voltage and operating free-air temperature, CL= 30 pF (for FN package only)

LIMITS

PARAMETER FIGURE 1.8 V 2.5 V 3.3 V 5 V UNIT

t

Pulse duration, BAUDOUT low t

w3

t

Pulse duration, BAUDOUT high t

w4

t

Delay time, XIN ↑ to BAUDOUT↑ t

d1

t

Delay time, XIN ↑ ↓ to BAUDOUT↓ t

d2

ALT. TEST

SYMBOL CONDITIONS

LW

HW

BLD

BHD

6 CLK ÷ 2 80 50 42 35 ns
6 CLK ÷ 2 80 50 42 35 ns
6 55 40 30 25 ns
6 55 40 30 25 ns

MIN MAX MIN MAX MIN MAX MIN MAX

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11