Texas Instruments SN74ACT534DBLE, SN74ACT534DBR, SN74ACT534DW, SN74ACT534DWR, SN74ACT534N Datasheet
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SN54ACT534, SN74ACT534
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS556B – NOVEMBER 1995 – REVISED JANUARY 2000
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Inputs Are TTL-Voltage Compatible
D
3-State Inverting Outputs Drive Bus Lines
Directly
D
Full Parallel Access for Loading
D
EPIC
(Enhanced-Performance Implanted
CMOS) 1-µm Process
D
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK) and
Flatpacks (W), and Standard Plastic (N) and
Ceramic (J) DIPs
description
These octal edge-triggered D-type flip-flops
feature 3-state outputs designed specifically for
driving highly capacitive or relatively
low-impedance loads. The devices are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
On the positive transition of the clock (CLK) input,
the Q
outputs are set to the complements of the
logic levels set up at the data (D) inputs.
A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal logic
state (high or low logic levels) or the
high-impedance state. In the high-impedance
state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and
increased drive provide the capability to drive bus
lines without need for interface or pullup
components.
OE
does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
The SN54ACT534 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74ACT534 is characterized for operation from –40°C to 85°C.
Copyright 2000, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
EPIC is a trademark of Texas Instruments Incorporated.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
V
CC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
SN54ACT534 ...J OR W PACKAGE
SN74ACT534 .. . DB, DW, N, OR PW PACKAGE
(TOP VIEW)
3212019
9
10 11 12 13
4
5
6
7
8
18
17
16
15
14
8D
7D
7Q
6Q
6D
2D
2Q
3Q
3D
4D
SN54ACT534 . . . FK PACKAGE
(TOP VIEW)
1D1QOE
5Q
5D
8Q
4Q
GND
CLK
V
CC
SN54ACT534, SN74ACT534
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS556B – NOVEMBER 1995 – REVISED JANUARY 2000
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
OE CLK D
Q
L ↑ H L
L ↑ LH
L H or L X Q
0
H X X Z
logic symbol
†
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
1D
3
1D
4
2D
7
3D
8
4D
13
5D
14
6D
17
7D
18
8D
2
5
6
9
12
15
16
19
EN
1
C1
11
CLK
OE
1
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
logic diagram (positive logic)
OE
CLK
1D
1Q
To Seven Other Channels
1D
C1
1
11
3
2
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
‡
Supply voltage range, V
CC
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±200 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): DB package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 69°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 83°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
SN54ACT534, SN74ACT534
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS556B – NOVEMBER 1995 – REVISED JANUARY 2000
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Note 3)
SN54ACT534 SN74ACT534
MIN MAX MIN MAX
UNIT
V
CC
Supply voltage 4.5 5.5 4.5 5.5 V
V
IH
High-level input voltage 2 2 V
V
IL
Low-level input voltage 0.8 0.8 V
V
I
Input voltage 0 V
CC
0 V
CC
V
V
O
Output voltage 0 V
CC
0 V
CC
V
I
OH
High-level output current –24 –24 mA
I
OL
Low-level output current 24 24 mA
∆t/∆v Input transition rise or fall rate 0 8 0 8 ns/V
T
A
Operating free-air temperature –55 125 –40 85 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C SN54ACT534 SN74ACT534
PARAMETER
TEST CONDITIONS
V
CC
MIN TYP MAX MIN MAX MIN MAX
UNIT
4.5 V 4.4 4.49 4.4 4.4
I
OH
= –
50 µA
5.5 V 5.4 5.49 5.4 5.4
4.5 V 3.8 3.7 3.76
V
OH
I
OH
= –24
mA
5.5 V 4.86 4.7 4.76
V
IOH = –50 mA
†
5.5 V 3.85
IOH = –75 mA
†
5.5 V 3.85
4.5 V 0.1 0.1 0.1
I
OL
= 50 µ
A
5.5 V 0.1 0.1 0.1
4.5 V 0.36 0.5 0.44
V
OL
I
OL
= 24
mA
5.5 V 0.36 0.5 0.44
V
IOL = 50 mA
†
5.5 V 1.65
IOL = 75 mA
†
5.5 V 1.65
I
OZ
VO = VCC or GND 5.5 V ±0.25 ±5 ±2.5 µA
I
I
VI = VCC or GND 5.5 V ±0.1 ±1 ±1 µA
I
CC
VI = VCC or GND, IO = 0 5.5 V 4 80 40 µA
∆I
CC
‡
One input at 3.4 V ,
Other inputs at GND or V
CC
5.5 V 0.6 1.6 1.5 mA
C
i
VI = VCC or GND 5 V 4.5 pF
†
Not more than one output should be tested at a time, and the duration of the test should not exceed 2 ms.
‡
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
TA = 25°C SN54ACT534 SN74ACT534
MIN MAX MIN MAX MIN MAX
UNIT
t
w
Pulse duration, CLK high or low 3.5 5 3.5 ns
t
su
Setup time, data before CLK↑ 3.5 5 4 ns
t
h
Hold time, data after CLK↑ 1 3 1.5 ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54ACT534, SN74ACT534
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS556B – NOVEMBER 1995 – REVISED JANUARY 2000
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
FROM TO
TA = 25°C SN54ACT534 SN74ACT534
PARAMETER
(INPUT) (OUTPUT)
MIN MAX MIN MAX MIN MAX
UNIT
f
max
100 85 120 MHz
t
PLH
2.5 11.5 1.5 14 2 12.5
t
PHL
CLK
Q
2 10.5 1.5 13 2 12
ns
t
PZH
2.5 12 1.5 14 2 12.5
t
PZL
OE
Q
2 11 1.5 13 2 11.5
ns
t
PHZ
1.5 12.5 1.5 14.5 1 13.5
t
PLZ
OE
Q
1.5 10.5 1.5 11.5 1 10.5
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
C
pd
Power dissipation capacitance CL = 50 pF, f = 1 MHz 40 pF
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54ACT534, SN74ACT534
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS556B – NOVEMBER 1995 – REVISED JANUARY 2000
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
50% V
CC
3 V
3 V
0 V
0 V
t
h
t
su
VOLTAGE WAVEFORMS
Data Input
t
PLH
t
PHL
V
OH
V
OL
3 V
0 V
Input
Output
Timing Input
50% V
CC
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
2 × V
CC
500 Ω
500 Ω
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
CC
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
V
OL
V
OH
t
PZL
t
PZH
t
PLZ
t
PHZ
≈V
CC
0 V
50% V
CC
VOL + 0.3 V
50% V
CC
≈0 V
Open
VOLTAGE WAVEFORMS
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open
2 × V
CC
Open
TEST S1
3 V
0 V
t
w
VOLTAGE WAVEFORMS
Input
VOH – 0.3 V
3 V
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one input transition per measurement.
VOLTAGE WAVEFORMS
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
Figure 1. Load Circuit and Voltage Waveforms
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Copyright 2000, Texas Instruments Incorporated
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