SN54ACT1284, SN74ACT1284
7-BIT BUS INTERFACES
WITH 3-STATE OUTPUTS
SCAS459B – NOVEMBER 1994 – REVISED APRIL 1996
D
3-State Outputs Directly Drive Bus Lines
D
Flow-Through Architecture Optimizes PCB
Layout
D
Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Designed for the IEEE 1284-I (Level 1 Type)
and IEEE 1284-II (Level 2 Type) Electrical
Specifications
D
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW), and
DIP (N) Packages, Ceramic Chip Carriers
(FK), Flat (W), and DIP (J) Packages
description
The ’ACT1284 are designed for asynchronous
two-way communication between data buses.
The control function minimizes external timing
requirements.
The devices allow data transmission in either the
A-to-B or the B-to-A direction for bits 1, 2, 3, and
4, depending on the logic level at the
direction-control (DIR) input. Bits 5, 6, and 7,
however, always transmit in the A-to-B direction.
SN54ACT1284 ...J OR W PACKAGE
SN74ACT1284 . . . DB, DW, N, OR PW PACKAGE
A4
GND
GND
A5
A6
(TOP VIEW)
A1
1
A2
2
A3
3
A4
4
GND
GND
A5
A6
A7
DIR
FK PACKAGE
(TOP VIEW)
5
6
7
8
9
10
A3A2A1
3212019
4
5
6
7
8
9
10 11 12 13
A7
DIR
HD
20
19
18
17
16
15
14
13
12
11
B1
B7
B2
18
17
16
15
14
B6
B1
B2
B3
B4
V
V
B5
B6
B7
HD
CC
CC
B3
B4
V
V
B5
CC
CC
The output drive for each mode is determined by the high drive (HD) control pin. When HD is high, the high drive
is delivered by the totem-pole configuration, and when HD is low, the outputs are open drain. This meets the
drive requirements as specified in the IEEE 1284-I (level 1 type) and the IEEE 1284-II (level 2 type) parallel
peripheral-interface specification.
The SN54ACT1284 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ACT1284 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
DIR HD
Open drain A to B: Bits 5, 6, 7
Totem pole B to A: Bits 1, 2, 3, 4
L H Totem pole B to A: Bits 1, 2, 3, 4 and A to B: Bits 5, 6, 7
H L Open drain A to B: Bits 1, 2, 3, 4, 5, 6, 7
H H Totem pole A to B: Bits 1, 2, 3, 4, 5, 6, 7
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Copyright 1996, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN54ACT1284, SN74ACT1284
7-BIT BUS INTERFACES
WITH 3-STATE OUTPUTS
SCAS459B – NOVEMBER 1994 – REVISED APRIL 1996
logic diagram (positive logic)
HD
DIR
A1, A2, A3, A4
B1, B2, B3, B4
A5, A6, A7
B5, B6, B7
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B-port input and output voltage range, VI and VO (see Notes 1 and 2) –2 V to 7 V. . . . . . . . . . . . . . . . . . . . . .
A-port input and output voltage range, V
Input clamp current, IIK (VI < 0 or VI > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through V
Package thermal impedance, θ
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The ac input voltage pulsewidth is limited to 20 ns if the input voltage goes more negative than –0.5 V.
3. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
or GND ±200 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
JA
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
and VO (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . .
I
(see Note 3): DB package 115°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package 97°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 128°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265