Texas Instruments SN74ABT646DBLE, SN74ABT646DBR, SN74ABT646DGVR, SN74ABT646DW, SN74ABT646DWR Datasheet

SN54ABT646, SN74ABT646

OCTAL BUS TRANSCEIVERS AND REGISTERS

WITH 3-STATE OUTPUTS

SCBS068E – JULY 1991 – REVISED JULY 1994

• State-of-the-Art

EPIC-ΙΙB

 BiCMOS Design

Significantly Reduces Power Dissipation

• ESD Protection Exceeds 2000 V Per

MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model (C = 200 pF,
R = 0)

• Latch-Up Performance Exceeds 500 mA

Per JEDEC Standard JESD-17

• Typical V

< 1 V at V

• High-Drive Outputs (–32-mA I

(Output Ground Bounce)

OLP

= 5 V, TA = 25°C

CC

OH

,

64-mA IOL)

• Package Options Include Plastic

Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK), and
Plastic (NT) and Ceramic (JT) DIPs

description

These devices consist of bus transceiver circuits,
D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the
input bus or from the internal registers. Data on the
A or B bus is clocked into the registers on the
low-to-high transition of the appropriate clock
(CLKAB or CLKBA) input. Figure 1 illustrates the
four fundamental bus-management functions that
can be performed with the ′ABT646.

Output-enable (OE) and direction-control (DIR)
inputs are provided to control the transceiver
functions. In the transceiver mode, data present at
the high-impedance port may be stored in either
register or in both.

SN74ABT646 . . . DB, DW, NT, OR PW PACKAGE

SN54ABT646 . . . JT PACKAGE

(TOP VIEW)

CLKAB

GND

SN54ABT646 . . . FK PACKAGE

A1
A2
A3

NC

A4
A5
A6

NC – No internal connection

1

SAB

2

DIR

3

A1

4

A2

5

A3

6

A4

7

A5

8

A6

9

A7

10

A8

11
12

(TOP VIEW)

DIR

SAB

CLKAB

432128

5
6
7
8
9
10
11

12 13 14 15

A8

A7

GND

24
23
22
21
20
19
18
17
16
15
14
13

NC

16

NC

CC

V

27 26

17 18

B8

V
CLKBA
SBA
OE
B1
B2
B3
B4
B5
B6
B7
B8

CLKBA

B7

CC

SBA

25
24
23
22
21
20
19

B6

OE
B1
B2
NC
B3
B4
B5

The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The
direction control (DIR) determines which bus will receive data when OE

is low. In the isolation mode (OE high),

A data may be stored in one register and/or B data may be stored in the other register.
When an output function is disabled, the input function is still enabled and may be used to store and transmit

data. Only one of the two buses, A or B, may be driven at a time.
T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74ABT646 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count

and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54ABT646 is characterized for operation over the full military temperature range of –55°C to 125°C. The

SN74ABT646 is characterized for operation from –40°C to 85°C.

EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.

UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1994, Texas Instruments Incorporated

2–1

SN54ABT646, SN74ABT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS

SCBS068E – JULY 1991 – REVISED JULY 1994

21
OE

L

BUS A

3

DIR

L

BUS A

1

CLKAB

REAL-TIME TRANSFER

BUS B TO BUS A

CLKBA

X

23

BUS B

22

2

SAB

X

SBA

X

L

BUS B

21
OE

BUS A

3

DIR

L

H

BUS A

1

CLKAB

X

REAL-TIME TRANSFER

BUS A TO BUS B

23

CLKBA

X

2

SAB

L

BUS B

22

SBA

X

BUS B

21

X
X
H

3

DIR

X
X
X

1

CLKAB23CLKBA

↑

XX

STORAGE FROM

A, B, OR A AND B

2

22

SAB

X

↑
↑↑

SBA

X

X

X
X
X

Figure 1. Bus-Management Functions

Pin numbers shown are for DB, DW, JT, NT, and PW packages.

2–2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

21

OEOE

L
LH L XHX

3

DIR

L

TRANSFER STORED DA TA

1

CLKAB

X

TO A AND/OR B

23

CLKBA

L

2

SAB

X

22

SBA

H

SN54ABT646, SN74ABT646

OPERATION OR FUNCTION

OCTAL BUS TRANSCEIVERS AND REGISTERS

WITH 3-STATE OUTPUTS

SCBS068E – JULY 1991 – REVISED JULY 1994

FUNCTION TABLE

INPUTS

OE DIR CLKAB CLKBA SAB SBA A1 THRU A8 B1 THRU B8

X X ↑ X X X Input Unspecified
X XX ↑ X X Unspecified
H X ↑ ↑ X X Input Input Store A and B data
H X H or L H or L X X Input disabled Input disabled Isolation, hold storage
L L X X X L Output Input Real-time B data to A bus
L L X H or L X H Output Input Stored B data to A bus
L H X X L X Input Output Real-time A data to B bus
L H H or L X H X Input Output Stored A data to B bus

†

The data output functions may be enabled or disabled by various signals at the OE
i.e., data at the bus pins will be stored on every low-to-high transition of the clock inputs.

DATA I/Os

†

†

Input Store B, A unspecified

and DIR inputs. Data input functions are always enabled;

Store A, B unspecified

†
†

logic symbol

‡

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the DB, DW, JT, NT, and PW packages.

‡

OE

DIR

CLKBA

SBA

CLKAB

SAB

A1

A2
A3
A4
A5
A6
A7
A8

21
3

23
22

1

2

4

5
6

7
8
9
10
11

G3
3 EN1 [BA]

3 EN2 [AB]

C4

G5

C6

G7

5

≥1

1

5

7

6D ≥1

7

1

4D

1

2

20

19
18
17
16
15
14
13

B1

B2
B3
B4
B5
B6
B7
B8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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