Texas Instruments SN74ABT646DBLE, SN74ABT646DBR, SN74ABT646DGVR, SN74ABT646DW, SN74ABT646DWR Datasheet
...
SN54ABT646, SN74ABT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS068E – JULY 1991 – REVISED JULY 1994
• State-of-the-Art
EPIC-ΙΙB
BiCMOS Design
Significantly Reduces Power Dissipation
• ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model (C = 200 pF,
R = 0)
• Latch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17
• Typical V
< 1 V at V
• High-Drive Outputs (–32-mA I
(Output Ground Bounce)
OLP
= 5 V, TA = 25°C
CC
OH
,
64-mA IOL)
• Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK), and
Plastic (NT) and Ceramic (JT) DIPs
description
These devices consist of bus transceiver circuits,
D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the
input bus or from the internal registers. Data on the
A or B bus is clocked into the registers on the
low-to-high transition of the appropriate clock
(CLKAB or CLKBA) input. Figure 1 illustrates the
four fundamental bus-management functions that
can be performed with the ′ABT646.
Output-enable (OE) and direction-control (DIR)
inputs are provided to control the transceiver
functions. In the transceiver mode, data present at
the high-impedance port may be stored in either
register or in both.
SN74ABT646 . . . DB, DW, NT, OR PW PACKAGE
SN54ABT646 . . . JT PACKAGE
(TOP VIEW)
CLKAB
GND
SN54ABT646 . . . FK PACKAGE
A1
A2
A3
NC
A4
A5
A6
NC – No internal connection
1
SAB
2
DIR
3
A1
4
A2
5
A3
6
A4
7
A5
8
A6
9
A7
10
A8
11
12
(TOP VIEW)
DIR
SAB
CLKAB
432128
5
6
7
8
9
10
11
12 13 14 15
A8
A7
GND
24
23
22
21
20
19
18
17
16
15
14
13
NC
16
NC
CC
V
27 26
17 18
B8
V
CLKBA
SBA
OE
B1
B2
B3
B4
B5
B6
B7
B8
CLKBA
B7
CC
SBA
25
24
23
22
21
20
19
B6
OE
B1
B2
NC
B3
B4
B5
The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The
direction control (DIR) determines which bus will receive data when OE
is low. In the isolation mode (OE high),
A data may be stored in one register and/or B data may be stored in the other register.
When an output function is disabled, the input function is still enabled and may be used to store and transmit
data. Only one of the two buses, A or B, may be driven at a time.
T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74ABT646 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count
and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54ABT646 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74ABT646 is characterized for operation from –40°C to 85°C.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1994, Texas Instruments Incorporated
2–1
SN54ABT646, SN74ABT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS068E – JULY 1991 – REVISED JULY 1994
21
OE
L
BUS A
3
DIR
L
BUS A
1
CLKAB
REAL-TIME TRANSFER
BUS B TO BUS A
CLKBA
X
23
BUS B
22
2
SAB
X
SBA
X
L
BUS B
21
OE
BUS A
3
DIR
L
H
BUS A
1
CLKAB
X
REAL-TIME TRANSFER
BUS A TO BUS B
23
CLKBA
X
2
SAB
L
BUS B
22
SBA
X
BUS B
21
X
X
H
3
DIR
X
X
X
1
CLKAB23CLKBA
↑
XX
STORAGE FROM
A, B, OR A AND B
2
22
SAB
X
↑
↑↑
SBA
X
X
X
X
X
Figure 1. Bus-Management Functions
Pin numbers shown are for DB, DW, JT, NT, and PW packages.
2–2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
21
OEOE
L
LH L XHX
3
DIR
L
TRANSFER STORED DA TA
1
CLKAB
X
TO A AND/OR B
23
CLKBA
L
2
SAB
X
22
SBA
H
SN54ABT646, SN74ABT646
OPERATION OR FUNCTION
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS068E – JULY 1991 – REVISED JULY 1994
FUNCTION TABLE
INPUTS
OE DIR CLKAB CLKBA SAB SBA A1 THRU A8 B1 THRU B8
X X ↑ X X X Input Unspecified
X XX ↑ X X Unspecified
H X ↑ ↑ X X Input Input Store A and B data
H X H or L H or L X X Input disabled Input disabled Isolation, hold storage
L L X X X L Output Input Real-time B data to A bus
L L X H or L X H Output Input Stored B data to A bus
L H X X L X Input Output Real-time A data to B bus
L H H or L X H X Input Output Stored A data to B bus
†
The data output functions may be enabled or disabled by various signals at the OE
i.e., data at the bus pins will be stored on every low-to-high transition of the clock inputs.
DATA I/Os
†
†
Input Store B, A unspecified
and DIR inputs. Data input functions are always enabled;
Store A, B unspecified
†
†
logic symbol
‡
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DB, DW, JT, NT, and PW packages.
‡
OE
DIR
CLKBA
SBA
CLKAB
SAB
A1
A2
A3
A4
A5
A6
A7
A8
21
3
23
22
1
2
4
5
6
7
8
9
10
11
G3
3 EN1 [BA]
3 EN2 [AB]
C4
G5
C6
G7
5
≥1
1
5
7
6D ≥1
7
1
4D
1
2
20
19
18
17
16
15
14
13
B1
B2
B3
B4
B5
B6
B7
B8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2–3
SN54ABT646, SN74ABT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS068E – JULY 1991 – REVISED JULY 1994
logic diagram (positive logic)
21
OE
3
DIR
SBA
SAB
23
22
1
2
One of Eight
Channels
CLKBA
CLKAB
1D
C1
4
A1
1D
C1
To Seven Other Channels
Pin numbers shown are for the DB, DW, JT, NT, and PW packages.
20
B1
2–4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT646, SN74ABT646
UNIT
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS068E – JULY 1991 – REVISED JULY 1994
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, V
Voltage range applied to any output in the high state or power-off state, VO –0.5 V to 5.5 V. . . . . . . . . . . . .
Current into any output in the low state, I
Input clamp current, I
Output clamp current, I
Maximum power dissipation at TA = 55°C (in still air) (see Note 2):DB package 0.65 W. . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils,
except for the NT package, which has a trace length of zero. For more information, refer to the
application note in the 1994
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(except I/O ports) (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
: SN54ABT646 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
SN74ABT646 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(VI < 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
(VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
DW package 1.7 W. . . . . . . . . . . . . . . . . . .
NT package 1.3 W. . . . . . . . . . . . . . . . . . . .
PW package 0.7 W. . . . . . . . . . . . . . . . . . .
ABT Advanced BiCMOS Technology Data Book
, literature number SCBD002B.
Package Thermal Considerations
recommended operating conditions (see Note 3)
SN54ABT646 SN74ABT646
MIN MAX MIN MAX
V
CC
V
IH
V
IL
V
I
I
OH
I
OL
∆t/∆v Input transition rise or fall rate 5 5 ns/V
T
A
NOTE 3: Unused or floating pins (input or I/O) must be held high or low.
Supply voltage 4.5 5.5 4.5 5.5 V
High-level input voltage 2 2 V
Low-level input voltage 0.8 0.8 V
Input voltage 0 V
High-level output current –24 –32 mA
Low-level output current 48 64 mA
Operating free-air temperature –55 125 –40 85 °C
CC
0 V
CC
V
†
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2–5
SN54ABT646, SN74ABT646
PARAMETER
TEST CONDITIONS
UNIT
V
V
V
4.5 V
V
V
V
V
I
CC
,
A
V
I
V
CC
GND
t
Set
CLKAB↑
CLKBA↑
ns
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS068E – JULY 1991 – REVISED JULY 1994
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C SN54ABT646 SN74ABT646
MIN TYP†MAX MIN MAX MIN MAX
V
IK
OH
OL
I
I
OZH
I
OZL
I
off
I
CEX
¶
I
O
I
CC
∆I
CC
C
i
C
io
* On products compliant to MIL-STD-883, Class B, this parameter does not apply.
†
All typical values are at VCC = 5 V.
‡
The parameters I
§
This data sheet limit may vary among suppliers.
¶
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
#
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V
VCC = 4.5 V, IOH = –3 mA 2.5 2.5 2.5
VCC = 5 V, IOH = –3 mA 3 3 3
=
CC
= 4.5
CC
V
= 5.5 V,
VI = VCC or GND
‡
VCC = 5.5 V, VO = 2.7 V 10
‡
VCC = 5.5 V, VO = 0.5 V –10
VCC = 0, VI or VO ≤ 4.5 V ±100 ±100 µA
VCC = 5.5 V, VO = 5.5 V Outputs high 50 50 50 µA
VCC = 5.5 V, VO = 2.5 V –50 –100 –180 –50 –180 –50 –180 mA
VCC = 5.5 V, IO = 0,
=
or
VCC = 5.5 V, One input at 3.4 V,
#
Other inputs at VCC or GND
VI = 2.5 V or 0.5 V Control inputs 7 pF
VO = 2.5 V or 0.5 V A or B ports 12 pF
and I
OZH
IOH = –24 mA 2 2
IOH = –32 mA 2* 2
IOL = 48 mA 0.55 0.55
IOL = 64 mA 0.55* 0.55
Control inputs ±1 ±1 ±1
A or B ports ±100 ±100 ±100
Outputs high 250 250 250 µA
Outputs low 30 30 30 mA
Outputs disabled 250 250 250 µA
include the input leakage current.
OZL
§
§
1.5 1.5 1.5 mA
50 10
–50 –10§µA
µ
§
µA
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 2)
f
clock
t
w
su
t
h
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
2–6
Clock frequency 0 125 0 125 0 125 MHz
Pulse duration, CLK high or low 4 4 4 ns
up time, A or B before
Hold time, A or B after CLKAB↑ or CLKBA↑ 0 0 0 ns
or
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
High 3.5 3.5 3.5
Low 3 3 3
VCC = 5 V,
TA = 25°C
MIN MAX MIN MAX MIN MAX
SN54ABT646 SN74ABT646
UNIT
SN54ABT646, SN74ABT646
(INPUT)
(OUTPUT)
CLKBA or CLKAB
A or B
ns
A or B
B or A
ns
SAB
SBA
†
B or A
ns
OE
A or B
ns
OE
A or B
ns
DIR
A or B
ns
DIR
A or B
ns
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS068E – JULY 1991 – REVISED JULY 1994
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
PARAMETER
f
max
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PZH
t
PZL
t
PHZ
t
†
These parameters are measured with the internal output state of the storage register opposite to that of the bus input.
PLZ
= 50 pF (unless otherwise noted) (see Figure 2)
L
FROM
or
TO
VCC = 5 V,
TA = 25°C
MIN TYP MAX MIN MAX MIN MAX
125 125 MHz
2.2 4 6.8 2.2 7.8
1.7 4 7.4 1.7 8.4
1.5 3 5.9 1.5 6.9
1.5 3.3 5.9 1.5 6.9
1.5 4 6.1 1.5 7.1
1.5 3.6 6.9 1.5 7.9
1 4.3 5.3 1 6.3
2.1 5.8 7.4 2.1 8.8
1.5 3.5 7.3 1.5 8.3
1.5 3 7 1.5 7.5
1.2 4.5 5.7 1.2 6.7
2.5 6.5 9 2.5 9.5
1.5 3.8 6.7 1.5 7.7
1.5 3.8 7.2 1.5 8.2
SN54ABT646 SN74ABT646
UNIT
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2–7
SN54ABT646, SN74ABT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS068E – JULY 1991 – REVISED JULY 1994
PARAMETER MEASUREMENT INFORMATION
7 V
From Output
Under Test
CL = 50 pF
(see Note A)
Input
500 Ω
500 Ω
LOAD CIRCUIT FOR OUTPUTS
t
w
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
S1
Open
GND
3 V
0 V
Timing Input
Data Input
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
t
su
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Open
Open
1.5 V
t
7 V
h
3 V
0 V
3 V
0 V
Input
(see Note B)
t
PLH
Output
t
PHL
Output
INVERTING AND NONINVERTING OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.
1.5 V 1.5 V
1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
Figure 2. Load Circuit and Voltage Waveforms
t
PHL
1.5 V
t
1.5 V1.5 V
PLH
3 V
0 V
V
V
V
V
OH
OL
OH
OL
Output
Output
Control
Control
Output
Waveform 1
S1 at 7 V
(see Note C)
Output
Waveform 2
S1 at Open
(see Note C)
1.5 V
t
PZL
t
PLZ
1.5 V
t
t
PZH
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
PHZ
1.5 V
VOLTAGE WAVEFORMS
1.5 V
VOL + 0.3 V
VOH – 0.3 V
3 V
0 V
3.5 V
V
OL
V
OH
[
0 V
2–8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCT OR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
Loading...