Texas Instruments SN74ABT3611-30PCB, SN74ABT3611-30PQ, SN74ABT3611-15PCB, SN74ABT3611-15PQ, SN74ABT3611-20PCB Datasheet
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SN74ABT3611
64 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E – JULY 1992 – REVISED APRIL 1998
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Free-Running CLKA and CLKB Can Be
Asynchronous or Coincident
D
64 × 36 Clocked FIFO Buffering Data From
Port A to Port B
D
Mailbox-Bypass Register In Each Direction
D
Programmable Almost-Full and
Almost-Empty Flags
D
Microprocessor Interface Control Logic
D
Full Flag and Almost-Full Flag
Synchronized by CLKA
D
Empty Flag and Almost-Empty Flag
Synchronized by CLKB
D
Passive Parity Checking on Each Port
D
Parity Generation Can Be Selected for Each
Port
D
Low-Power Advanced BiCMOS Technology
D
Supports Clock Frequencies up to 67 MHz
D
Fast Access Times of 10 ns
D
Package Options Include 120-Pin Thin
Quad Flat (PCB) and 132-Pin Plastic Quad
Flat (PQ) Packages
description
The SN74ABT361 1 is a high-speed, low-power BiCMOS clocked FIFO memory. It supports clock frequencies
up to 67 MHz and has read access times as fast as 10 ns. A 64 × 36 dual-port SRAM FIFO buffers data from
port A to port B. The FIFO has flags to indicate empty and full conditions and two programmable flags (almost
full and almost empty) to indicate when a selected number of words is stored in memory. Communication
between each port takes place through two 36-bit mailbox registers. Each mailbox register has a flag to signal
when new mail has been stored. Parity is checked passively on each port and can be ignored if not desired.
Parity generation can be selected for data read from each port. Two or more devices are used in parallel to create
wider datapaths.
The SN74ABT3611 is a clocked FIFO, which means each port employs a synchronous interface. All data
transfers through a port are gated to the low-to-high transition of a port clock by enable signals. The clocks for
each port are independent of one another and can be asynchronous or coincident. The enables for each port
are arranged to provide a simple bidirectional interface between microprocessors and/or buses with
synchronous control.
The full flag (FF
) and almost-full (AF) flag of the FIFO are two-stage synchronized to the port clock that writes
data to its array (CLKA). The empty flag (EF
) and almost-empty (AE) flag of the FIFO are two-stage
synchronized to the port clock that reads data from its array.
The SN74ABT3611 is characterized for operation from 0°C to 70°C.
For more information on this device family, see the following application reports:
•
FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control
(literature
number SCAA007)
•
Parity-Generate and Parity-Check Features for High-Bandwidth-Computing FIFO Applications
(literature number SCAA015)
• Metastability Performance of Clocked FIFOs (literature number SCZA004)
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN74ABT3611
64 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E – JULY 1992 – REVISED APRIL 1998
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
PCB PACKAGE
(TOP VIEW)
A23
A22
A21
GND
A20
A19
A18
A17
A16
A15
A14
A13
A12
A1 1
A10
GND
A9
A8
A7
V
CC
A6
A5
A4
A3
GND
A2
A1
A0
NC
NC
B22
B21
GND
B20
B19
B18
B17
B16
B15
B14
B13
B12
B1 1
B10
GND
B9
B8
B7
V
CC
B6
B5
B4
B3
GND
B2
B1
B0
EFB
AEB
NC
A24
A25
A26
ENA
CLKA
AFA
FFA
CSA
A27
A28
A29
A33
A30
A35
GND
B35
B34
B33
B32
B30
B29
B28
MBF2
W/RA
PEFA
ODD/EVEN
RST
NC
GND
NC
NC
MBF1
PEFB
PGB
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
B26
B25
B24
54
53
52
51
CLKB
ENB
W/RB
CSB
5556575859
60
V
CC
A34
FS0
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
91
92
93
94
95
A31
GND
MBB
V
CC
B27
PGA
MBA
NC
NC
A32
FS1
V
CC
V
CC
GND
B31
B23
NC – No internal connection
SN74ABT3611
64 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E – JULY 1992 – REVISED APRIL 1998
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
5251 83828180797877767574737271706968676665646362616059585756555453
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2
1
GND
NC
NC
A0
A1
A2
GND
A3
A4
A5
A6
V
CC
A7
A8
A9
GND
A10
A11
V
CC
A12
A13
A14
GND
A15
A16
A17
A18
A19
A20
GND
A21
A22
A23
GND
AEB
EFB
B0
B1
B2
GND
B3
B4
B5
B6
V
CC
B7
B8
B9
GND
B10
B11
V
CC
B12
B13
B14
GND
B15
B16
B17
B18
B19
B20
GND
B21
B22
B23
PQ PACKAGE
†
(TOP VIEW)
AFA
FFAVENA
CLKA
W/RA
PGA
PEFA
GND
MBF2
MBA
FS0
ODD/EVEN
RST
GNDNCNCNCNC
MBB
MBF1
GND
PGB
W/RB
CLKB
ENB
CSBNCNC
A24
A25
A26
GND
A27
A29
A30
A31
A32
GND
A33
A34
A35
GND
B35
B34
GND
B32
B31
B30
B29
B28
B27
GND
B26
B25
B24
CC
V
CC
CC
V
A28
CC
V
B33
CC
V
CC
V
CSA
FS1
PEFB
NC – No internal connection
†
Uses Yamaichi socket IC51-1324-828
SN74ABT3611
64 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E – JULY 1992 – REVISED APRIL 1998
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
EF
Port-A
Control
Logic
AF
FIFO
Programmable-
Flag
Offset Register
Port-B
Control
Logic
MBB
Parity
Gen/Check
Mail2
Register
Status-Flag
Logic
Write
Pointer
CLKA
CSA
W/RA
ENA
MBA
FF
FS0
A0–A35
Device
Control
64 × 36
SRAM
Output Register
Mail1
Register
Read
Pointer
FS1
MBF2
AE
B0–B35
CLKB
CSB
ENB
36
Parity
RST
MBF1
36
PEFB
PGB
ODD/
EVEN
Input Register
W/RB
Parity
Gen/Check
PEFA
PGA
Generation
36
SN74ABT3611
64 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E – JULY 1992 – REVISED APRIL 1998
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NAME
I/O DESCRIPTION
A0–A35 I/O Port-A data. The 36-bit bidirectional data port for side A.
AE O
Almost-empty flag. Programmable flag synchronized to CLKB. AE is low when the number of words in the FIFO is less
than or equal to the value in the offset register, X.
AF O
Almost-full flag. Programmable flag synchronized to CLKA. AF is low when the number of empty locations in the FIFO
is less than or equal to the value in the offset register, X.
B0–B35 I/O Port-B data. The 36-bit bidirectional data port for side B.
CLKA I
Port-A clock. CLKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous
or coincident to CLKB. FF
and AF are synchronized to the low-to-high transition of CLKA.
CLKB I
Port-B clock. CLKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronous
or coincident to CLKA. EF
and AE are synchronized to the low-to-high transition of CLKB.
CSA I
Port-A chip select. CSA must be low to enable a low-to-high transition of CLKA to read or write data on port A. The
A0–A35 outputs are in the high-impedance state when CSA
is high.
CSB I
Port-B chip select. CSB must be low to enable a low-to-high transition of CLKB to read or write data on port B. The
B0–B35 outputs are in the high-impedance state when CSB
is high.
EF O
Empty flag. EF is synchronized to the low-to-high transition of CLKB. When EF is low, the FIFO is empty and reads from
its memory are disabled. Data can be read from the FIFO to its output register when EF
is high. EF is forced low when
the device is reset and is set high by the second low-to-high transition of CLKB after data is loaded into empty FIFO
memory.
ENA I Port-A enable. ENA must be high to enable a low-to-high transition of CLKA to read or write data on port A.
ENB I Port-B enable. ENB must be high to enable a low-to-high transition of CLKB to read or write data on port B.
FF O
Full flag. FF is synchronized to the low-to-high transition of CLKA. When FF is low, the FIFO is full and writes to its
memory are disabled. FF
is forced low when the device is reset and is set high by the second low-to-high transition of
CLKA after reset.
FS1, FS0 I
Flag-offset selects. The low-to-high transition of RST latches the values of FS0 and FS1, which loads one of four preset
values into the almost-full and almost-empty offset register, X.
MBA I Port-A mailbox select. A high level on MBA chooses a mailbox register for a port-A read or write operation.
MBB I
Port-B mailbox select. A high level on MBB chooses a mailbox register for a port-B read or write operation. When the
B0–B35 outputs are active, a high level on MBB selects data from the mail1 register for output and a low level selects
the FIFO output register data for output.
MBF1 O
Mail1 register flag. MBF1 is set low by the low-to-high transition of CLKA that writes data to the mail1 register. W rites
to the mail1 register are inhibited while MBF1
is low. MBF1 is set high by a low-to-high transition of CLKB when a port-B
read is selected and MBB is high. MBF1
is set high when the device is reset.
MBF2 O
Mail2 register flag. MBF2 is set low by the low-to-high transition of CLKB that writes data to the mail2 register. W rites
to the mail2 register are inhibited while MBF2
is low. MBF2 is set high by a low-to-high transition of CLKA when a port-A
read is selected and MBA is high. MBF2
is set high when the device is reset.
ODD/
EVEN
I
Odd/even parity select. Odd parity is checked on each port when ODD/EVEN is high and even parity is checked when
ODD/EVEN
is low. ODD/EVEN also selects the type of parity generated for each port if parity generation is enabled
for a read operation.
PEFA
O
(port A)
Port-A parity error flag. When any byte applied to A0–A35 fails parity, PEFA is low. Bytes are organized as A0–A8,
A9–A17, A18–A26, and A27–A35, with the most-significant bit of each byte serving as the parity bit. The type of parity
checked is determined by the state of ODD/EVEN
.
The parity trees used to check the A0–A35 inputs are shared by the mail2 register to generate parity if parity generation
is selected by PGA. Therefore, if a mail2 read with parity generation is set up by having CSA low, ENA high, W/RA low ,
MBA high, and PGA high, PEFA is forced high, regardless of the state of the A0 –A35 inputs.
SN74ABT3611
64 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E – JULY 1992 – REVISED APRIL 1998
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions (continued)
TERMINAL
NAME
I/O DESCRIPTION
PEFB
O
(port B)
Port-B parity error flag. When any byte applied to terminals B0–B35 fails parity, PEFB is low. Bytes are organized as
B0–B8, B9–B17, B18–B26, and B27–B35, with the most-significant bit of each byte serving as the parity bit. The type
of parity checked is determined by the state of ODD/EVEN
.
The parity trees used to check the B0–B35 inputs are shared by the mail1 register to generate parity if parity generation
is selected by PGB. Therefore, if a mail1 read with parity generation is set up by having CSB low, ENB high, W/RB
low, MBB high, and PGB high, PEFB
is forced high regardless of the state of the B0–B35 inputs.
PGA I
Port-A parity generation. Parity is generated for mail2 register reads from port A when PGA is high. The type of parity
generated is selected by the state of ODD/EVEN
. Bytes are organized as A0–A8, A9–A17, A18–A26, and A27–A35.
The generated parity bits are output in the most-significant bit of each byte.
PGB I
Port-B parity generation. Parity is generated for data reads from port B when PGB is high. The type of parity generated
is selected by the state of ODD/EVEN
. Bytes are organized as B0 –B8, B9–B17, B18–B26, and B27–B35. The
generated parity bits are output in the most significant bit of each byte.
RST I
Reset. To reset the device, four low-to-high transitions of CLKA and four low-to-high transitions of CLKB must occur
while RST
is low. This sets AF , MBF1, and MBF2 high and EF , AE, and FF low . The low-to-high transition of RST latches
the status of FS1 and FS0 to select AF
and AE flag offset.
W/RA I
Port-A write/read select. W/RA high selects a write operation and a low selects a read operation on port A for a
low-to-high transition of CLKA. The A0–A35 outputs are in the high-impedance state when W/R
A is high.
W/RB I
Port-B write/read select. W/RB high selects a write operation and a low selects a read operation on port B for a
low-to-high transition of CLKB. The B0–B35 outputs are in the high-impedance state when W/R
B is high.
detailed description
reset
The SN74ABT3611 is reset by taking the reset (RST
) input low for at least four port-A clock (CLKA) and four
port-B clock (CLKB) low-to-high transitions. RST
can switch asynchronously to the clocks. A device reset
initializes the internal read and write pointers of the FIFO and forces the full flag (FF
) low, the empty flag (EF)
low, the almost-empty flag (AE
) low, and the almost-full flag (AF) high. A reset also forces the mailbox flags
(MBF1
, MBF2) high. After a reset, FF is set high after two low-to-high transitions of CLKA. The device must be
reset after power up before data is written to its memory.
A low-to-high transition on RST
loads the almost-full and almost-empty offset register (X) with the value selected
by the flag-select (FS0, FS1) inputs. The values that can be loaded into the register are shown in Table 1.
T able 1. Flag Programming
FS1 FS0 RST
ALMOST-FULL AND
ALMOST-EMPTY FLAG
OFFSET REGISTER (X)
H H ↑ 16
H L ↑ 12
L H ↑ 8
L L ↑ 4
FIFO write/read operation
The state of the port-A data (A0 –A35) outputs is controlled by the port-A chip select (CSA
) and the port-A
write/read select (W/R
A). The A0–A35 outputs are in the high-impedance state when either CSA or W/RA is
high. The A0–A35 outputs are active when both CSA
and W/RA are low. Data is loaded into the FIFO from the
A0–A35 inputs on a low-to-high transition of CLKA when CSA
is low, W/RA is high, ENA is high, MBA is low,
and FF
is high (see Table 2).
SN74ABT3611
64 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E – JULY 1992 – REVISED APRIL 1998
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FIFO write/read operation (continued)
Table 2. Port-A Enable Function Table
CSA W/RA ENA MBA CLKA
A0–A35 OUTPUTS PORT FUNCTION
H X X X X In high-impedance state None
L H L X X In high-impedance state None
L H H L ↑ In high-impedance state FIFO write
L H H H ↑ In high-impedance state Mail1 write
L L L L X Active, mail2 register None
L L H L ↑ Active, mail2 register None
L L L H X Active, mail2 register None
L L H H ↑ Active, mail2 register Mail2 read (set MBF2 high)
The port-B control signals are identical to those of port A. The state of the port-B data (B0 –B35) outputs is
controlled by the port-B chip select (CSB
) and the port-B write/read select (W/RB). The B0–B35 outputs are
in the high-impedance state when either CSB
or W/RB is high. The B0–B35 outputs are active when both CSB
and W/RB are low. Data is read from the FIFO to the B0–B35 outputs by a low-to-high transition of CLKB when
CSB
is low, W/RB is low, ENB is high, MBB is high, and EF is high (see Table 3).
Table 3. Port-B Enable Function Table
CSB W/RB ENB MBB CLKB
B0–B35 OUTPUTS PORT FUNCTION
H X X X X In high-impedance state None
L H L X X In high-impedance state None
L H H L ↑ In high-impedance state None
L H H H ↑ In high-impedance state Mail2 write
L L L L X Active, FIFO output register None
L L H L ↑ Active, FIFO output register FIFO read
L L L H X Active, mail1 register None
L L H H ↑ Active, mail1 register Mail1 read (set MBF1 high)
The setup- and hold-time constraints to the port clocks for the port-chip selects (CSA, CSB) and write/read
selects (W/R
A, W/RB) are only for enabling write and read operations and are not related to high-impedance
control of the data outputs. If a port enable is low during a clock cycle, the port-chip select and write/read select
can change states during the setup- and hold-time window of the cycle.
SN74ABT3611
64 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E – JULY 1992 – REVISED APRIL 1998
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
synchronized FIFO flags
Each FIFO flag is synchronized to its port clock through two flip-flop stages. This is done to improve flag reliability
by reducing the probability of metastable events on their outputs when CLKA and CLKB operate
asynchronously to one another. FF
and AF are synchronized to CLKA. EF and AE are synchronized to CLKB.
Table 4 shows the relationship of the flags to the FIFO.
Table 4. FIFO Flag Operation
NUMBER OF WORDS
SYNCHRONIZED
TO CLKB
SYNCHRONIZED
TO CLKA
IN THE FIFO
EF AE AF FF
0 L L H H
1 to X H LHH
(X + 1) to [64 – (X + 1)] H HHH
(64 – X) to 63 H HLH
64 H H L L
†
X is the value in the almost-empty flag and almost-full flag offset register.
empty flag (EF)
The FIFO empty flag is synchronized to the port clock that reads data from its array (CLKB). When EF is high,
new data can be read to the FIFO output register. When EF
is low, the FIFO is empty and attempted FIFO reads
are ignored.
The FIFO read pointer is incremented each time a new word is clocked to its output register. A word written to
the FIFO can be read to the FIFO output register in a minimum of three port-B clock (CLKB) cycles; therefore,
EF
is low if a word in memory is the next data to be sent to the FIFO output register and two CLKB cycles have
not elapsed since the time the word was written. The empty flag of the FIFO is set high by the second low-to-high
transition of CLKB, and the new data word can be read to the FIFO output register in the following cycle.
A low-to-high transition on CLKB begins the first synchronization cycle of a write if the clock transition occurs
at time t
sk1
, or greater, after the write. Otherwise, the subsequent CLKB cycle can be the first synchronization
cycle (see Figure 4).
full flag (FF)
The FIFO full flag is synchronized to the port clock that writes data to its array (CLKA). When FF is high, an
SRAM location is free to receive new data. No memory locations are free when FF
is low and attempted writes
to the FIFO are ignored.
Each time a word is written to the FIFO, its write pointer is incremented. From the time a word is read from the
FIFO, its previous memory location is ready to be written in a minimum of three port-A clock cycles. FF
is low
if less than two CLKA cycles have elapsed since the next memory write location has been read. The second
low-to-high transition on CLKA after the read sets FF
high and data can be written in the following clock cycle.
A low-to-high transition on CLKA begins the first synchronization cycle of a read if the clock transition occurs
at time t
sk1
, or greater, after the read. Otherwise, the subsequent clock cycle can be the first synchronization
cycle (see Figure 5).
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