Texas Instruments SN74ABT2952ADBLE, SN74ABT2952ADBR, SN74ABT2952ADWR, SN74ABT2952ANT, SNJ54ABT2952AFK Datasheet

SN54ABT2952A, SN74ABT2952A

OCTAL BUS TRANSCEIVERS AND REGISTERS

WITH 3-STATE OUTPUTS

SCBS203D – AUGUST 1992 – REVISED JANUARY 1998

D

State-of-the-Art

EPIC-ΙΙB

 BiCMOS Design

Significantly Reduces Power Dissipation

D

Two 8-Bit Back-to-Back Registers Store
Data Flowing in Both Directions

D

Noninverting Outputs

D

T ypical V

(Output Ground Bounce) < 1 V

OLP

at VCC = 5 V, TA = 25°C

D

Latch-Up Performance Exceeds 500 mA Per
JESD 17

D

ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)

D

Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK),
Ceramic Flat (W) Package, and Plastic (NT)
and Ceramic (JT) DIPs

description

The ’ABT2952A transceivers consist of two 8-bit
back-to-back registers that store data flowing in
both directions between two bidirectional buses.
Data on the A or B bus is stored in the registers on
the low-to-high transition of the clock (CLKAB or
CLKBA) input provided that the clock-enable
(CLKENAB
output-enable (OEAB or OEBA) input low
accesses the data on either port.

T o ensure the high-impedance state during power
up or power down, OE should be tied to V
through a pullup resistor; the minimum value of
the resistor is determined by the current-sinking
capability of the driver.

or CLKENBA) input is low. Taking the

CC

SN54ABT2952A . . . JT OR W PACKAGE

SN74ABT2952A . . . DB, DW, PW, OR NT PACKAGE

OEAB

CLKAB

CLKENAB

SN54ABT2952A . . . FK PACKAGE

B5
B4
B3

NC

B2
B1

OEAB

NC – No internal connection

(TOP VIEW)

B8

1

B7

2

B6

3

B5

4

B4

5

B3

6

B2

7

B1

8
9
10
11

GND

12

(TOP VIEW)

B7

B8

B6

3212827

426

5
6
7
8
9
10
11

12 13 14 15 16 17 18

GND

CLKAB

CLKENAB

24
23
22
21
20
19
18
17
16
15
14
13

CC

V

NC

NC

CLKENBA

V

CC

A8
A7
A6
A5
A4
A3
A2
A1
OEBA
CLKBA
CLKENBA

A8

A7

A6

25

A5

24

A4

23

NC

22

A3

21

A2

20

A1

19

OEBA

CLKBA

The SN54ABT2952A is characterized for
operation over the full military temperature range
of –55°C to 125°C. The SN74ABT2952A is
characterized for operation from –40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1998, Texas Instruments Incorporated

On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.

1

SN54ABT2952A, SN74ABT2952A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS

SCBS203D – AUGUST 1992 – REVISED JANUARY 1998

logic symbol

FUNCTION TABLE

INPUTS

CLKENAB CLKAB OEAB A

H X L X B
X H or L L X B

L ↑ LL L
L ↑ LH H

X X H X Z

†

A-to-B data flow is shown; B-to-A data flow is similar,
but uses CLKENBA

‡

Level of B before the indicated steady-state input
conditions were established

, CLKBA, and OEBA.

†

OUTPUT

B

‡

0

‡

0

§

OEBA

CLKENBA

CLKBA

OEAB

CLKENAB

CLKAB

A1

A2
A3
A4
A5
A6
A7
A8

15
13

14

9

11

10

16

17
18
19
20
21
22
23

EN3
G1

1 C5

EN4

G2

2 C6

31

8

5D

16D

4

B1

7

B2

6

B3

5

B4

4

B5

3

B6

2

B7

1

B8

§

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the DB, DW, JT, NT, PW, and W packages.

2

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logic diagram (positive logic)

SN54ABT2952A, SN74ABT2952A

OCTAL BUS TRANSCEIVERS AND REGISTERS

WITH 3-STATE OUTPUTS

SCBS203D – AUGUST 1992 – REVISED JANUARY 1998

CLKENAB

CLKAB

OEAB

CLKENBA

CLKBA

OEBA

A1

11

10

9

13

14

15

16

C1

1D

8

B1

Pin numbers shown are for the DB, DW, JT, NT, PW, and W packages.

C1

1D

To Seven Other Channels

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

SN54ABT2952A, SN74ABT2952A

UNIT

OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS

SCBS203D – AUGUST 1992 – REVISED JANUARY 1998

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

†

Input voltage range, VI (except I/O ports) (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the high or power-off state, VO –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .

Current into any output in the low state, IO: SN54ABT2952A 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SN74ABT2952A 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I
Output clamp current, I
Package thermal impedance, θ

(V

< 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IK

I

(V

OK

< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

(see Note 2): DB package 104°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

DW package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NT package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 120°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

recommended operating conditions (see Note 3)

SN54ABT2952A SN74ABT2952A

MIN MAX MIN MAX

V
V
V
V
I

OH

I

OL

∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V
T

NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Supply voltage 4.5 5.5 4.5 5.5 V

CC

High-level input voltage 2 2 V

IH

Low-level input voltage 0.8 0.8 V

IL

Input voltage 0 V

I

High-level output current –24 –32 mA
Low-level output current 48 64 mA

Operating free-air temperature –55 125 –40 85 °C

A

Implications of Slow or Floating CMOS Inputs

, literature number SCBA004.

CC

0 V

CC

V

4

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SN54ABT2952A, SN74ABT2952A

PARAMETER

TEST CONDITIONS

UNIT

V

V

V

4.5 V

VOLV

V

V

I

V

V

V

GND

A

V

I

V

CC

or

t

Set

CLK↑

High or lo

ns

t

Hold ti

CLK↑

ns

OCTAL BUS TRANSCEIVERS AND REGISTERS

WITH 3-STATE OUTPUTS

SCBS203D – AUGUST 1992 – REVISED JANUARY 1998

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

TA = 25°C SN54ABT2952A SN74ABT2952A

MIN TYP†MAX MIN MAX MIN MAX

V

IK

OH

V

hys

I

I

OZH

I

OZL

I

off

I

CEX

I

O

I

CC

∆I
C

C

* On products compliant to MIL-PRF-38535, this parameter does not apply.
†

All typical values are at VCC = 5 V.

‡

The parameters I

§

Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

¶

This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.

Control inputs
A or B ports

‡

‡

§

A or B ports

¶

CC

Control inputs VI = 2.5 V or 0.5 V 3.5 pF

i

A or B ports VO = 2.5 V or 0.5 V 7.5 pF

io

OZH

VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V
VCC = 4.5 V, IOH = –3 mA 2.5 2.5 2.5
VCC = 5 V, IOH = –3 mA 3 3 3

=

CC

= 4.5

CC

= 5.5 V,

CC

VCC = 5.5 V, VO = 2.7 V 50* 10 50 µA
VCC = 5.5 V, VO = 0.5 V –50* –10 –50 µA
VCC = 0, VI or VO ≤ 4.5 V ±100* ±100 µA
VCC = 5.5 V,

VO = 5.5 V
VCC = 5.5 V, VO = 2.5 V –50 –100 –180 –50 –180 –50 –180 mA
VCC = 5.5 V,

IO = 0,

=

=

GND
VCC = 5.5 V, One input at 3.4 V,

Other inputs at VCC or GND

and I

include the input leakage current.

OZL

IOH = –24 mA 2 2
IOH = –32 mA 2* 2
IOL = 48 mA 0.55 0.55
IOL = 64 mA 0.55* 0.55

100 mV

=

or

I

CC

Outputs high 50 50 50 µA

Outputs high 1 250 250 250 µA
Outputs low 24 35 35 35 mA
Outputs disabled 0.5 250 250 250 µA

±1 ±1 ±1

±100 ±100 ±100

1.5 1.5 1.5 mA

µ

timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)

f

clock

t

w

su

h

VCC = 5 V,

TA = 25°C
MIN MAX MIN MAX MIN MAX

Clock frequency 0 150 0 150 0 150 MHz
Pulse duration, CLK high or low 3.3 3.3 3.3 ns

up time before

me after

A or B
CLKEN
A or B 1.5 1.5 1.5
CLKEN 2 2 2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

w

2.5 3 2.5
3 3 3

SN54ABT2952A SN74ABT2952A

UNIT

5

SN54ABT2952A, SN74ABT2952A

(INPUT)

(OUTPUT)

CLKAB

CLKBA

B or A

ns

OEBA

OEAB

A or B

ns

OEBA

OEAB

A or B

ns

OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS

SCBS203D – AUGUST 1992 – REVISED JANUARY 1998

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C

PARAMETER

f

max

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

= 50 pF (unless otherwise noted) (see Figure 1)

L

FROM

or

or

or

TO

VCC = 5 V,

TA = 25°C

MIN TYP MAX MIN MAX MIN MAX

150 150 150 MHz

2 3.3 5.2 2 6.3 2 5.9

2.5 4 6.1 2.5 6.8 2.5 6.3

1.5 3.2 4.7 1.5 5.7 1.5 5.6
2 3.7 5.7 2 6.7 2 6.6

1.5 3.5 5.1 1.5 6.5 1.5 6.4

1.5 3.4 5.9 1.5 6.7 1.5 6.2

SN54ABT2952A SN74ABT2952A

UNIT

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

From Output

Under Test

CL = 50 pF

(see Note A)

SN54ABT2952A, SN74ABT2952A

OCTAL BUS TRANSCEIVERS AND REGISTERS

SCBS203D – AUGUST 1992 – REVISED JANUARY 1998

PARAMETER MEASUREMENT INFORMATION

7 V

500 Ω

500 Ω

S1

Open

GND

TEST S1

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

WITH 3-STATE OUTPUTS

Open

7 V

Open

LOAD CIRCUIT

t

w

Input

Input

Output

Output

INVERTING AND NONINVERTING OUTPUTS

1.5 V 1.5 V

VOLTAGE WAVEFORMS

PULSE DURATION

1.5 V 1.5 V

t

PLH

1.5 V

t

PHL

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

t

PHL

1.5 V

t

PLH

1.5 V1.5 V

3 V

0 V

3 V

0 V

V

V

V

V

OH

OL

OH

OL

Timing Input

Data Input

Output

Control

Output

Waveform 1

S1 at 7 V

(see Note B)

Output

Waveform 2

S1 at Open

(see Note B)

1.5 V

t

su

1.5 V 1.5 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

1.5 V

t

PZL

t

PLZ

1.5 V

t

t

PZH

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

PHZ

1.5 V

VOLTAGE WAVEFORMS

t

h

1.5 V

VOL + 0.3 V

VOH – 0.3 V

3 V

0 V

3 V

0 V

3 V

0 V

3.5 V

V

OL

V

OH

≈ 0 V

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.

Figure 1. Load Circuit and Voltage Waveforms

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7

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Copyright  1998, Texas Instruments Incorporated