SN54ABT2952A, SN74ABT2952A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS203D – AUGUST 1992 – REVISED JANUARY 1998
D
State-of-the-Art
EPIC-ΙΙB
BiCMOS Design
Significantly Reduces Power Dissipation
D
Two 8-Bit Back-to-Back Registers Store
Data Flowing in Both Directions
D
Noninverting Outputs
D
T ypical V
(Output Ground Bounce) < 1 V
OLP
at VCC = 5 V, TA = 25°C
D
Latch-Up Performance Exceeds 500 mA Per
JESD 17
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK),
Ceramic Flat (W) Package, and Plastic (NT)
and Ceramic (JT) DIPs
description
The ’ABT2952A transceivers consist of two 8-bit
back-to-back registers that store data flowing in
both directions between two bidirectional buses.
Data on the A or B bus is stored in the registers on
the low-to-high transition of the clock (CLKAB or
CLKBA) input provided that the clock-enable
(CLKENAB
output-enable (OEAB or OEBA) input low
accesses the data on either port.
T o ensure the high-impedance state during power
up or power down, OE should be tied to V
through a pullup resistor; the minimum value of
the resistor is determined by the current-sinking
capability of the driver.
or CLKENBA) input is low. Taking the
CC
SN54ABT2952A . . . JT OR W PACKAGE
SN74ABT2952A . . . DB, DW, PW, OR NT PACKAGE
OEAB
CLKAB
CLKENAB
SN54ABT2952A . . . FK PACKAGE
B5
B4
B3
NC
B2
B1
OEAB
NC – No internal connection
(TOP VIEW)
B8
1
B7
2
B6
3
B5
4
B4
5
B3
6
B2
7
B1
8
9
10
11
GND
12
(TOP VIEW)
B7
B8
B6
3212827
426
5
6
7
8
9
10
11
12 13 14 15 16 17 18
GND
CLKAB
CLKENAB
24
23
22
21
20
19
18
17
16
15
14
13
CC
V
NC
NC
CLKENBA
V
CC
A8
A7
A6
A5
A4
A3
A2
A1
OEBA
CLKBA
CLKENBA
A8
A7
A6
25
A5
24
A4
23
NC
22
A3
21
A2
20
A1
19
OEBA
CLKBA
The SN54ABT2952A is characterized for
operation over the full military temperature range
of –55°C to 125°C. The SN74ABT2952A is
characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1998, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1
SN54ABT2952A, SN74ABT2952A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS203D – AUGUST 1992 – REVISED JANUARY 1998
logic symbol
FUNCTION TABLE
INPUTS
CLKENAB CLKAB OEAB A
H X L X B
X H or L L X B
L ↑ LL L
L ↑ LH H
X X H X Z
†
A-to-B data flow is shown; B-to-A data flow is similar,
but uses CLKENBA
‡
Level of B before the indicated steady-state input
conditions were established
, CLKBA, and OEBA.
†
OUTPUT
B
‡
0
‡
0
§
OEBA
CLKENBA
CLKBA
OEAB
CLKENAB
CLKAB
A1
A2
A3
A4
A5
A6
A7
A8
15
13
14
9
11
10
16
17
18
19
20
21
22
23
EN3
G1
1 C5
EN4
G2
2 C6
31
8
5D
16D
4
B1
7
B2
6
B3
5
B4
4
B5
3
B6
2
B7
1
B8
§
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DB, DW, JT, NT, PW, and W packages.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
SN54ABT2952A, SN74ABT2952A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS203D – AUGUST 1992 – REVISED JANUARY 1998
CLKENAB
CLKAB
OEAB
CLKENBA
CLKBA
OEBA
A1
11
10
9
13
14
15
16
C1
1D
8
B1
Pin numbers shown are for the DB, DW, JT, NT, PW, and W packages.
C1
1D
To Seven Other Channels
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3