SN54ALS174, SN54ALS175, SN54AS174, SN54AS175A
SN74ALS174, SN74ALS175, SN74AS174, SN74AS175B
HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
SDAS207C – APRIL 1982 – REVISED OCTOBER 1995
Copyright 1995, Texas Instruments Incorporated
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
• ′ALS174 and ′AS174 Contain Six Flip-Flops
With Single-Rail Outputs
• ′ALS175, SN54AS175A, and SN74AS175B
Contain Four Flip-Flops With Double-Rail
Outputs
• Buffered Clock and Direct-Clear Inputs
• Applications Include:
– Buffer/Storage Registers
– Shift Registers
– Pattern Generators
• Fully Buffered Outputs for Maximum
Isolation From External Disturbances
(′AS Only)
• Package Options Include Plastic
Small-Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
description
These positive-edge-triggered flip-flops utilize
TTL circuitry to implement D-type flip-flop logic. All
have a direct-clear (CLR
) input, and the ′ALS175,
SN54AS175A, and SN74AS175B feature
complementary outputs from each flip-flop.
Information at the data (D) inputs meeting the
setup-time requirements is transferred to the
outputs on the positive-going edge of the clock
pulse. Clock triggering occurs at a particular
voltage level and is not directly related to the
transition time of the positive-going pulse. When
the clock (CLK) input is at either the high or low
level, the D-input signal has no effect at the output.
These circuits are fully compatible for use with
most TTL circuits.
The SN54ALS174, SN54ALS175, SN54AS174,
and SN54AS175A are characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74ALS174, SN74ALS175,
SN74AS174, and SN74AS175B are
characterized for operation from 0°C to 70°C.
SN54ALS175, SN54AS175A ...J PACKAGE
SN74ALS175, SN74AS175B ...D OR N PACKAGE
(TOP VIEW)
SN54ALS174, SN54AS174 ...J PACKAGE
SN74ALS174, SN74AS174 ...D OR N PACKAGE
(TOP VIEW)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
6D
5D
NC
5Q
4D
1D
2D
NC
2Q
3D
SN54ALS174, SN54AS174 . . . FK PACKAGE
(TOP VIEW)
1Q
CLR
NC
CLK
4Q
6Q
3Q
GND
NC
NC – No internal connection
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLR
1Q
1D
2D
2Q
3D
3Q
GND
V
CC
6Q
6D
5D
5Q
4D
4Q
CLK
3212019
910111213
4
5
6
7
8
18
17
16
15
14
4Q
4D
NC
3D
3Q
1Q
1D
NC
2D
2Q
SN54ALS175A, SN54AS175A . . . FK PACKAGE
(TOP VIEW)
1Q
CLR
NC
CLK
3Q
4Q
2Q
GND
NC
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLR
1Q
1Q
1D
2D
2Q
2Q
GND
V
CC
4Q
4Q
4D
3D
3Q
3Q
CLK
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN54ALS174, SN54ALS175, SN54AS174, SN54AS175A
SN74ALS174, SN74ALS175, SN74AS174, SN74AS175B
HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
SDAS207C – APRIL 1982 – REVISED OCTOBER 1995
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUTS
CLR CLK D Q Q
†
L X X L H
H ↑ HHL
H↑LLH
HLXQ
0
Q
0
†
′ALS175, SN54AS175A, and SN74AS175B only
logic symbols
‡
R
1
9
CLK
C1
1D
3
1D
4
2D
6
3D
11
4D
13
5D
14
6D
1Q
2
2Q
5
3Q
7
4Q
10
5Q
12
6Q
15
CLR
CLR
1Q
2Q
R
1
9
CLK
C1
1D
4
1D
3
1Q
2
5
2D
6
2Q
7
12
3D
11
3Q
10
13
4D
14
4Q
15
3Q
4Q
′ALS174, ′AS174
′ALS175, SN54AS175A, and SN74AS175B
‡
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
logic diagrams (positive logic)
1D
C1
R
To Five Other Channels
1
9
3
2
CLR
CLK
1D
1Q
1Q
9
1
C1
1D
CLR
CLK
1D
R
1Q
To Three Other Channels
4
2
3
′ALS174, ′AS174 ′ALS175, SN54AS175A, and SN74AS175B
Pin numbers shown are for the D, J, and N packages.
SN54ALS174, SN54ALS175, SN54AS174, SN54AS175A
SN74ALS174, SN74ALS175, SN74AS174, SN74AS175B
HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
SDAS207C – APRIL 1982 – REVISED OCTOBER 1995
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage, V
CC
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, V
I
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
A
: SN54ALS174, SN54ALS175 –55°C to 125°C. . . . . . . . . . . . . . . .
SN74ALS174, SN74ALS175 0°C to 70°C. . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54ALS174
SN54ALS175
SN74ALS174
SN74ALS175
UNIT
MIN NOM MAX MIN NOM MAX
V
CC
Supply voltage 4.5 5 5.5 4.5 5 5.5 V
V
IH
High-level input voltage 2 2 V
V
IL
Low-level input voltage 0.8 0.8 V
I
OH
High-level output current –0.4 –0.4 mA
I
OL
Low-level output current 4 8 mA
f
clock
Clock frequency 0 40 0 50 MHz
CLR low 15 10
t
w
Pulse duration
CLK high
12.5 10
ns
CLK low 12.5 10
Data 15 10
t
su
S
etup time before
CLK↑
CLR inactive 8 6
ns
t
h
Hold time, data after CLK↑ 0 0 ns
T
A
Operating free-air temperature –55 125 0 70 °C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS
SN54ALS174
SN54ALS175
SN74ALS174
SN74ALS175
UNIT
MIN TYP‡MAX MIN TYP‡MAX
V
IK
VCC = 4.5 V, II = –18 mA –1.5 –1.5 V
V
OH
VCC = 4.5 V to 5.5 V, IOH = –0.4 mA VCC –2 VCC –2 V
IOL = 4 mA 0.25 0.4 0.25 0.4
VOLV
CC
=
4.5 V
IOL = 8 mA 0.35 0.5
V
I
I
VCC = 5.5 V, VI = 7 V 0.1 0.1 mA
I
IH
VCC = 5.5 V, VI = 2.7 V 20 20 µA
All others
–0.1 –0.1
I
IL
CLK
V
CC
= 5.5 V,
V
I
= 0.4
V
–0.15
mA
I
O
§
VCC = 5.5 V, VO = 2.25 V –20 –112 –30 –112 mA
′ALS174
11 19 11 19
I
CC
′ALS175
V
CC
= 5.5 V,
See Note 1
8 14 9 14
mA
‡
All typical values are at VCC = 5 V, TA = 25°C.
§
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
NOTE 1: ICC is measured with D inputs and CLR
grounded, and CLK at 4.5 V .
SN54ALS174, SN54ALS175, SN54AS174, SN54AS175A
SN74ALS174, SN74ALS175, SN74AS174, SN74AS175B
HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
SDAS207C – APRIL 1982 – REVISED OCTOBER 1995
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics (see Figure 1)
FROM
TO
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500 Ω
,
TA = MIN to MAX
†
PARAMETER
(INPUT) (OUTPUT)
SN54ALS174
SN54ALS175
SN74ALS174
SN74ALS175
UNIT
MIN MAX MIN MAX
f
max
40 50 MHz
t
PLH
Any Q (′ALS175
)
3 20 5 18
t
PHL
CLR
yQ( )
Any Q
5 30 8 23
ns
t
PLH
Any Q
3 20 3 15
t
PHL
CLK
y
(or Q, ′ALS175)
5 24 5 17
ns
†
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
‡
Supply voltage, V
CC
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, V
I
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
A
: SN54AS174, SN54AS175A –55°C to 125°C. . . . . . . . . . . . . . . .
SN74AS174, SN74AS175B 0°C to 70°C. . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54AS174
SN54AS175A
SN74AS174
SN74AS175B
UNIT
MIN NOM MAX MIN NOM MAX
V
CC
Supply voltage 4.5 5 5.5 4.5 5 5.5 V
V
IH
High-level input voltage 2 2 V
V
IL
Low-level input voltage 0.8 0.8 V
I
OH
High-level output current –2 –2 mA
I
OL
Low-level output current 20 20 mA
f
clock
* Clock frequency 0 100 0 100 MHz
CLR low 5.5 5
CLK high 4 4
tw* Pulse duration
′AS174 6 6
ns
CLK low
SN54AS175A,
SN74AS175B
5 5
′AS174 4 4
tsu*
Setup time before
CLK↑
Data
SN54AS175A,
SN74AS175B
3 3
ns
CLR inactive 6 6
th* Hold time, data after CLK↑ 1 1 ns
T
A
Operating free-air temperature –55 125 0 70 °C
* On products compliant to MIL-STD-883, Class B, this parameter is based on characterization data but is not production tested.
SN54ALS174, SN54ALS175, SN54AS174, SN54AS175A
SN74ALS174, SN74ALS175, SN74AS174, SN74AS175B
HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
SDAS207C – APRIL 1982 – REVISED OCTOBER 1995
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS
SN54AS174
SN54AS175A
SN74AS174
SN74AS175B
UNIT
MIN TYP†MAX MIN TYP†MAX
V
IK
VCC = 4.5 V, II = –18 mA –1.2 –1.2 V
V
OH
VCC = 4.5 V to
5.5 V ,
IOH = –2 mA VCC –2 VCC –2 V
V
OL
VCC = 4.5 V, IOL = 20 mA 0.35 0.5 0.35 0.5 V
I
I
VCC = 5.5 V, VI = 7 V 0.1 0.1 mA
I
IH
VCC = 5.5 V, VI = 2.7 V 20 20 µA
I
IL
VCC = 5.5 V, VI = 0.4 V –0.5 –0.5 mA
I
O
‡
VCC = 5.5 V, VO = 2.25 V –30 –112 –30 –112 mA
′AS174
30 45 30 45
I
CC
SN54AS175A, SN74AS175B
V
CC
= 5.5 V,
See Note 2
22.5 34 22.5 34
mA
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
NOTE 2: ICC is measured with D inputs, CLR
, and CLK grounded.
switching characteristics (see Figure 1)
PARAMETER
FROM
(
INPUT
)
TO
(
OUTPUT
)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500 Ω
,
TA = MIN to MAX
§
UNIT
(INPUT)
(OUTPUT)
SN54AS174 SN74AS174
MIN MAX MIN MAX
f
max
* 100 100 MHz
t
PHL
CLR
Any Q 5 15 5 14 ns
t
PLH
3.5 9.5 3.5 8
t
PHL
CLK
Any Q
4.5 11.5 4.5 10
ns
* On products compliant to MIL-STD-883, Class B, these parameters are based on characterization data but are not production tested.
§
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
switching characteristics (see Figure 1)
PARAMETER
FROM
(
INPUT
)
TO
(
OUTPUT
)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500 Ω
,
TA = MIN to MAX
§
UNIT
(INPUT)
(OUTPUT)
SN54AS175A SN74AS175B
MIN MAX MIN MAX
f
max
* 100 100 MHz
t
PLH
4 10 4 9
t
PHL
CLR
A
ny Q or
Q
4.5 15 4.5 13
ns
t
PLH
4 8.5 3 7.5
t
PHL
CLK
A
ny Q or
Q
4 11 3 10
ns
* On products compliant to MIL-STD-883, Class B, this parameter is based on characterization data but is not production tested.
§
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
SN54ALS174, SN54ALS175, SN54AS174, SN54AS175A
SN74ALS174, SN74ALS175, SN74AS174, SN74AS175B
HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
SDAS207C – APRIL 1982 – REVISED OCTOBER 1995
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
t
PHZ
t
PLZ
t
PHL
t
PLH
0.3 V
t
PZL
t
PZH
t
PLH
t
PHL
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
From Output
Under Test
Test
Point
R1
S1
C
L
(see Note A)
7 V
1.3 V
1.3 V1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
t
h
t
su
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing
Input
Data
Input
1.3 V 1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
High-Level
Pulse
Low-Level
Pulse
t
w
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
Out-of-Phase
Output
(see Note C)
1.3 V 1.3 V
1.3 V1.3 V
1.3 V 1.3 V
1.3 V1.3 V
1.3 V
1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
V
OL
V
OH
V
OH
V
OL
Output
Control
(low-level
enabling)
Waveform 1
S1 Closed
(see Note B)
Waveform 2
S1 Open
(see Note B)
[
0 V
V
OH
V
OL
[
3.5 V
In-Phase
Output
0.3 V
1.3 V 1.3 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
R2
V
CC
R
L
Test
Point
From Output
Under Test
C
L
(see Note A)
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
From Output
Under Test
Test
Point
C
L
(see Note A)
R
L
RL = R1 = R2
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICA TIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
Loading...