Texas Instruments SN54AS161J, SN74ALS163BD, SN74ALS163BDR, SN74ALS163BN, SN74ALS163BN3 Datasheet
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SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276 – DECEMBER 1994
• Internal Look-Ahead Circuitry for Fast
Counting
• Carry Output for n-Bit Cascading
• Synchronous Counting
• Synchronously Programmable
• Package Options Include Plastic
Small-Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
description
These synchronous, presettable, 4-bit decade
and binary counters feature an internal carry
look-ahead circuitry for application in high-speed
counting designs. The SN54ALS162B is a 4-bit
decade counter. The ′ALS161B, ′ALS163B,
′AS161, and ′AS163 are 4-bit binary counters.
Synchronous operation is provided by having all
flip-flops clocked simultaneously so that the
outputs change coincidentally with each other
when instructed by the count-enable (ENP, ENT)
inputs and internal gating. This mode of operation
eliminates the output counting spikes normally
associated with asynchronous (ripple-clock)
counters. A buffered clock (CLK) input triggers the
four flip-flops on the rising (positive-going) edge of
the clock input waveform.
These counters are fully programmable; they may
be preset to any number between 0 and 9 or 15.
Because presetting is synchronous, setting up a
low level at the load (LOAD
counter and causes the outputs to agree with the
setup data after the next clock pulse, regardless of
the levels of the enable inputs.
) input disables the
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161,
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161,
SN54AS163 ...J PACKAGE
SN74ALS161B, SN74ALS163B, SN74AS161,
SN74AS163 ...D OR N PACKAGE
SN54AS163 . . . FK PACKAGE
A
B
NC
C
D
NC – No internal connection
(TOP VIEW)
CLR
1
CLK
2
A
3
B
4
C
5
D
6
ENP
7
GND
8
(TOP VIEW)
CLK
3212019
4
5
6
7
8
910111213
ENP
CLR
GND
NC
NC
16
15
14
13
12
11
10
9
CC
V
LOAD
V
CC
RCO
Q
A
Q
B
Q
C
Q
D
ENT
LOAD
RCO
18
17
16
15
14
ENT
Q
Q
NC
Q
Q
A
B
C
D
The clear function for the ′ALS161B and ′AS161 is asynchronous. A low level at the clear (CLR
four of the flip-flop outputs low, regardless of the levels of the CLK, LOAD
for the SN54ALS162B, ′ALS163B, and ′AS163 is synchronous, and a low level at CLR
, or enable inputs. The clear function
sets all four of the flip-flop
) input sets all
outputs low after the next clock pulse, regardless of the levels of the enable inputs. This synchronous clear
allows the count length to be modified easily by decoding the Q outputs for the maximum count desired. The
active-low output of the gate used for decoding is connected to CLR
to synchronously clear the counter to
0000 (LLLL).
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without
additional gating. ENP and ENT inputs and a ripple-carry (RCO) output are instrumental in accomplishing this
function. Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. RCO, thus enabled,
produces a high-level pulse while the count is maximum (9 or 15 with Q
high). The high-level overflow
A
ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed,
regardless of the level of CLK.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1994, Texas Instruments Incorporated
1
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276 – DECEMBER 1994
description (continued)
These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that
modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of
the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the
stable setup and hold times.
The SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, and SN54AS163 are characterized for
operation over the full military temperature range of – 55°C to 125°C. The SN74ALS161B, SN74ALS163B,
SN74AS161, and SN74AS163 are characterized for operation from 0°C to 70°C.
logic symbols
′ALS161B AND ′AS161 BINARY COUNTERS
1
CLR
ENT
ENP
CLK
9
10
7
2
3
A
4
B
5
C
6
D
LOAD
†
WITH DIRECT CLEAR
CTRDIV16
CT=0
M1
M2
G3
G4
1, 5D
3CT=15
C5/2,3,4+
[1]
[2]
[4]
[8]
LOAD
CLR
ENT
ENP
CLK
′ALS163B AND ′AS163 BINARY COUNTERS
WITH SYNCHRONOUS CLEAR
1
CLR
ENT
ENP
CLK
9
10
7
2
3
A
4
B
5
C
6
D
15
14
13
12
11
15
RCO
14
Q
A
13
Q
B
12
Q
C
11
Q
D
SN54ALS162B DECADE COUNTER
WITH SYNCHRONOUS CLEAR
1
9
10
7
2
3
A
4
B
5
C
6
D
CTRDIV10
5CT=0
M1
M2
G3
G4
C5/2,3,4+
1, 5D
LOAD
3CT=9
[1]
[2]
[4]
[8]
CTRDIV16
5CT=0
M1
M2
G3
G4
C5/2,3,4+
1, 5D
RCO
Q
A
Q
B
Q
C
Q
D
3CT=15
[1]
[2]
[4]
[8]
15
14
13
12
11
RCO
Q
A
Q
B
Q
C
Q
D
†
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
logic diagram (positive logic)
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276 – DECEMBER 1994
LOAD
ENT
ENP
CLR
CLK
9
10
7
1
2
3
A
SN54ALS162B
1D
1D
C1
C1
15
14
13
RCO
Q
A
Q
B
4
B
5
C
6
D
Pin numbers shown are for the J package.
12
C1
1D
C1
1D
Q
C
11
Q
D
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276 – DECEMBER 1994
logic diagram (positive logic)
CLR
LOAD
ENT
ENP
CLK
1
9
10
7
2
3
A
′ALS163B and ′AS163
1D
1D
C1
C1
15
14
13
RCO
Q
A
Q
B
4
B
5
C
6
D
Pin numbers shown are for the D, J, and N packages.
′ALS161B and ′AS161 synchronous binary counters are similar; however, CLR
is asynchronous.
1D
1D
C1
C1
12
11
Q
C
Q
D
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
typical clear, preset, count, and inhibit sequences
SN54ALS162B
The following sequence is illustrated below:
1. Clear outputs to zero (SN54ALS162B is synchronous)
2. Preset to BCD 7
3. Count to 8, 9, 0, 1, 2, and 3
4. Inhibit
CLR
LOAD
A
SDAS276 – DECEMBER 1994
Data
Inputs
Data
Outputs
CLK
ENP
ENT
Q
Q
Q
Q
RCO
B
C
D
A
B
C
D
90123
Count Inhibit
Sync
Clear
78
Preset
Async
Clear
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
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