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SN54ALVTH16373, SN74ALVTH16373
2.5-V/3.3-V 16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCES067F – JUNE 1996 – REVISED JANUARY 1999
D
State-of-the-Art Advanced BiCMOS
Technology (ABT)
Widebus
Design for
2.5-V and 3.3-V Operation and Low Static
Power Dissipation
D
Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 2.3-V to
3.6-V V
D
Typical V
< 0.8 V at V
D
High Drive (–24/24 mA at 2.5-V and
–32/64 mA at 3.3-V V
D
Power Off Disables Outputs, Permitting
)
CC
(Output Ground Bounce)
OLP
= 3.3 V, TA = 25°C
CC
)
CC
Live Insertion
D
High-Impedance State During Power Up
and Power Down Prevents Driver Conflict
D
Uses Bus Hold on Data Inputs in Place of
External Pullup/Pulldown Resistors to
Prevent the Bus From Floating
D
Auto3-State Eliminates Bus Current
Loading When Output Exceeds V
D
Latch-Up Performance Exceeds 250 mA Per
CC
JESD 17
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model; and Exceeds 1000 V
Using Charged-Device Model, Robotic
Method
D
Flow-Through Architecture Facilitates
Printed Circuit Board Layout
D
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D
Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink
Small-Outline (DGG), Thin Very
Small-Outline (DGV) Packages, and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
+ 0.5 V
SN54ALVTH16373.. . WD PACKAGE
SN74ALVTH16373... DGG, DGV, OR DL PACKAGE
1OE
1Q1
1Q2
GND
1Q3
1Q4
V
CC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
V
CC
2Q5
2Q6
GND
2Q7
2Q8
2OE
(TOP VIEW)
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
1LE
1D1
1D2
GND
1D3
1D4
V
CC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
V
CC
2D5
2D6
GND
2D7
2D8
2LE
description
The ’AL VTH16373 devices are 16-bit transparent D-type latches with 3-state outputs designed for 2.5-V or 3.3-V
V
operation, but with the capability to provide a TTL interface to a 5-V system environment. These devices
CC
are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working
registers.
These devices can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high,
the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up
at the D inputs.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1999, Texas Instruments Incorporated
1
SN54ALVTH16373, SN74ALVTH16373
2.5-V/3.3-V 16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCES067F – JUNE 1996 – REVISED JANUARY 1999
description (continued)
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly . The high-impedance state and the increased drive provide the capability to drive bus
lines without interface or pullup components.
OE
does not affect internal operations of the latch. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
When V
However, to ensure the high-impedance state above 1.2 V, OE
is between 0 and 1.2 V , the device is in the high-impedance state during power up or power down.
CC
should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ALVTH16373 is characterized for operation over the full military temperature range of –55°C to
125°C. The SN74ALVTH16373 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each 8-bit section)
INPUTS
OE
LE D
L H H H
L HL L
LLX Q
HXX Z
OUTPUT
Q
0
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UNIT
I
mA
logic diagram (positive logic)
SN54ALVTH16373, SN74ALVTH16373
2.5-V/3.3-V 16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCES067F – JUNE 1996 – REVISED JANUARY 1999
1OE
1LE
1D1
1
48
47
C1
1D
To Seven Other Channels
1Q1
2OE
2LE
2D1
24
25
36
C1
1D
To Seven Other Channels
132
2Q1
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, V
Voltage range applied to any output in
or power-off state, V
Voltage range applied to any output in the high state, V
Output current in the low state, I
Output current in the high state, I
Input clamp current, I
Output clamp current, I
Package thermal impedance, θ
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
the high-impedance
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
: SN54ALVTH16373 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . .
O
SN74ALVTH16373 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
: SN54ALVTH16373 –48 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
SN74ALVTH16373 –64 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(V
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
I
(V
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
O
(see Note 2): DGG package 89°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DGV package 93°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DL package 94°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
†
recommended operating conditions, VCC = 2.5 V ± 0.2 V (see Note 3)
SN54ALVTH16373 SN74ALVTH16373
MIN TYP MAX MIN TYP MAX
V
CC
V
IH
V
IL
V
I
I
OH
OL
∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V
∆t/∆V
T
A
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
Supply voltage 2.3 2.7 2.3 2.7 V
High-level input voltage 1.7 1.7 V
Low-level input voltage 0.7 0.7 V
Input voltage 0 V
High-level output current –6 –8 mA
Low-level output current 6 8
Low-level output current; current duty cycle ≤ 50%; f ≥ 1 kHz 18 24
Power-up ramp rate 200 200 µs/V
CC
Operating free-air temperature –55 125 –40 85 °C
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CC
5.5 0 V
CC
5.5 V
3
SN54ALVTH16373, SN74ALVTH16373
UNIT
I
mA
2.5-V/3.3-V 16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCES067F – JUNE 1996 – REVISED JANUARY 1999
recommended operating conditions, VCC = 3.3 V ± 0.3 V (see Note 3)
SN54ALVTH16373 SN74ALVTH16373
MIN TYP MAX MIN TYP MAX
V
CC
V
IH
V
IL
V
I
I
OH
OL
∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V
∆t/∆V
T
A
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 3 3.6 3 3.6 V
High-level input voltage 2 2 V
Low-level input voltage 0.8 0.8 V
Input voltage 0 V
High-level output current –24 –32 mA
Low-level output current 24 32
Low-level output current; current duty cycle ≤ 50%; f ≥ 1 kHz 48 64
Power-up ramp rate 200 200 µs/V
CC
Operating free-air temperature –55 125 –40 85 °C
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
CC
5.5 0 V
CC
5.5 V
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER
TEST CONDITIONS
UNIT
V
V
V
V
Control inputs
I
V
V
5
5µA
I
V
V
5–5µA
V
CC
SN54ALVTH16373, SN74ALVTH16373
2.5-V/3.3-V 16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCES067F – JUNE 1996 – REVISED JANUARY 1999
electrical characteristics over recommended operating free-air temperature range,
= 2.5 V ± 0.2 V (unless otherwise noted)
V
CC
SN54ALVTH16373 SN74ALVTH16373
MIN TYP†MAX MIN TYP†MAX
V
IK
V
OH
V
OL
I
I
Data inputs VCC = 2.7 V
I
off
‡
I
BHL
§
I
BHH
¶
I
BHLO
#
I
BHHO
||
I
EX
I
OZ(PU/PD)
OZH
OZL
I
CC
C
i
C
o
†
All typical values are at VCC = 2.5 V, TA = 25°C.
‡
The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. I
then raising it to VIL max.
§
The bus-hold circuit can source at least the minimum high sustaining current at VIH min. I
then lowering it to VIH min.
¶
An external driver must source at least I
#
An external driver must sink at least I
||
Current into an output in the high state when VO > V
k
High-impedance state during power up or power down
k
VCC = 2.3 V, II = –18 mA –1.2 –1.2 V
VCC = 2.3 V to 2.7 V, IOH = –100 µA VCC–0.2 VCC–0.2
= 2.3
CC
VCC = 2.3 V to 2.7 V, IOL = 100 µA 0.2 0.2
= 2.3
CC
VCC = 2.7 V, VI = VCC or GND ±1 ±1
p
VCC = 0 or 2.7 V, VI = 5.5 V 10 10
VCC = 0, VI or VO = 0 to 4.5 V ±100 µA
VCC = 2.3 V, VI = 0.7 V 115 115 µA
VCC = 2.3 V, VI = 1.7 V –10 –10 µA
VCC = 2.7 V, VI = 0 to V
VCC = 2.7 V, VI = 0 to V
VCC = 2.3 V, VO = 5.5 V 125 125 µA
VCC ≤ 1.2 V, VO = 0.5 V to VCC,
VI = GND or VCC, OE
= 2.7
CC
= 2.7
CC
=
= 2.7 V,
IO = 0,
VI = VCC or GND
VCC = 2.5 V, VI = 2.5 V or 0 3.5 3.5 pF
VCC = 2.5 V, VO = 2.5 V or 0 6 6 pF
BHLO
to switch this node from high to low.
BHHO
IOH = –6 mA 1.8
IOH = –8 mA 1.8
IOL = 6 mA 0.4
IOL = 8 mA 0.4
IOL = 18 mA 0.5
IOL = 24 mA 0.5
VI = 5.5 V 10 10
VI = V
CC
VI = 0 –5 –5
CC
CC
= don’t care
VO = 2.3 V,
VI = 0.7 V or 1.7 V
VO = 0.5 V,
VI = 0.7 V or 1.7 V
Outputs high 0.04 0.1 0.04 0.1
Outputs low 2.3 4.5 2.3 4.5
Outputs disabled 0.04 0.1 0.04 0.1
to switch this node from low to high.
CC
300 300 µA
–300 –300 µA
should be measured after lowering VIN to GND and
BHL
should be measured after raising VIN to VCC and
BHH
1 1
±100 ±100 µA
–
V
V
µA
mA
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN54ALVTH16373, SN74ALVTH16373
PARAMETER
TEST CONDITIONS
UNIT
V
V
V
V
Control inputs
I
V
V
5
5µA
I
V
3.6 V
5–5µA
V
CC
2.5-V/3.3-V 16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCES067F – JUNE 1996 – REVISED JANUARY 1999
electrical characteristics over recommended operating free-air temperature range,
= 3.3 V ± 0.3 V (unless otherwise noted)
V
CC
SN54ALVTH16373 SN74ALVTH16373
MIN TYP†MAX MIN TYP†MAX
V
IK
V
OH
OL
I
I
Data inputs VCC = 3.6 V
I
off
‡
I
BHL
§
I
BHH
¶
I
BHLO
#
I
BHHO
||
I
EX
I
OZ(PU/PD)
OZH
OZL
I
CC
∆I
CC
C
i
C
o
†
All typical values are at VCC = 3.3 V, TA = 25°C.
‡
The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. I
then raising it to VIL max.
§
The bus-hold circuit can source at least the minimum high sustaining current at VIH min. I
then lowering it to VIH min.
¶
An external driver must source at least I
#
An external driver must sink at least I
||
Current into an output in the high state when VO > V
k
High-impedance state during power up or power down
h
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
k
h
VCC = 3 V, II = –18 mA –1.2 –1.2 V
VCC = 3 V to 3.6 V, IOH = –100 µA VCC–0.2 VCC–0.2
= 3
CC
VCC = 3 V to 3.6 V, IOL = 100 µA 0.2 0.2
VCC = 3 V
VCC = 3.6 V, VI = VCC or GND ±1 ±1
p
VCC = 0 or 3.6 V, VI = 5.5 V 10 10
VCC = 0, VI or VO = 0 to 4.5 V ±100 µA
VCC = 3 V, VI = 0.8 V 75 75 µA
VCC = 3 V, VI = 2 V –75 –75 µA
VCC = 3.6 V, VI = 0 to V
VCC = 3.6 V, VI = 0 to V
VCC = 3 V, VO = 5.5 V 125 125 µA
VCC ≤ 1.2 V, VO = 0.5 V to VCC,
VI = GND or VCC, OE
= 3.6
CC
=
CC
=
= 3.6 V,
IO = 0,
VI = VCC or GND
VCC = 3 V to 3.6 V, One input at VCC – 0.6 V,
Other inputs at VCC or GND
VCC = 3.3 V, VI = 3.3 V or 0 3.5 3.5 pF
VCC = 3.3 V, VO = 3.3 V or 0 6 6 pF
BHLO
to switch this node from high to low.
BHHO
IOH = –24 mA 2
IOH = –32 mA 2
IOL = 16 mA 0.4
IOL = 24 mA 0.5
IOL = 32 mA 0.5
IOL = 48 mA 0.55
IOL = 64 mA 0.55
VI = 5.5 V 10 10
VI = V
CC
VI = 0 –5 –5
CC
CC
= don’t care
VO = 3 V,
VI = 0.8 V or 2 V
VO = 0.5 V,
VI = 0.8 V or 2 V
Outputs high 0.07 0.1 0.07 0.1
Outputs low 3.2 5.5 3.2 5
Outputs disabled 0.07 0.1 0.07 0.1
to switch this node from low to high.
CC
500 500 µA
–500 –500 µA
should be measured after lowering VIN to GND and
BHL
should be measured after raising VIN to VCC and
BHH
1 1
±100 ±100 µA
–
0.4 0.4 mA
V
µA
mA
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UNIT
t
Set
LE↓
ns
t
h
Hold time, data after LE↓
ns
UNIT
t
Set
LE↓
ns
t
h
Hold time, data after LE↓
ns
PARAMETER
UNIT
D
Q
ns
LE
Q
ns
OE
Q
ns
OE
Q
ns
PARAMETER
UNIT
D
Q
ns
LE
Q
ns
OE
Q
ns
OE
Q
ns
SN54ALVTH16373, SN74ALVTH16373
2.5-V/3.3-V 16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCES067F – JUNE 1996 – REVISED JANUARY 1999
timing requirements over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V
(unless otherwise noted) (see Figure 1)
SN54ALVTH16373 SN74ALVTH16373
MIN MAX MIN MAX
t
w
su
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V
(unless otherwise noted) (see Figure 2)
t
w
su
Pulse duration, LE high 1.5 1.5 ns
up time, data before
Pulse duration, LE high 1.5 1.5 ns
up time, data before
Data high 1.1 1
Data low 1.6 1.5
Data high 1 0.9
Data low 1.6 1.5
SN54ALVTH16373 SN74ALVTH16373
MIN MAX MIN MAX
Data high 1.5 1.4
Data low 1 0.9
Data high 1 0.9
Data low 1.5 1.4
switching characteristics over recommended operating free-air temperature range, CL = 30 pF,
= 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
V
CC
SN54ALVTH16373 SN74ALVTH16373
MIN MAX MIN MAX
1 3.4 1 3.3
1 4.3 1 4.2
1.4 3.9 1.5 3.8
1.4 4.6 1.5 4.5
1.7 4.4 1.8 4.3
1.4 4.1 1.5 4
1.4 4.7 1.5 4.6
1 3.7 1 3.6
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
FROM TO
(INPUT) (OUTPUT)
switching characteristics over recommended operating free-air temperature range, CL = 50 pF,
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 2)
V
CC
SN54ALVTH16373 SN74ALVTH16373
MIN MAX MIN MAX
1 3.2 1 3.1
1 3.4 1 3.3
1 3.4 1 3.3
1 3.6 1 3.5
1.3 4.1 1.4 4
1 3.5 1 3.4
1.4 5 1.5 4.9
1.4 4.6 1.5 4.5
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
FROM TO
(INPUT) (OUTPUT)
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
SN54ALVTH16373, SN74ALVTH16373
2.5-V/3.3-V 16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCES067F – JUNE 1996 – REVISED JANUARY 1999
PARAMETER MEASUREMENT INFORMATION
V
= 2.5 V ± 0.2 V
CC
2 × V
CC
Open
GND
From Output
Under Test
CL = 30 pF
(see Note A)
500 Ω
500 Ω
S1
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open
2 × V
GND
CC
LOAD CIRCUIT
Timing
Input
t
Data
Input
Input
t
PLH
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
VCC/2
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2 VCC/2
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC/2
t
su
h
VCC/2
VCC/2 VCC/2
t
PHL
V
0 V
V
0 V
V
0 V
V
V
CC
CC
CC
OH
OL
Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
CC
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VCC/2
VCC/2
t
w
V
0 V
V
0 V
V
V
V
0 V
CC
CC
CC
OL
OH
VCC/2VCC/2
VCC/2VCC/2
t
PLZ
VOL + 0.15 V
t
PHZ
VOH – 0.15 V
Figure 1. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
From Output
Under Test
CL = 50 pF
(see Note A)
SN54ALVTH16373, SN74ALVTH16373
2.5-V/3.3-V 16-BIT TRANSPARENT D-TYPE LATCHES
SCES067F – JUNE 1996 – REVISED JANUARY 1999
PARAMETER MEASUREMENT INFORMATION
V
= 3.3 V ± 0.3 V
CC
6 V
500 Ω
500 Ω
S1
Open
GND
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
WITH 3-STATE OUTPUTS
Open
6 V
GND
LOAD CIRCUIT
Timing
Input
Data
Input
Input
Output
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform22 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V 1.5 V
VOLTAGE WAVEFORMS
1.5 V
t
su
t
h
t
PLH
1.5 V 1.5 V
t
PHL
3 V
0 V
3 V
0 V
3 V
0 V
V
V
OH
OL
Input
Output Control
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
t
w
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V 1.5 V
t
PZL
1.5 V
t
PZH
1.5 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
1.5 V
VOL + 0.3 V
VOH – 0.3 V
t
PLZ
t
PHZ
3 V
0 V
3 V
0 V
3 V
V
OL
V
OH
≈ 0 V
Figure 2. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
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