Texas Instruments SN54ALS86J, SN74ALS86D, SN74ALS86DR, SN74ALS86N, SN74ALS86N3 Datasheet
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SN54ALS86, SN54AS86A, SN74ALS86, SN74AS86A
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SDAS006B – APRIL 1982 – REVISED DECEMBER 1994
• Package Options Include Plastic
Small-Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
description
These devices contain four independent 2-input
exclusive-OR gates. They perform the Boolean
functions Y = A ⊕ B or Y = A
logic.
A common application is as a true/complement
element. If one of the inputs is low, the other input
is reproduced in true form at the output. If one of
the inputs is high, the signal on the other input is
reproduced inverted at the output.
The SN54ALS86 and SN54AS86A are
characterized for operation over the full military
temperature range of –55°C to 125°C. The
SN74ALS86 and SN74AS86A are characterized
for operation from 0°C to 70°C.
FUNCTION TABLE
(each gate)
INPUTS
A B
L L L
L HH
HLH
HHL
B + AB in positive
OUTPUT
Y
SN54ALS86, SN54AS86A ...J PACKAGE
SN74ALS86, SN74AS86A ...D OR N PACKAGE
SN54ALS86, SN54AS86A . . . FK PACKAGE
1Y
NC
2A
NC
2B
NC – No internal connection
(TOP VIEW)
1A
1
1B
2
1Y
3
2A
4
2B
5
2Y
6
GND
7
(TOP VIEW)
1B1ANC
3212019
4
5
6
7
8
910111213
2Y
NC
GND
14
13
12
11
10
V
CC
4B
4A
4Y
3B
3A
9
3Y
8
CC
V
4B
4A
18
NC
17
16
4Y
15
NC
14
3B
3Y
3A
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
†
1A
1B
2A
2B
3A
3B
4A
4B
1
2
4
5
9
10
12
13
= 1
3
1Y
6
2Y
8
3Y
11
4Y
Copyright 1994, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN54ALS86, SN54AS86A, SN74ALS86, SN74AS86A
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SDAS006B – APRIL 1982 – REVISED DECEMBER 1994
exclusive-OR logic
An exclusive-OR gate has many applications, some of which can be represented better by alternative logic
symbols.
EXCLUSIVE-OR
= 1
These are five equivalent exclusive-OR symbols valid for an ′ALS86 or ′AS86A gate in positive logic. Negation
may be shown at any two ports.
LOGIC-IDENTITY ELEMENT EVEN-PARITY ELEMENT ODD-PARITY ELEMENT
= 2k 2k + 1
The output is active (low) if
all inputs are at the same
logic level (i.e., A = B).
The output is active (low) if
an even number of inputs
(i.e., 0 or 2) are active.
The output is active (high) if
an odd number of inputs
(i.e., only 1 of the 2) are
active.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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