Texas Instruments JM38510-37101BCA, JM38510-37101B2A, SN54ALS74AJ, SN54AS74AJ, SN74ALS74AD Datasheet
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SN54ALS74A, SN54AS74A, SN74ALS74A, SN74AS74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SDAS143C – APRIL 1982 – REVISED AUGUST 1995
Copyright 1995, Texas Instruments Incorporated
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
• Package Options Include Plastic
Small-Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
TYPE
TYPICAL MAXIMUM
CLOCK FREQUENCY
(CL = 50 pF)
(MHz)
TYPICAL POWER
DISSIPATION
PER FLIP-FLOP
(mW)
′ALS74A 50 6
′AS74A 134 26
description
These devices contain two independent
positive-edge-triggered D-type flip-flops. A low
level at the preset (PRE
) or clear (CLR) inputs sets
or resets the outputs regardless of the levels of the
other inputs. When PRE
and CLR are inactive
(high), data at the data (D) input meeting the
setup-time requirements are transferred to the
outputs on the positive-going edge of the clock
(CLK) pulse. Clock triggering occurs at a voltage
level and is not directly related to the rise time of
CLK. Following the hold-time interval, data at the
D input can be changed without affecting the
levels at the outputs.
The SN54ALS74A and SN54AS74A are
characterized for operation over the full military
temperature range of –55°C to 125°C. The
SN74ALS74A and SN74AS74A are characterized
for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
OUTPUTS
PRE CLR CLK D Q Q
L H X X H L
H LXXLH
LLXXH
†
H
†
HH↑HHL
HH↑LLH
HHLXQ
0
Q
0
†
The output levels in this configuration are not
specified to meet the minimum levels for VOH if the
lows at PRE
and CLR are near VIL maximum.
Furthermore, this configuration is nonstable; that
is, it does not persist when PRE
or CLR returns to
its inactive (high) level.
SN54ALS74A, SN54AS74A ...J PACKAGE
SN74ALS74A, SN74AS74A ...D OR N PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1CLR
1D
1CLK
1PRE
1Q
1Q
GND
V
CC
2CLR
2D
2CLK
2PRE
2Q
2Q
SN54ALS74A, SN54AS74A . . . FK PACKAGE
(TOP VIEW)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
2D
NC
2CLK
NC
2PRE
1CLK
NC
1PRE
NC
1Q
1D
1CLR
NC
2Q
2Q
V
2CLR
1Q
NC
CC
NC – No internal connection
GND
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN54ALS74A, SN54AS74A, SN74ALS74A, SN74AS74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SDAS143C – APRIL 1982 – REVISED AUGUST 1995
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
S
4
3
1CLK
1D
2
1D
R
1
1Q
5
6
C1
10
11
2CLK
12
2D
13
2Q
9
8
1PRE
2PRE
1CLR
2CLR
1Q
2Q
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
logic diagram (positive logic)
PRE
CLR
Q
Q
CLK
D
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
‡
Supply voltage, V
CC
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, V
I
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
A
: SN54ALS74A –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74ALS74A 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
SN54ALS74A, SN54AS74A, SN74ALS74A, SN74AS74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SDAS143C – APRIL 1982 – REVISED AUGUST 1995
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions
SN54ALS74A SN74ALS74A
MIN NOM MAX MIN NOM MAX
UNIT
V
CC
Supply voltage 4.5 5 5.5 4.5 5 5.5 V
V
IH
High-level input voltage 2 2 V
V
IL
Low-level input voltage 0.7 0.8 V
I
OH
High-level output current –0.4 –0.4 mA
I
OL
Low-level output current 4 8 mA
f
clock
Clock frequency 0 25 0 34 MHz
PRE or CLR low 15 15
t
w
Pulse duration
CLK high
17.5 14.5
ns
CLK low 17.5 14.5
Data 16 15
t
su
S
etup time before
CLK↑
PRE or CLR inactive 10 10
ns
t
h
Hold time after CLK↑ Data 2 0 ns
T
A
Operating free-air temperature –55 125 0 70 °C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54ALS74A SN74ALS74A
PARAMETER
TEST CONDITIONS
MIN TYP†MAX MIN TYP†MAX
UNIT
V
IK
VCC = 4.5 V, II = –18 mA –1.5 –1.5 V
V
OH
VCC = 4.5 V to 5.5 V, IOH = –2 mA VCC–2 VCC–2 V
IOL = 4 mA 0.25 0.4 0.25 0.4
VOLV
CC
= 4.5
V
IOL = 8 mA 0.35 0.5
V
CLK or D
0.1 0.1
I
I
PRE or CLR
V
CC
=
4.5 V
,
V
I
=
7 V
0.2 0.2
mA
CLK or D
20 20
I
IH
PRE or CLR
V
CC
= 4.5 V,
V
I
= 2.7
V
40 40
µ
A
CLK or D
–0.2 –0.2
I
IL
PRE or CLR
V
CC
= 4.5 V,
V
I
= 0.4
V
–0.4 –0.4
mA
I
O
‡
VCC = 5.5 V, VO = 2.25 V –20 –112 –30 –112 mA
I
CC
VCC = 5.5 V, See Note 1 2.4 4 2.4 4 mA
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
NOTE 1: ICC is measured with D, CLK, and PRE
grounded, then with D, CLK, and CLR grounded.
SN54ALS74A, SN54AS74A, SN74ALS74A, SN74AS74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SDAS143C – APRIL 1982 – REVISED AUGUST 1995
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics (see Figure 1)
PARAMETER
FROM
(
INPUT
)
TO
(
OUTPUT
)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500 Ω
,
TA = MIN to MAX
†
UNIT
(INPUT)
(OUTPUT)
SN54ALS74A SN74ALS74A
MIN MAX MIN MAX
f
max
25 34 MHz
t
PLH
3 18 3 13
t
PHL
PRE
or
CLR
Q
or
Q
5 17 5 15
ns
t
PLH
5 23 5 16
t
PHL
CLK
Q or Q
5 20 5 18
ns
†
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
‡
Supply voltage, V
CC
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, V
I
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
A
: SN54AS74A –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74AS74A 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54AS74A SN74AS74A
MIN NOM MAX MIN NOM MAX
UNIT
V
CC
Supply voltage 4.5 5 5.5 4.5 5 5.5 V
V
IH
High-level input voltage 2 2 V
V
IL
Low-level input voltage 0.8 0.8 V
I
OH
High-level output current –2 –2 mA
I
OL
Low-level output current 20 20 mA
f
clock
* Clock frequency 0 90 0 105 MHz
PRE or CLR low 4 4
tw* Pulse duration
CLK high 4 4
ns
CLK low 5.5 5.5
*
Data 4.5 4.5
tsu*
S
etup time before
CLK↑
PRE or CLR inactive 2 2
ns
th* Hold time after CLK↑ Data 0 0 ns
T
A
Operating free-air temperature –55 125 0 70 °C
* On products compliant to MIL-STD-833, Class B, this parameter is based on characterization data but is not production tested.
SN54ALS74A, SN54AS74A, SN74ALS74A, SN74AS74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SDAS143C – APRIL 1982 – REVISED AUGUST 1995
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54AS74A SN74AS74A
PARAMETER
TEST CONDITIONS
MIN TYP†MAX MIN TYP†MAX
UNIT
V
IK
VCC = 4.5 V, II = –18 mA –1.2 –1.2 V
V
OH
VCC = 4.5 V to 5.5 V, IOH = –2 mA VCC–2 VCC–2 V
V
OL
VCC = 4.5 V, IOL = 20 mA 0.25 0.5 0.25 0.5 V
I
I
VCC = 5.5 V, VI = 7 V 0.1 0.1 mA
CLK or D
20 20
I
IH
PRE or CLR
V
CC
= 5.5 V,
V
I
= 2.7
V
40 40
µ
A
CLK or D
–0.5 –0.5
I
IL
PRE or CLR
V
CC
= 5.5 V,
V
I
= 0.4
V
–1.8 –1.8
mA
I
O
‡
VCC = 5.5 V, VO = 2.25 V –30 –112 –30 –112 mA
I
CC
VCC = 5.5 V, See Note 1 10.5 16 10.5 16 mA
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
NOTE 1: ICC is measured with D, CLK, and PRE
grounded, then with D, CLK, and CLR grounded.
switching characteristics (see Figure 1)
PARAMETER
FROM
(
INPUT
)
TO
(
OUTPUT
)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500 Ω
,
TA = MIN to MAX
§
UNIT
(INPUT)
(OUTPUT)
SN54AS74A SN74AS74A
MIN MAX MIN MAX
f
max
* 90 105 MHz
t
PLH
2 9 2 7.5
t
PHL
PRE
or
CLR
Q
or
Q
2.5 11.5 2.5 10.5
ns
t
PLH
2.5 10 3 8
t
PHL
CLK
Q or Q
3.5 10.5 3 9
ns
* On products compliant to MIL-STD-833, Class B, this parameter is based on characterization data but is not production tested.
§
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
SN54ALS74A, SN54AS74A, SN74ALS74A, SN74AS74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SDAS143C – APRIL 1982 – REVISED AUGUST 1995
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
t
PHZ
t
PLZ
t
PHL
t
PLH
0.3 V
t
PZL
t
PZH
t
PLH
t
PHL
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
From Output
Under Test
Test
Point
R1
S1
C
L
(see Note A)
7 V
1.3 V
1.3 V1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
t
h
t
su
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing
Input
Data
Input
1.3 V 1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
High-Level
Pulse
Low-Level
Pulse
t
w
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
Out-of-Phase
Output
(see Note C)
1.3 V 1.3 V
1.3 V1.3 V
1.3 V 1.3 V
1.3 V1.3 V
1.3 V
1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
V
OL
V
OH
V
OH
V
OL
Output
Control
(low-level
enabling)
Waveform 1
S1 Closed
(see Note B)
Waveform 2
S1 Open
(see Note B)
[
0 V
V
OH
V
OL
[
3.5 V
In-Phase
Output
0.3 V
1.3 V 1.3 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
R2
V
CC
R
L
Test
Point
From Output
Under Test
C
L
(see Note A)
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
From Output
Under Test
Test
Point
C
L
(see Note A)
R
L
RL = R1 = R2
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
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Copyright 1998, Texas Instruments Incorporated
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