OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SDAS066F – DECEMBER 1983 – REVISED OCTOBER 1996
D
Bus Transceivers/Registers
D
Independent Registers and Enables for A
SN54ALS’, SN54AS’ . . . JT PACKAGE
SN74ALS’, SN74AS’ . . . DW OR NT PACKAGE
(TOP VIEW)
and B Buses
D
Multiplexed Real-Time and Stored Data
D
Choice of True or Inverting Data Paths
D
Choice of 3-State or Open-Collector
Outputs to A Bus
D
Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic
(NT) and Ceramic (JT) 300-mil DIPs
DEVICEA OUTPUTB OUTPUTLOGIC
SN74ALS651A,
’AS651
SN54ALS652,
SN74ALS652A,
’AS652
’ALS653Open Collector3 StateInverting
SN74ALS654Open Collector3 StateTrue
3 State3 StateInverting
3 State3 StateTrue
description
These devices consist of bus-transceiver circuits,
D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the
data bus or from the internal storage registers.
Output-enable (OEAB and OEBA
provided to control the transceiver functions.
Select-control (SAB and SBA) inputs are provided
to select real-time or stored data transfer. The
circuitry used for select control eliminates the
typical decoding glitch that occurs in a multiplexer
during the transition between stored and real-time
data. A low input level selects real-time data, and
) inputs are
CLKAB
OEAB
GND
SN54ALS’, SN54AS’ . . . FK PACKAGE
A1
A2
A3
NC
A4
A5
A6
SAB
A1
A2
A3
A4
A5
A6
A7
A8
4
5
6
7
8
9
10
11
12
A7
1
2
3
4
5
6
7
8
9
10
11
12
(TOP VIEW)
OEAB
SAB
CLKAB
321
13 14
A8
15 16 17
GND
NC – No internal connection
24
23
22
21
20
19
18
17
16
15
14
13
CC
NC
V
28 27 26
B8B7B6
NC
V
CC
CLKBA
SBA
OEBA
B1
B2
B3
B4
B5
B6
B7
B8
CLKBA
SAB
25
24
23
22
21
20
19
18
OEBA
B1
B2
NC
B3
B4
B5
a high input level selects stored data. Figure 1
illustrates the four fundamental bus-management functions that can be performed with the octal bus
transceivers and registers.
Data on the A or B data bus, or both, can be stored in the internal D-type flip-flops by low-to-high transitions at
the appropriate clock (CLKAB or CLKBA) terminals, regardless of the select- or output-control terminals. When
SAB and SBA are in the real-time transfer mode, it is possible to store data without using the internal D-type
flip-flops by simultaneously enabling OEAB and OEBA
. In this configuration, each output reinforces its input.
When all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains
at its last state.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1996, Texas Instruments Incorporated
1
SN54ALS652, SN54ALS653, SN54AS651, SN54AS652
SN74ALS651A, SN74ALS652A, SN74ALS653, SN74ALS654, SN74AS651, SN74AS652
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SDAS066F – DECEMBER 1983 – REVISED OCTOBER 1996
description (continued)
The -1 versions of the SN74ALS651A and SN74ALS652A are identical to the standard versions except that the
recommended maximum I
SN54ALS652, SN54ALS653, SN74ALS653, and SN74ALS654.
The SN54ALS’ and SN54AS’ families are characterized for operation over the full military temperature range
of –55°C to 125°C. The SN74ALS’ and SN74AS’ families are characterized for operation from 0°C to 70°C.
for the -1 versions is increased to 48 mA. There are no -1 versions of the
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SDAS066F – DECEMBER 1983 – REVISED OCTOBER 1996
BUS A
321123222123222321
OEAB
OEBA
LL
CLKABXCLKBAXSABXSBA
REAL-TIME TRANSFER
BUS B TO BUS A
BUS A
BUS B
OEAB OEBA
L
BUS B
BUS A
HH
BUS A
BUS B
CLKABXCLKBAXSABLSBA
X
REAL-TIME TRANSFER
BUS A TO BUS B
BUS B
321232223211222
OEAB
Pin numbers are for the DW, JT, and NT packages.
OEBA
X
L
L
H
X
H
1
CLKAB CLKBAXSABXSBA
↑
XX
STORAGE FROM
A, B, OR A AND B
↑
↑↑
Figure 1. Bus-Management Functions
OEAB OEBA
X
X
X
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
X
HLH or LHH
23
CLKAB CLKBA SABSBA
H or L
TRANSFER STORED DA TA
TO A AND/OR B
3
SN54ALS652, SN54ALS653, SN54AS651, SN54AS652
OPERATION OR FUNCTION
OPERATION OR FUNCTION
SN74ALS651A, SN74ALS652A, SN74ALS653, SN74ALS654, SN74AS651, SN74AS652
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SDAS066F – DECEMBER 1983 – REVISED OCTOBER 1996
FUNCTION TABLES
SN54ALS653, SN54AS651,
SN74ALS651A, SN74ALS653, SN74AS651
INPUTS
OEABOEBACLKABCLKBASABSBAA1–A8B1–B8
LHH or LH or LXXInputInputIsolation
LH↑↑XXInputInputStore A and B data
XH↑H or LXXInputUnspecified
HH↑↑X
LXH or L↑XXUnspecified
LL↑↑XX
LLXXXLOutputInputReal-time B data to A bus
LLXH or LXHOutputInputStored B data to A bus
HHXXLXInputOutputReal-time A data to B bus
HHH or LXHXInputOutputStored A data to B bus
HLH or LH or LHHOutputOutput
†
The data output functions may be enabled or disabled by a variety of level combinations at OEAB or OEBA. Data input functions are always
enabled; i.e., data at the bus terminals is stored on every low-to-high transition on the clock inputs.
‡
Select control = L; clocks can occur simultaneously.
Select control = H; clocks must be staggered to load both registers.
‡
XInputOutputStore A in both registers
‡
DATA I/O
‡
OutputInputStore B in both registers
†
‡
InputHold A, store B
Store A, hold B
Stored A data to B bus and
stored B
data to A bus
SN54ALS652, SN54AS652,
SN74ALS652A, SN74ALS654, SN74AS652
INPUTS
OEABOEBACLKABCLKBASABSBAA1–A8B1–B8
LHH or LH or LXXInputInputIsolation
LH↑↑XXInputInputStore A and B data
XH↑H or LXXInputUnspecified
HH↑↑X
LXH or L↑XXUnspecified
LL↑↑XX
LLXXXLOutputInputReal-time B data to A bus
LLXH or LXHOutputInputStored B data to A bus
HHXXLXInputOutputReal-time A data to B bus
HHH or LXHXInputOutputStored A data to B bus
HLH or LH or LHHOutputOutput
†
The data output functions may be enabled or disabled by a variety of level combinations at OEAB or OEBA. Data input functions are always
enabled; i.e., data at the bus terminals is stored on every low-to-high transition on the clock inputs.
‡
Select control = L; clocks can occur simultaneously.
Select control = H; clocks must be staggered to load both registers.
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SDAS066F – DECEMBER 1983 – REVISED OCTOBER 1996
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
Input voltage, V
Operating free-air temperature range, T
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
CLKBA or CLKAB low14.512.5
Setup time before CLKAB↑ or CLKBA↑A or B1510ns
Hold time after CLKAB↑ or CLKBA↑A or B50ns
Operating free-air temperature–55125070°C
1224
48
m
‡
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
SN54ALS652, SN54ALS653, SN54AS651, SN54AS652
PARAMETER
TEST CONDITIONS
UNIT
V
V
V
V
I
mA
I
V
V
V
A
I
V
5.5 V
V
0.4 V
A
SN74ALS651A, SN74ALS652A, SN74ALS653, SN74ALS654, SN74AS651, SN74AS652
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SDAS066F – DECEMBER 1983 – REVISED OCTOBER 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN74ALS651A
MIN TYP†MAX
V
IK
V
OH
V
OL
I
IH
IL
I
O
I
CC
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
For I/O ports, the parameters IIH and IIL include the off-state output current.
§
The output conditions have been chosen to produce a current that closely approximates one-half of the true short-circuit output current, IOS.
Control inputsVCC = 5.5 V,VI = 7 V0.1
A or B portsVCC = 5.5 V,VI = 5.5 V0.1
Control inputs
A or B ports
Control inputs
A or B ports
§
‡
‡
VCC = 4.5 V,II = –18 mA–1.2V
VCC = 4.5 V to 5.5 V,IOH = –0.4 mAVCC–2
SN74ALS651A, SN74ALS652A, SN74ALS653, SN74ALS654, SN74AS651, SN74AS652
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SDAS066F – DECEMBER 1983 – REVISED OCTOBER 1996
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
Input voltage, V
Operating free-air temperature range, T
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
CLKBA or CLKAB low2014.5
Setup time before CLKAB↑ or CLKBA↑A or B1510ns
Hold time after CLKAB↑ or CLKBA↑A or B50ns
Operating free-air temperature–55125070°C
SN74ALS651A, SN74ALS652A, SN74ALS653, SN74ALS654, SN74AS651, SN74AS652
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SDAS066F – DECEMBER 1983 – REVISED OCTOBER 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN74ALS654
MIN TYP†MAX
V
IK
V
OH
OL
I
IH
IL
I
OH
I
O
I
CC
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
For I/O ports, the parameters IIH and IIL include the off-state output current.
§
The output conditions have been chosen to produce a current that closely approximates one-half of the true short-circuit output current, IOS.
B ports
Control inputsVCC = 5.5 V,VI = 7 V0.1
A or B portsVCC = 5.5 V,VI = 5.5 V0.1
Control inputs
A or B ports
Control inputs
A or B ports
A portsVCC = 4.5 V,VOH = 5.5 V0.1mA
§
B portsVCC = 5.5 V,VO = 2.25 V–30–112mA
‡
‡
VCC = 4.5 V,II = –18 mA–1.2V
VCC = 4.5 V to 5.5 V,IOH = –0.4 mAVCC–2
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SDAS066F – DECEMBER 1983 – REVISED OCTOBER 1996
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
Input voltage, V
Operating free-air temperature range, T
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SDAS066F – DECEMBER 1983 – REVISED OCTOBER 1996
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
(see Note A)
Timing
Input
Data
Input
7 V
S1
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
t
su
1.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Open
R1 = 500 Ω
1.3 V
Test Point
R2 = 500 Ω
t
h
1.3 V
3.5 V
0.3 V
3.5 V
0.3 V
SWITCH POSITION TABLE
TESTS1
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Open
Open
Open
Closed
Open
Closed
High-Level
Pulse
Low-Level
Pulse
V
CC
R
L
From Output
Under Test
CL = 50 pF
(see Note A)
1.3 V
t
1.3 V
LOAD CIRCUIT
w
FOR OPEN-COLLECTOR OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
Test Point
1.3 V
1.3 V
3.5 V
0.3 V
3.5 V
0.3 V
Input
t
PLH
In-Phase
Output
t
PHL
Out-of-Phase
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 2 ns, tf≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
1.3 V
1.3 V1.3 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
1.3 V
Figure 2. Load Circuits and Voltage Waveforms
t
1.3 V1.3 V
t
PHL
PLH
3.5 V
0.3 V
V
OH
V
OL
V
OH
V
OL
Output
Control
Waveform 1
S1 Closed
(see Note B)
Waveform 2
S1 Open
(see Note B)
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
t
PZL
t
PZH
1.3 V
1.3 V
t
PHZ
1.3 V
VOLTAGE WAVEFORMS
1.3 V
t
PLZ
V
0.3 V
3.5 V
0.3 V
3.5 V
OL
0.3 V
V
OH
0 V
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
21
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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