Datasheet SE370C768AFZT, SE370C769AFZT Datasheet (Texas Instruments)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TMS370Cx6x

8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

1

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

D

CMOS/EEPROM/EPROM Technologies on a Single Device – Mask-ROM Devices for High-Volume

Production

– One-Time-Programmable (OTP) EPROM

Devices for Low-Volume Production

– Reprogrammable EPROM Devices for

Prototyping Purposes

D

Internal System Memory Configurations – On-Chip Program Memory Versions

– ROM: 24K, 32K, or 48K Bytes

– EPROM: 32K or 48K Bytes – Data EEPROM: 256 Bytes – Static RAM: 1K or 3.5K Bytes – External Memory/Peripheral Wait States – Precoded External Chip-Select Outputs

in Microcomputer Mode

D

Flexible Operating Features – Low-Power Modes: STANDBY and HALT – Commercial, Industrial, and Automotive

T emperature Ranges

– Clock Options

– Divide-by-4 (0.5 MHz – 5 MHz SYSCLK)

– Divide-by-1 (2 MHz – 5 MHz SYSCLK)

PLL

– Supply Voltage (V

CC

): 5 V ± 10%

D

Eight-Channel 8-Bit Analog-to-Digital Converter 1 (ADC1)

D

Three 16-Bit General Purpose Timers – Software Configurable as

Three 16-Bit Event Counters, or Three 16-Bit Pulse Accumulators, or Five 16-Bit Input Capture Functions, or Six Compare Registers, or Three Self-Contained PWM Functions

– One Timer Has an 8-Bit Prescaler,

Providing a 24-Bit Real-Time Timer

D

On-Chip 24-Bit Watchdog Timer – EPROM/OTP: Standard Watchdog – Mask-ROM Devices: Hard Watchdog,

Simple Counter, or Standard Watchdog

D

Serial Communications Interface (SCI1) – Asynchronous and Isosynchronous

†

Modes – Full Duplex, Double-Buffered RX and TX – Two Multiprocessor Communication

Formats

D

Serial Peripheral Interface (SPI) – Variable-Length High-Speed Shift

Register

– Synchronous Master/Slave Operation

D

Flexible Interrupt Handling – Two S/W Programmable Interrupt Levels – Global- and Individual-Interrupt Masking – Programmable Rising- or Falling-Edge

Detect

D

TMS370 Series Compatibility – Register-to-Register Architecture – 256 General-Purpose Registers – 14 Powerful Addressing Modes – Instructions Upwardly Compatible With

All TMS370 Devices

D

CMOS/Package/TTL-Compatible I/O Pins – 46 Bidirectional Pins, 9 Input Pins – 68-Pin Plastic and Ceramic Leaded Chip

Carrier Packages

– All Peripheral Function Pins Are

Software Configurable for Digital I/O

D

Workstation/PC-Based Development System – C Compiler and C Source Debugger – Real-Time In-Circuit Emulation – Extensive Breakpoint/Trace Capability – Software Performance Analysis – Multi-Window User Interface – Microcontroller Programmer

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright  1997, Texas Instruments Incorporated

FN/FZ PACKAGE

(TOP VIEW)

V

SS1

B7

C2C1MCC0B6

T2AIC1/CR

SCICLK

SCIRXD

SCITXD

XTAL2/CLKIN

XTAL1

C3 C4 C5 C6 C7

SPISOMI

SPICLK

SPISIMO

T1IC/CR T1PWM T1EVT

9876543

10 11 12 13 14 15 16

B5B0B4B3B2B1V

CC2VSS2VCC1

2 1 686766 65 6463 62 61

2728293031323334 353637 38 394041 4243

V

CC3

V

SS3

V

CC1

17 18 19 20 21 22 23 24 25 26

60 59 58 57 56 55 54

53 52 51 50 49 48 47 46 45 44

V

CC2

V

SS2

A0 A1 A2 A3 A4 A5 A6 A7

T2AEVT

T2AIC2/PWM

INT1 INT2 INT3

T2BIC2/PWM T2BEVT D3/SYSCLK D4/R/W D5/CSPF D6/CSH1/EDS D7/CSE1/WAIT RESET

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

T2BIC1/CR

†

Isosynchronous = Isochronous

TMS370Cx6x 8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

2

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Pin Descriptions

NAME

ALTERNATE

FUNCTION

PLCC

(68)

I/O

†

DESCRIPTION

‡

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

A0 A1 A2 A3 A4 A5 A6 A7

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7

Á

17 18 19 20 21 22 23 24

I/O

ББББББББББББББББББББ

Á

ББББББББББББББББББББ

Á

ББББББББББББББББББББ

Á

ББББББББББББББББББББ

Á

ББББББББББББББББББББ

Á

Single-chip mode: Port A is a general-purpose bidirectional I/O port. Expansion mode: Port A can be individually programmed as the external bidirectional data bus (DATA0–DATA7).

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

B0 B1 B2 B3 B4 B5 B6 B7

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7

Á

65 66 67 68

1 2 3 4

I/O

ББББББББББББББББББББ

Á

ББББББББББББББББББББ

Á

ББББББББББББББББББББ

Á

ББББББББББББББББББББ

Á

Single-chip mode: Port B is a general-purpose bidirectional I/O port. Expansion mode: Port B can be individually programmed as the low-order address output bus (ADDR0–ADDR7).

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

C0 C1 C2 C3 C4 C5 C6 C7

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ADDR8

ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15

Á

5 7

8 10 11 12 13 14

I/O

ББББББББББББББББББББ

Á

ББББББББББББББББББББ

Á

ББББББББББББББББББББ

Á

ББББББББББББББББББББ

Á

Single-chip mode: Port C is a general-purpose bidirectional I/O port. Expansion mode: Port C can be individually programmed as the high-order address output bus (ADDR8–ADDR15).

ÁÁÁ

Á

ÁÁÁ

Á

INT1 INT2 INT3

ÁÁÁÁ

Á

ÁÁÁÁ

Á

NMI

— —

Á

52 51 50

I I/O I/O

ББББББББББББББББББББ

Á

ББББББББББББББББББББ

Á

External (nonmaskable or maskable) interrupt/general-purpose input pin External maskable interrupt input/general-purpose bidirectional pin External maskable interrupt input/general-purpose bidirectional pin

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

E0 E1 E2 E3 E4 E5 E6 E7

Á

36 37 38 39 40 41 42 43

I

ББББББББББББББББББББ

Á

ББББББББББББББББББББ

Á

ББББББББББББББББББББ

Á

ББББББББББББББББББББ

Á

ADC1 analog input (AN0–AN7) or positive reference pins (AN1–AN7) Port E can be programmed individually as general-purpose input pins if not used as ADC1 analog input or positive reference input.

ÁÁÁ

Á

V

CC3

V

SS3

ÁÁÁÁÁÁ

Á

34 35

ББББББББББББББББББББ

Á

ADC1 positive-supply voltage and optional positive-reference input pin ADC1 ground reference pin

ÁÁÁ

Á

RESET

ÁÁÁÁÁÁ

Á

53

I/O

ББББББББББББББББББББ

Á

System reset bidirectional pin. RESET, as an input, initializes the microcontroller; as open-drain output, RESET

indicates an internal failure was detected by the watchdog or

oscillator fault circuit.

MC

6

I

Mode control (MC) pin. MC enables EEPROM write-protection override (WPO) mode, also EPROM VPP.

ÁÁÁ

Á

XTAL2/CLKIN XTAL1

ÁÁÁÁÁÁ

Á

31 32IO

ББББББББББББББББББББ

Á

Internal oscillator crystal input/external clock source input Internal oscillator output for crystal

V

CC1

33, 61

Positive supply voltage

V

CC2

15, 63

Positive supply voltage

†

I = input, O = output

‡

Ports A, B, C, and D can be configured only as general-purpose I/O pins. Also, port D3 can be configured as SYSCLK.

TMS370Cx6x

8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

3

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Pin Descriptions (Continued)

ÁÁÁ

Á

NAME

ÁÁÁÁ

Á

ALTERNATE

FUNCTION

Á

PLCC

(68)

I/O

†

БББББББББББББББББББ

Á

DESCRIPTION

‡

V

SS1

9

Ground reference for digital logic

V

SS2

16,62

Ground reference for digital I/O logic

ÁÁÁÁÁÁÁÁ

Á

FUNCTION

Á

БББББББББББББББББББ

Á

Single-chip mode: Port D is a general-purpose bidirectional I /O port. Each of the port D pins can be configured individually as a general-purpose I/O pin, primary memory

p

A

B

control signal (function A), or secondary memory control signal (function B). All chip

selects are independent and can be used for memory-bank switching. See Table 1 for function A memory accesses.

D3

SYSCLK

58

I/O pin A, B: Internal clock signal is 1/1 (PLL) or 1/4 XTAL2/CLKIN frequency

D4

R/W

57

I/O pin A, B: Read/write output pin

ÁÁÁ

Á

D5

Á

CSPF

ÁÁ

Á

—

Á

56

БББББББББББББББББББ

Á

I / O pin A: Chip select peripheral output for peripheral file goes low during memory accesses I/O pin B: Reserved

ÁÁÁ

Á

D6

Á

CSH1

ÁÁ

Á

EDS

Á

55

I/O

БББББББББББББББББББ

Á

I/O pin A: Chip select half output 1 goes low during memory accesses I/O pin B: External data strobe output goes low during memory accesses from external memory and has the same timings as the five chip selects.

ÁÁÁ

Á

D7

Á

CSE1

ÁÁ

Á

WAIT

Á

54

БББББББББББББББББББ

Á

I/O pin A: Chip select eighth output goes low during memory accesses. I/O pin B: Wait-input pin extends bus signals.

ÁÁÁ

Á

SCITXD SCIRXD SCICLK

ÁÁÁÁ

Á

SCIIO1 SCIIO2 SCIIO3

Á

30 29 28

I/O

БББББББББББББББББББ

Á

SCI transmit data output pin/general-purpose bidirectional pin

§

SCI receive data input pin/general-purpose bidirectional pin SCI bidirectional serial clock pin/general-purpose bidirectional pin

ÁÁÁ

Á

T1IC/CR T1PWM T1EVT

ÁÁÁÁ

Á

T1IO1 T1IO2 T1IO3

Á

46 45 44

I/O

БББББББББББББББББББ

Á

Timer1 input capture/counter reset input pin/general-purpose bidirectional pin Timer1 pulse width modulation (PWM) output pin/general-purpose bidirectional pin Timer1 external event input pin/general-purpose bidirectional pin

ÁÁÁ

Á

ÁÁÁ

Á

T2AIC1/CR T2AIC2/PWM T2AEVT

ÁÁÁÁ

Á

ÁÁÁÁ

Á

T2AIO1 T2AIO2 T2AIO3

Á

27 26 25

I/O

БББББББББББББББББББ

Á

БББББББББББББББББББ

Á

Timer2A input capture 1/counter-reset input pin/general-purpose bidirectional pin Timer2A input capture 2/PWM output pin/general-purpose bidirectional pin Timer2A external event input pin/general-purpose bidirectional pin

ÁÁÁ

Á

T2BIC1/CR T2BIC2/PWM T2BEVT

ÁÁÁÁ

Á

T2BIO1 T2BIO2 T2BIO3

Á

64 60 59

I/O

БББББББББББББББББББ

Á

Timer2B input capture 1/counter-reset input pin/general-purpose bidirectional pin Timer2B input capture 2/PWM output pin/general-purpose bidirectional pin Timer2B external event input pin/general-purpose bidirectional pin

ÁÁÁ

Á

SPISOMI SPISIMO SPICLK

ÁÁÁÁ

Á

SPIIO1 SPIIO2 SPIIO3

Á

49 48 47

I/O

БББББББББББББББББББ

Á

SPI slave output pin, master input pin/general-purpose bidirectional pin SPI slave input pin, master output pin/general-purpose bidirectional pin SPI bidirectional serial clock pin/general-purpose bidirectional pin

†

I = input, O = output

‡

Ports A, B, C, and D can be configured only as general-purpose I/O pins. Port D3 also can be configured as SYSCLK.

§

The three-pin configuration SCI is referred to as SCI1.

Table 1. Function A Memory-Access Locations for ‘x6x Devices

FUNCTION A

’X67

‘X68

‘X69

CSE1

A000h – BFFFh (8K bytes)

E000h – EFFFh (4K bytes)

CSH1

C000h – FFFFh (16K bytes)

F000h – FFFFh (4K bytes)

CSPF

10C0h – 10FFh (64 bytes)

TMS370Cx6x 8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

4

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

functional block diagram

Program Memory

ROM: 24K, 32K, or

48K Bytes

EPROM: 32K or

48K Bytes

V

SS1

V

CC1

RESET

MCXTAL2/

CLKIN

XTAL1INT3INT2INT1

E0–E7

or

AN0–AN7

V

CC2

V

SS2

Data EEPROM

256 Bytes

RAM

1K or 3.5K Bytes

CPU

Port D

Port C

Port B

Watchdog

Timer 1

Timer 2B

Serial

Communications

Interface 1

Serial

Peripheral

Interface

System Control

Clock Options:

Divide-by-4 or

Divide-by-1(PLL)

T1PWM

T1EVT

T1IC/CR

T2BIC2/PWM

T2BEVT

T2BIC1/CR

SCICLK

SCITXD

SCIRXD

SPICLK

SPISIMO

SPISOMI

V

SS3

V

CC3

Port A

Interrupts

5888

Memory Expansion

Data

Address LSbyte

Address MSbyte

Control

Timer 2A

T2AIC2/PWM

T2AEVT

T2AIC1/CR

Analog to Digital

Converter 1

description

The TMS370C067, TMS370C068, TMS370C069, TMS370C768, TMS370C769, SE370C768, and SE370C769 devices are members of the TMS370 family of single-chip 8-bit microcontrollers. Unless otherwise noted, the term TMS370Cx6x refers to these devices. The TMS370 family provides cost-effective real-time control through integration of advanced peripheral function modules and various on-chip memory configurations.

The TMS370Cx6x family of devices is implemented using high-performance silicon-gate CMOS EPROM and EEPROM technologies. The low-operating power, wide-operating temperature range, and noise immunity of CMOS technology, coupled with the high performance and extensive on-chip peripheral functions, make the TMS370Cx6x devices attractive in system designs for automotive electronics, industrial motor control, computer peripheral control, telecommunications, and consumer application.

All TMS370Cx6x devices contain the following on-chip peripheral modules:

D

8-channel, 8-bit analog-to-digital converter 1 (ADC1)

D

Serial communications interface 1 (SCI1)

D

Serial peripheral interface (SPI)

TMS370Cx6x

8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

5

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

description (continued)

D

One 24-bit general-purpose watchdog timer

D

Three 16-bit general-purpose timers (one with an 8-bit prescaler)

Table 2 provides a memory configuration overview of the TMS370Cx6x devices.

Table 2. Memory Configurations

DEVICE

PROGRAM

MEMORY

(BYTES)

OFF-CHIP

MEMORY

DATA MEMORY

(BYTES)

OPERATING

MODES

PACKAGES

68-PIN PLCC/CLCC

ROM EPROM

EXP. (BYTES)

RAM EEPROM µC†µP

†

TMS370C067A

24K

—

24K

1K

256

√

FN – PLCC

TMS370C068A

32K

—

24K

1K

256

√

FN – PLCC

TMS370C069A

48K

‡

—

8K

3.5K

256

√

FN – PLCC

TMS370C768A

—

32K

24K

1K

256

√

FN – PLCC

TMS370C769A

—

48K

‡

8K

3.5K

256

√

FN – PLCC

SE370C768A

§

—

32K

24K

1K

256

√

FZ – CLCC

SE370C769A

§

—

48K

‡

8K

3.5K

256

√

FZ – CLCC

†

µC – Microcomputer mode µP – Microprocessor mode

‡

’x69 can only operate up to 3 MHz SYSCLK.

§

System evaluators and development tools are for use only in a prototype environment, and their reliability has not been characterized.

The suffix letter (A) appended to the device names shown in the device column of Table 2 indicates the configuration of the device. ROM or EPROM devices have different configurations as indicated in T able 3. ROM devices with the suffix letter A are configured through a programmable contact during manufacture.

Table 3. Suffix Letter Configuration

DEVICE

¶

WATCHDOG TIMER CLOCK LOW-POWER MODE

EPROM A Standard Divide-by-4 (Standard oscillator) Enabled

Standard

ROM A

Hard

Divide-by-4 or Divide-by-1 (PLL) Enabled or disabled

Simple

¶

Refer to the “device numbering conventions” section for device nomenclature and the “device part numbers” section for ordering.

The mask-programmable ROM in the associated TMS370C06x devices is replaced in the TMS370C76x with 32K or 48K bytes of EPROM while all the other available memory and on-chip peripherals are identical. One-time-programmable (OTP) (TMS370C768 and TMS370C769) and reprogrammable devices (SE370C768 and SE370C769) are available.

TMS370C768 and TMS370C769 are OTP devices that are available in plastic packages. This microcomputer is effective to use for immediate production updates for other members of the TMS370Cx6x family or for low-volume production runs when the mask charge or cycle time for low-cost mask-ROM devices is not practical.

The SE370C768 and SE370C769 have windowed ceramic packages to allow reprogramming of the program EPROM memory during the development / prototyping phase of design. The SE370C768 and SE370C769 devices allow quick updates to breadboards and prototype systems while iterating initial designs.

TMS370Cx6x 8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

6

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

description (continued)

The TMS370Cx6x family provides two low-power modes (STANDBY and HALT) for applications where low-power consumption is critical. Both modes stop all central processing unit (CPU) activity (i.e., no instructions are executed). In the ST ANDBY mode, the internal oscillator and the general-purpose timer remain active. In the HAL T mode, all device activity is stopped. The device retains all RAM data and peripheral configuration bits throughout both low-power modes.

The TMS370Cx6x features advanced register-to-register architecture that allows direct arithmetic and logical operations without requiring an accumulator (for example, ADD R24, R47; add the contents of register 24 to the contents of register 47 and store the result in register 47). The TMS370Cx6x family is fully instruction-set compatible, allowing easy transition between members of the TMS370 8-bit microcontroller family.

The SPI and the two operational modes of the SCI1 allow three methods of serial communications. The SCI1 allows standard RS-232-C communications interface between other common data transmission equipment, while the SPI gives high-speed communications between simpler shift-register type devices, such as display drivers, ADC1, phase-locked loop (PLL), I/O expansion, or other microcontrollers in the system.

For large memory applications, the TMS370Cx6x family provides an external bus with non-multiplexed address and data. Precoded memory chip-select outputs can be enabled, which allows minimum-chip-count system implementations. Wait-state support facilitates performance matching among the CPU, external memory, and the peripherals. All pins associated with memory expansion interface are individually software configurable for general purpose digital input/output (I/O) pins when operating in the microcomputer mode.

The TMS370Cx6x family provides the system designer with an economical, efficient solution to real-time control applications. The TMS370 family compact development tool (CDT) solves the challenge of efficiently developing the software and hardware required to design the TMS370Cx6x into an ever-increasing number of complex applications. The application source code can be written in assembly and C language, and the output code can be generated by the linker. The TMS370 family CDT development tool can communicate through a standard RS-232-C interface with an existing personal computer. This allows the use of the personal computer editors and software utilities already familiar to the designer. The TMS370 family CDT emphasizes extensive use of menus and screen windowing so that a system designer with minimal training can begin developing software. Precise real-time in-circuit emulation and extensive symbolic debug and analysis tools ensure efficient software and hardware implementation as well as reduced time-to-market cycle.

The TMS370Cx6x family together with the TMS370 family CDT370, starter kit, software tools, the SE370C76x reprogrammable devices, comprehensive product documentation, and customer support provide a complete solution to the needs of the system designer.

CDT is a trademark of Texas Instruments Incorporated.

TMS370Cx6x

8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

7

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

modes

The TMS370Cx6x has four operating modes, two basic modes with each mode having two memory configurations. The basic operating modes are the microcomputer and microprocessor modes, which are selected by the voltage level applied to the dedicated MC pin two cycles before RESET

goes inactive. The two memory configurations then are selected through software programming of the internal system configuration registers. The four operating modes are the microcomputer single chip, microcomputer with external expansion, microprocessor without internal program memory, and microprocessor with internal program memory. These modes are described in the following list.

D

Microcomputer single chip mode: – Operates as a self-contained microcomputer with all memory and peripherals on-chip – Maximizes the general-purpose I/O capability for real-time control applications

D

Microcomputer with external expansion mode: – Supports bus expansion to external memory or peripherals, while all on-chip memory (RAM, ROM,

EPROM, and data EEPROM) remains active

– Configures digital I/O ports (ports A, B, C, and D) through software, under control of the associated port

control, to become external memory as follows: – Port A: 8-bit data memory – Port B and Port C: 16-bit address memory – Port D: 5-bit control memory (pin not used as function A or B can be configured as I/O)

– Utilizes the pins available (not used for address, data, or control memory) as general-purpose

input/output by programming them individually

– Lowers the system cost by not requiring an external address/data latch (address memory and data

memory are nonmultiplexed)

– Reduces external interface decode logic by using the precoded chip select outputs that provide direct

memory/peripheral chip select or chip enable functions

– Function A maps up to 24K bytes of external memory into the address space by using CSE1

and CSH1

as memory-bank selects under software control.

– Function B maps up to 24K bytes of external memory into the address space by using EDS under

software control.

D

Microprocessor without internal program memory mode: – Ports A, B, C, and D (these ports are not programmable) become the address, data, and control buses

for interface to external memory and peripherals. – On-chip RAM and data EEPROM remain active, while the on-chip ROM or EPROM is disabled. – Program area and the reset, interrupt, and trap vectors are located in off-chip memory locations.

D

Microprocessor with internal program memory mode: – Configured as the microprocessor without internal program memory mode with respect to the external

bus interface – Application program in external memory enables the internal program ROM or EPROM to be active in

the system. (Writing a zero to the MEMORY DISABLED control bit (SCCR1.2) of the SCCR1 control

register accomplishes this.)

TMS370Cx6x 8-BIT MICROCONTROLLER

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memory/peripheral wait operation

The TMS370Cx6x enhances interface flexibility by providing WAIT -state support, decoupling the cycle time of the CPU from the read/write access of the external memory or peripherals. External devices can extend the read/write accesses indefinitely by placing an active low on the WAIT

input pin. The CPU continues to wait as

long as WAIT remains active. Programmable automatic wait-state generation also is provided by the TMS370Cx6x on-chip bus controller.

Following a hardware reset, the TMS370Cx6x is configured to add one wait state to all external bus transactions and memory and peripheral accesses, thus making every external access a minimum of three system clock cycles. The designer can disable the automatic wait-state generation if the AUTOWAIT DISABLE bit in SCCR1 is set to 1. Also, all accesses to the upper four frames of the peripheral file can be extended independently to four system clock cycles if the PF AUTO WAIT bit in SCCR0 is set to one. Programmable wait states

can be

used in conjunction with the external WAIT pin. In applications where the external device read/write access can interface with the TMS370Cx6x CPU using one wait state, the automatic wait-state generation can eliminate external WAIT interface logic, lowering system cost.

TMS370Cx6x

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CPU

The CPU used on TMS370Cx6x devices is the high-performance 8-bit TMS370 CPU module. The ’x6x implements an efficient register-to-register architecture that eliminates the conventional accumulator bottleneck. The complete ’x6x instruction set is summarized in Table 22. Figure 1 illustrates the CPU registers and memory blocks.

0000h

0400h

1000h 10C0h 1100h

Interrupts and Reset Vectors;

Trap Vectors

FFFFh

0

RAM (Includes 256-Byte Registers File)

015

Program Counter (PC)

7

Legend:

Z=Zero

IE1=Level1 interrupts Enable

C=Carry

V=Overflow

N=Negative

IE2=Level2 interrupts Enable

IE1IE2ZNC

01234567

V

Status Register (ST)

Stack Pointer (SP)

R0(A) R1(B)

R3

R127

0000h 0001h

0002h

007Fh

R255

0003h

R2

00FFh

Reserved

†

24K-Byte ROM (2000h–7FFFh)

1F00h

0100h

0E00h

32K-Byte ROM/EPROM (2000h–9FFFh)

48K-Byte ROM/EPROM (2000h–DFFFh)

Memory Expansion

2000h

7FBEh

A000h

E000h

1K-Byte RAM (0000h–03FFh)

3.5K-Byte RAM (0000h–0DFFh)

Peripheral File

Peripheral Expansion

Reserved

256-Byte Data EEPROM

00FFh

03FFh

0FFFh 10BFh 10FFh

1EFFh

0DFFh

1FFFh

7FBDh

8000h

7FFFh

9FFFh

DFFFh

†

Reserved means the address space is reserved for future expansion.

Figure 1. Programmer’s Model

TMS370Cx6x 8-BIT MICROCONTROLLER

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CPU (continued)

The ’x6x CPU architecture provides the following components:

D

CPU registers: – A stack pointer that points to the last entry in the memory stack – A status register that monitors the operation of the instructions and contains the global-interrupt-enable

bits

– A program counter (PC) that points to the memory location of the next instruction to be executed

D

A memory map that includes : – 1K- or 3.5K-byte general-purpose RAM that can be used for data-memory storage, program

instructions, general-purpose register, or the stack (can be located only in the first 256 bytes)

– A peripheral file that provides access to all internal peripheral modules, system-wide control functions,

and EEPROM/EPROM programming control

– 256-byte EEPROM module that provides in-circuit programmability and data retention in power-off

conditions

– 24K-, 32K-, or 48K-byte ROM or 32K-, or 48K-byte EPROM program memory

stack pointer (SP)

The SP is an 8-bit CPU register. The stack operates as a last-in, first-out, read/write memory . The stack is used typically to store the return address on subroutine calls as well as the status-register contents during interrupt sequences.

The SP points to the last entry or to the top of the stack. The SP increments automatically before data is pushed onto the stack and decrements after data is popped from the stack. The stack can be located only in the first 256 bytes of the on-chip RAM memory.

status register (ST)

The ST monitors the operation of the instructions and contains the global-interrupt-enable bits. The ST includes four status bits (condition flags) and two interrupt-enable bits:

D

The four status bits indicate the outcome of the previous instruction; conditional instructions (for example, the conditional-jump instructions) use these status bits to determine program flow.

D

The two interrupt-enable bits control the two interrupt levels.

The ST register, status bit notation, and status bit definitions are shown in Table 4.

Table 4. Status Registers

7

6

5

4

3

2

1

0

C

N

Z

V

IE2

IE1

Reserved

RW-0

R = read, W = write, 0 = value after reset

TMS370Cx6x

8-BIT MICROCONTROLLER

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CPU (continued)

program counter (PC)

The contents of the PC point to the memory location of the next instruction to be executed. The PC consists of two 8-bit registers in the CPU: the program counter high (PCH) and program counter low (PCL). These registers contain the most-significant byte (MSbyte) and least-significant byte (LSbyte) of a 16-bit address.

The contents of the reset vector (7FFEh, 7FFFh) are loaded into the program counter during reset. The PCH (MSbyte of the PC) is loaded with the contents of memory location 7FFEh, and the PCL (LSbyte of the PC) is loaded with the contents of memory location 7FFFh. Figure 2 shows this operation using an example value of 6000h as the contents of memory locations 7FFEh and 7FFFh (reset vector).

Memory

Program Counter

60 00

PCH PCL

60 00

0000h

7FFEh 7FFFh

Figure 2. Program Counter After Reset

memory map

The TMS370Cx6x architecture is based on the Von Neuman architecture, where the program memory and data memory share a common address space. All peripheral input/output is memory mapped in this same common address space. In the expansion mode, external memory peripherals are also memory-mapped into this common address. As shown in Figure 3, the TMS370Cx6x provides a 16 bit-address range to access internal or external RAM, ROM, data EEPROM, EPROM input/output pins, peripheral functions, and system-interrupt vectors.

The peripheral file contains all input/output port control, on- and off-chip peripheral status and control, EPROM, EEPROM programming, and system-wide control functions. The peripheral file consists of 256 contiguous addresses located from 1000h to 10FFh. The 256 contiguous addresses are logically divided into 16 peripheral file frames of 16 bytes each. Each on-chip peripheral is assigned to a separate frame through which peripheral control and data information is passed. The TMS370Cx6x has its on-chip peripherals and system control assigned to peripheral file frames 1 through 8, addresses 1010h through 108Fh.

TMS370Cx6x 8-BIT MICROCONTROLLER

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memory map (continued)

Memory Expansion

48K-Byte ROM/EPROM

(2000h–DFFFh)

Interrupts and Reset

Vectors; Trap Vectors

Peripheral File Control Registers

1000h–100Fh

Reserved

†

1F00h

24K-Byte ROM

(2000h–7FFFh)

256-Byte Data EEPROM

(1F00h–1FFFh)

Peripheral Expansion

Peripheral File

3.5K-Byte RAM

(0000h–0DFFh)

1K-Byte RAM

(0000h–03FFh)

0000h

0400h

10C0h

1100h

2000h

7FBEh

8000h

A000h

E000h FFFFh

Microprocessor Mode

¶

Microprocessor With

Internal Program

Memory

Microcomputer

Mode With External

Expansion

ÚÚ

’X67

ÚÚ

Microcomputer

Single Chip Mode

FFFFh

E000h

A000h

8000h

1F00h

10C0h

1000h

0E00h

0400h

0000h

’X68’X69

Not Available

‡

(N/A)

Not Available

‡

Reserved

†

On-Chip For TMS370Cx69 Devices On-Chip For TMS370Cx68 Devices On-Chip For TMS370Cx67 Devices

ÚÚ

2000h

1100h

Reserved

†

’X67

’X68’X69

External

§

Reserved

†

External

§

N/A

‡

Reserved

†

’X67

’X68’X69

External

§

Reserved

†

External

§

N/A

‡

Reserved

†

’X67

’X68’X69

External

§

Reserved

†

External

§

Reserved

0E00h

1000h

Reserved

1010h–101Fh

System Control

1020h–102Fh

Digital Port Control

1030h–103Fh

SPI Peripheral Control

32K-Byte ROM/EPROM

(2000h–9FFFh)

1040h–104Fh

Timer 1 Peripheral Contr.

1050h–105Fh

SCI1 Peripheral Contr.

1060h–106Fh

Timer 2A Peripheral Contr.

1070h–107Fh

ADC1 Peripheral Contr.

1080h–108Fh

Timer 2B Periph. Contr.

1090h–109Fh

Reserved

Vectors

7FBEh–7FBFh

Timer 2B

7FC0h–7FCFh

Trap 15–0

7FE0h–7FEBh

Reserved

7FECh–7FEDh

A/D Converter

7FEEh–7FEFh

Timer 2A

7FF0h–7FF1h

Serial Comm I/F TX

7FF2h–7FF3h

Serial Comm I/F RX

7FF4h–7FF5h

Timer 1

7FF6h–7FF7h

Serial Peripferal I/F

7FF8h–7FF9h

Interrupt 3

7FFAh–7FFBh

Interrupt 2

7FFCh–7FFDh

Interrupt 1

7FFEh–7FFFh

Reset

†

Reserved = the address space is reserved for future expansion.

‡

Not available (N/A) = address space is unavailable in the mode illustrated.

§

Precoded chip select outputs available on external expansion bus.

¶

Microprocessor mode is designed for ROM-less devices. ROM and EPROM devices also can be used in this mode, but all on-chip memory is ignored.

Figure 3. TMS370Cx6x Memory Map

TMS370Cx6x

8-BIT MICROCONTROLLER

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RAM/register file (RF)

Locations within RAM address space can serve as either register file or general-purpose read/write memory, program memory, or stack instructions. The TMS370Cx67 and TMS370Cx68 devices contain 1K bytes of internal RAM, mapped beginning at location 0000h and continuing through location 03FFh, which is shown in Table 5 along with ’x69 devices.

Table 5. RAM Memory Map

‘x67 and ‘x68

‘x69

RAM Size

1K Bytes

3.5K Bytes

Memory Mapped

0000h – 03FFh

0000h – 0DFFh

The first 256 bytes of RAM (0000h – 00FFh) are register files, R0 through R255 (see Figure 1). The first two registers, R0 and R1, are also called register A and B, respectively . Some instructions implicitly use register A or B; for example, the instruction LDSP (load SP) assumes that the value to be loaded into the stack pointer is contained in register B. Registers A and B are the only registers cleared on reset.

peripheral file (PF)

The TMS370Cx6x control registers contain all the registers necessary to operate the system and peripheral modules on the device. The instruction set includes some instructions that access the PF directly. These instructions designate the register by the number of the PF relative to 1000h, preceded by P0 for a hexadecimal designator or by P for a decimal designator. For example, the system control register 0 (SCCR0) is located at address 1010h; its peripheral file hexadecimal designator is P010, and its decimal designator is P16. Table 6 lists the TMS370Cx6x peripheral files.

Table 6. TMS370Cx6x Peripheral File Address Map

БББББ

Á

ADDRESS RANGE

БББББББ

Á

БББББ

Á

PERIPHERAL FILE

DESIGNAT OR

БББББББББББББББББББ

Á

DESCRIPTION

1000h–100Fh

БББББББ

P000–P00F

Reserved for factory test

1010h–101Fh

БББББББ

P010–P01F

System and EEPROM/EPROM control registers

1020h–102Fh

P020–P02F

Digital I/O port control registers

1030h–103Fh

БББББББ

P030–P03F

Serial peripheral interface registers

1040h–104Fh

БББББББ

P040–P04F

Timer 1 registers

1050h–105Fh

БББББББ

P050–P05F

Serial communication interface 1 registers

1060h–106Fh

БББББББ

P060–P06F

Timer 2A registers

1070h–107Fh

БББББББ

P070–P07F

Analog-to-digital converter 1 registers

1080h–108Fh

БББББББ

P080–P08F

Timer 2B registers

1090h–10BFh

БББББББ

P090–P0BF

Reserved

10C0h–10FFh

БББББББ

P0C0–P0FF

External peripheral control

data EEPROM

The TMS370Cx6x devices contain 256 bytes of data EEPROM, and the memory is mapped beginning at location 1F00h and continuing through location 1FFFh.

Writing to the data EEPROM module is controlled by the data-EEPROM control register (DEECTL) and the write-protection register (WPR). Programming algorithm examples are available in the

TMS370 Family User’s

Guide

(literature number SPNU127) or the

TMS370 Data Manual

(SPNS014B). The data EEPROM features

include the following:

D

Programming: – Bit, byte, and block write/erase modes

TMS370Cx6x 8-BIT MICROCONTROLLER

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data EEPROM (continued)

– Internal charge pump circuitry. No external EEPROM programming voltage supply is needed. – Control register: Data EEPROM programming is controlled by the data EEPROM control register

(DEECTL) located in the PF frame beginning at location P01A.

– In-circuit programming capability: There is no need to remove the device to program it.

D

Write-protection: Writes to the data EEPROM are disabled during the following conditions: – Reset: All programming of the data EEPROM module is halted. – Write protection active: there is one write-protect bit per 32-byte EEPROM block. – Low-power mode operation

D

Write protection can be overridden by applying 12 V to MC.

Table 7 shows the memory map of the control registers.

T able 7. Data EEPROM and Program EPROM Control Registers Memory Map

ADDRESS

SYMBOL

БББББББББББББББББББ

NAME

†

P014

EPCTLH

БББББББББББББББББББ

Program EPROM control register – high array

P015–P016

БББББББББББББББББББ

Reserved

P017

INT1

БББББББББББББББББББ

External interrupt 1 control register

P018

INT2

БББББББББББББББББББ

External interrupt 2 control register

P019

INT3

БББББББББББББББББББ

External interrupt 3 control register

P01A

DEECTL

БББББББББББББББББББ

Data EEPROM control register

P01B

БББББББББББББББББББ

Reserved

P01C

EPCTLM

Program EPROM control register – middle array

P01D

БББББББББББББББББББ

Reserved

P01E

EPCTLL

БББББББББББББББББББ

Program EPROM control register – low array

†

For the 24K- and 32K-byte EPROM device, the program memory is controlled by P01C and P01E; for the 48K-byte EPROM device, the program memory is controlled by P014, P01C, and P01E.

program EPROM

The ‘370C767 program EPROM consists of 24K bytes that are made up of one 16K-byte array and one 8K-byte array of EPROM; the 16K-byte array is located at address locations 2000h through 5FFFh, and the 8K-byte array is located at address locations 6000h through 7FFFh. The ‘370C768 program EPROM consists of 32K bytes that are made up of two 16K-byte arrays of EPROM; the first 16K-byte array is located at address locations 2000h through 5FFFh, and the second 16K-byte array is located at address locations 6000h through 9FFFh. The ’370C769 program EPROM consists of 48K bytes that are made up of three 16K-byte arrays of EPROM; the first 16K-byte array is located at address locations 2000h through 5FFFh, the second 16K-byte array is located at address locations 6000h through 9FFFh, the third 16K-byte array is located at address locations A000h through DFFFh as shown in Table 8.

TMS370Cx6x

8-BIT MICROCONTROLLER

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program EPROM (continued)

T able 8. EPROM Memory Map

’767

’768

’769

ÁÁ

Á

EPROM size

БББББББ

Á

24K Bytes

БББББББ

Á

32K Bytes

ББББББББББББ

Á

48K Bytes

Memory mapped

16K

2000h–5FFFh8K6000h–7FFFh

First 16K

2000h–5FFFh

Second 16K

6000h–9FFFh

First 16K

2000h–5FFFh

Second 16K

6000h–9FFFh

Third 16K

A000h–DFFFh

ÁÁ

Á

Contol registers

ÁÁÁ

Á

EPCTLL

P01E

ÁÁÁ

Á

EPCTLM

P01C

ÁÁÁ

Á

EPCTLL

P01E

ÁÁÁ

Á

EPCTLM

P01C

ÁÁÁÁ

Á

EPCTLL

P01E

ÁÁÁ

Á

EPCTLM

P01C

ÁÁÁ

Á

EPCTLH

P014

The EPROM memory map in Table 8 expresses the following:

– For the 24K-byte EPROM, the 16K-byte array is controlled by EPCTLL register, located at 101Eh

(P01E); the 8K-byte array is controlled by EPCTLM register, located at 101Ch (P01C). – For the 32K-byte EPROM, the first 16-byte array is controlled by EPCTLL register, located at 101Eh

(P01E); the second 16K-byte array is controlled by EPCTLM register, located at 101Ch (P01C). – For the 48K-bytes EPROM, the first 16K-byte array is controlled by EPCTLL register, located at 101Eh

(P01E); the second 16K-byte array is controlled by EPCTLM register, located at 101Ch (P01C); the third

16K-byte array is controlled by EPCTLH register, located at 1014h (P014).

Reading the program-EPROM modules is identical to reading other internal memory . During programming, the EPROM is controlled by the EPCTL. The program EPROM modules’ features include:

D

Programming – In-circuit programming capability if V

PP

is applied to MC

– Control register: Program EPROM programming is controlled by the program EPROM control registers

(EPCTLL, EPCTLM, and EPCTLH) located in the PF frame as shown in Table 7. – Programming one EPROM module while executing the other

D

Write protection: Writes to the program EPROM are disabled under the following conditions: – Reset: All programming to the EPROM module is halted. – Low-power modes – 13 V not applied to MC

program ROM

The program ROM consists of 24K, 32K or 48K bytes of mask-programmable ROM. The program ROM is used for permanent storage of data or instructions. Programming of the mask ROM is performed at the time of device fabrication. Table 9 shows the program ROM memory map.

Table 9. ROM Memory Map

†

‘067

’068

‘069

ROM Size

24K Bytes

32K Bytes

48K Bytes

Memory Mapped

2000h – 7FFFh

2000h – 9FFFh

2000h – DFFFh

†

Memory addresses 7FE0h through 7FEBh are reserved for Texas Instruments Incorporated. Memory addresses 7FBEh through 7FBFh and 7FECh through 7FFFh are reserved for interrupts and reset vectors. Trap vectors, used with TRAP0 through TRAP15 instructions, are located at addresses 7FC0h and 7FCFh.

TMS370Cx6x 8-BIT MICROCONTROLLER

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system reset

The system-reset operation ensures an orderly start-up sequence for the TMS370Cx6x CPU-based device. There are up to three different actions that can cause a system reset to the device. Two of these actions are internally generated, while one (RESET) is controlled externally. These actions are as follows:

D

Watchdog (WD) timer. A watchdog-generated reset occurs if an improper value is written to the WD key register, or if the re-initialization does not occur before the watchdog timer timeout . See the

TMS370 Family

User’s Guide

(literature number SPNU127) or the

TMS370 Family Data Manual

(literature number

SPNS014B) for more information.

D

Oscillator reset. Reset occurs when the oscillator operates outside the recommended operating range. See the

TMS370 Family User’s Guide

(literature number SPNU127) or the

TMS370 Family Data Manual

(literature number SPNS014B) for more information.

D

External RESET Pin. A low level signal can trigger an external reset. T o ensure a reset, the external signal should be held low for one SYSCLK cycle. Signals of less than one SYSCLK can generate a reset. See the

TMS370 Family User’s Guide

(literature number SPNU127) or the

TMS370 Family Data Manual

(literature

number SPNS014B) for more information.

Once a reset source is activated, the external RESET pin is driven (active) low for a minimum of eight SYSCLK cycles. This allows the ’x6x device to reset external system components. Additionally , if a cold start (V

CC

is off for several hundred milliseconds) condition or oscillator failure occurs or RESET pin is held low , then the reset logic holds the device in a reset state for as long as these actions are active.

After a reset, the program can check the oscillator fault flag (OSC FLT FLAG, SCCR0.4), the cold start flag (COLD ST ART , SCCR0.7) and the watchdog reset (WD OVRFL INT FLAG, T1CTL2.5) to determine the source of the reset. A reset does not clear these flags. Table 10 lists the reset sources.

Table 10. Reset Sources

REGISTER

ADDRESS

PF

BIT NO.

БББББББББ

CONTROL BIT

SOURCE OF RESET

SCCR0

1010h

P010

7

БББББББББ

COLD START

Cold (power-up)

SCCR0

1010h

P010

4

OSC FLT FLAG

Oscillator out of range

T1CTL2

104Ah

P04A

5

БББББББББ

WD OVRFL INT FLAG

Watchdog timer timeout

Once a reset is activated, the following sequence of events occurs:

1. The CPU registers are initialized: ST = 00h, SP = 01h (reset state).

2. Registers A and B are initialized to 00h (no other RAM is changed).

3. The contents of the LSbyte of the reset vector (07FFh) are read and stored in the PCL.

4. The contents of the MSbyte of the reset vector (07FEh) are read and stored in the PCH.

5. Program execution begins with an opcode fetch from the address pointed to by the PC. The reset sequence takes 20 SYSCLK cycles from the time the reset pulse is released until the first opcode

fetch. During a reset, RAM contents (except for registers A and B) remain unchanged, and the module control register bits are initialized to their reset state. During RESET

, the two basic operating modes which are the microcomputer and microprocessor modes can be selected by applying the desired voltage level to the dedicated MC pin two cycles before RESET goes inactive. See the mode section for operating modes description.

TMS370Cx6x

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interrupts

The TMS370 family software programmable interrupt structure permits flexible on-chip and external interrupt configurations to meet real-time interrupt-driven application requirements. The hardware interrupt structure incorporates two priority levels as shown in Figure 4. Interrupt level 1 has a higher priority than interrupt level 2. The two priority levels can be independently masked by the global-interrupt mask bits (IE1 and IE2) of the status register.

Each system interrupt is independently configured to either the high- or low-priority chain by the application program during system initialization. Within each interrupt chain, the interrupt priority is fixed by the position of the system interrupt. However, since each system interrupt is selectively configured on either the high-or-low priority interrupt chain, the application program can elevate any system interrupt to the highest priority. Arbitration between the two priority levels is performed within the CPU. Arbitration within each of the priority chains is performed within the peripheral modules to support interrupt expansion for future modules. Pending interrupts are serviced upon completion of current instruction execution, depending on their interrupt mask and priority conditions.

The TMS370Cx6x has ten hardware system interrupts (plus RESET

) as shown in Table 11. Each system interrupt has a dedicated vector located in program memory through which control is passed to the interrupt service routines. A system interrupt can have multiple interrupt sources (e.g., SCI RXINT has two interrupt sources). All of the interrupt sources are individually maskable by local interrupt-enable control bits in the associated PF . Each interrupt source FLAG bit is individually readable for software polling or to determine which interrupt source generated the associated system interrupt. Interrupt control block diagram is illustrated in Figure 4.

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interrupts (continued)

SCI INT

RX

BRKDT RXRDY

TX

TXRDY

TXPRI

RXPRI

TIMER 2A

CPU

NMI

Logic

Enable

IE1

IE2

Level 1 INT Level 2 INT

T2A PRI

Priority

Overflow Compare1

Ext Edge Compare2 Input Capture 1

Input Capture 2

EXT INT 3

INT3 PRI

INT 3

STATUS REG

EXT INT1

INT1 PRI

INT1

SPI INT SPI PRI

SPI

EXT INT 2

INT2 PRI

INT 2

AD INT

AD PRI

A/D

TIMER 1

T1 PRI

Overflow Compare1

Ext Edge Compare2 Input Capture 1

Watchdog

TIMER 2B

T2B PRI

Overflow Compare1

Ext Edge Compare2 Input Capture 1 Input Capture 2

Figure 4. Interrupt Control

Seven of the system interrupts are generated by on-chip peripheral functions, and three external interrupts are supported. Software configuration of the external interrupts is performed through the INT1, INT2, and INT3 control registers in PF frame 1. Each external interrupt is individually software configurable for input polarity (rising or falling edge) for ease of system interface. External interrupt INT1 is software configurable as either a maskable or non-maskable interrupt. When INT1 is configured as nonmaskable, it cannot be masked by the individual- or global-enable-mask bits. Recall that the INT1 NMI bit is protected during non-privileged operation and therefore should be configured during the initialization sequence following reset. T o maximize pin flexibility , external interrupts INT2 and INT3 can be software configured as general-purpose input/output pins if the interrupt function is not required (INT1 can be similarly configured as an input pin). Table 11 shows the interrupt-vector sources, corresponding addresses, and hardware priorities.

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interrupts (continued)

T able 11. Hardware-System Interrupts

ББББББББ

Á

INTERRUPT SOURCE

БББББББ

Á

INTERRUPT FLAG

ÁÁÁÁ

Á

SYSTEM

INTERRUPT

БББББ

Á

VECTOR

ADDRESS

ÁÁÁ

Á

PRIORITY

†

ББББББББ

Á

External RESET Watchdog overflow Oscillator fault detect

БББББББ

Á

COLD START WD OVRFL INT FLAG OSC FLT FLAG

ÁÁÁÁ

Á

RESET

‡

БББББ

Á

7FFEh, 7FFFh

ÁÁÁ

Á

1

External INT1

INT1 FLAG

INT1

‡

7FFCh, 7FFDh

2

External INT2

INT2 FLAG

INT2

‡

7FFAh, 7FFBh

3

External INT3

INT3 FLAG

INT3

‡

7FF8h, 7FF9h

4

SPI RX/TX complete

SPI INT FLAG

SPIINT

7FF6h, 7FF7h

5

ББББББББ

Á

ББББББББ

Á

ББББББББ

Á

Timer 1 overflow Timer 1 compare 1 Timer 1 compare 2 Timer 1 external edge Timer 1 input capture 1 Watchdog overflow

БББББББ

Á

БББББББ

Á

БББББББ

Á

T1 OVRFL INT FLAG T1C1 INT FLAG T1C2 INT FLAG T1EDGE INT FLAG T1IC1 INT FLAG WD OVRFL INT FLAG

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

T1INT

§

БББББ

Á

БББББ

Á

БББББ

Á

7FF4h, 7FF5h

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

6

SCI RX data register full SCI RX break detect

RXRDY FLAG BRKDT FLAG

RXINT

‡

7FF2h,7FF3h

7

SCI TX data register empty

TXRDY FLAG

TXINT

7FF0h, 7FF1h

8

ББББББББ

Á

ББББББББ

Á

ББББББББ

Á

Timer 2A overflow Timer 2A compare 1 Timer 2A compare 2 Timer 2A external edge Timer 2A input capture 1 Timer 2A input capture 2

БББББББ

Á

БББББББ

Á

БББББББ

Á

T2A OVRFL INT FLAG T2AC1 INT FLAG T2AC2 INT FLAG T2AEDGE INT FLAG T2AIC1 INT FLAG T2AIC2 INT FLAG

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

T2AINT

БББББ

Á

БББББ

Á

БББББ

Á

7FEEh, 7FEFh

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

9

ADC1 conversion complete

AD INT FLAG

ADINT

7FECh, 7FEDh

10

ББББББББ

Á

ББББББББ

Á

ББББББББ

Á

Timer 2B overflow Timer 2B compare 1 Timer 2B compare 2 Timer 2B external edge Timer 2B input capture 1 Timer 2B input capture 2

БББББББ

Á

БББББББ

Á

БББББББ

Á

T2B OVRFL INT FLAG T2BC1 INT FLAG T2BC2 INT FLAG T2BEDGE INT FLAG T2BIC1 INT FLAG T2BIC2 INT FLAG

ÁÁÁÁ

Á

ÁÁÁÁ

Á

ÁÁÁÁ

Á

T2BINT

БББББ

Á

БББББ

Á

БББББ

Á

7FBEh, 7FBFh

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

11

†

Relative priority within an interrupt level

‡

Release microcontroller from STANDBY and HALT low-power modes

§

Release microcontroller from STANDBY low-power mode

privileged operation and EEPROM write-protection override

The TMS370Cx6x family has significant flexibility to enable the designer to software-configure the system and peripherals to meet the requirements of a broad variety of applications. The nonprivileged mode of operation ensures the integrity of the system configuration, once it is defined for an application. Following a hardware reset, the TMS370Cx6x operates in the privileged mode, where all peripheral file registers have unrestricted read/write access, and the application program configures the system during the initialization sequence following reset. As the last step of system initialization, the PRIVILEGE DISABLE bit (SCCR2.0) should be set to 1 to enter the nonprivileged mode, disabling write operations to specific configuration control bits within the peripheral file. Table 12 lists the system configuration bits that are write-protected during the nonprivileged mode and must be configured by software prior to exiting the privileged mode.

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privileged operation and EEPROM write-protection override (continued)

Table 12. Privileged Bits

REGISTER

†

NAME

LOCATION

CONTROL BIT

ÁÁÁ

SCCRO

ÁÁÁ

Á

P010.5 P010.6

БББББББББ

Á

PF AUTOWAIT OSC POWER

SCCR1

P011.2 P011.4

MEMORY DISABLE AUTOWAIT DISABLE

ÁÁÁ

SCCR2

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

P012.0 P012.1 P012.3 P012.4 P012.6 P012.7

БББББББББ

Á

БББББББББ

Á

БББББББББ

Á

PRIVILEGE DISABLE INT1 NMI CPU STEST BUS STEST PWRDWN/IDLE HALT/STANDBY

ÁÁÁ

SPIPRI

ÁÁÁ

Á

ÁÁÁ

Á

P03F.5 P03F.6 P03F.7

БББББББББ

Á

БББББББББ

Á

SPI ESPEN SPI PRIORITY SPI STEST

ÁÁÁ

SCIPRI

ÁÁÁ

Á

P05F.4 P05F.5 P05F.6 P05F.7

БББББББББ

Á

SCI ESPEN SCIRX PRIORITY SCITX PRIORITY SCI STEST

ÁÁÁ

T1PRI

ÁÁÁ

Á

P04F.6 P04F.7

БББББББББ

Á

T1 PRIORITY T1 STEST

ÁÁÁ

T2APRI

ÁÁÁ

Á

P06F.6 P06F.7

БББББББББ

Á

T2A PRIORITY T2A STEST

ÁÁÁ

ADPRI

ÁÁÁ

Á

P07F.5 P07F.6 P07F.7

БББББББББ

Á

AD ESPEN AD PRIORITY AD STEST

T2BPRI

P08F.6 P08F.7

T2B PRIORITY T2B STEST

†

The privileged bits are shown in a bold typeface in Table 14.

The write-protect override (WPO) mode provides an external hardware method of overriding the write-protection registers of data EEPROM on the TMS370Cx6x.The WPO mode is entered by applying a 12-V input to MC after RESET

input goes high (logic 1). The high voltage on MC during the WPO mode is not the programming voltage for the data EEPROM or program EPROM. All EEPROM programming voltages are generated on-chip. The WPO mode provides hardware system-level capability to modify the content of the data EEPROM while the device remains in the application but only while requiring a 12-V external input on the MC pin (normally not available in the end application except in a service or diagnostic environment).

low-power and IDLE modes

The TMS370Cx6x devices have two low-power modes (STANDBY and HALT) and an IDLE mode. For mask-ROM devices, low-power modes can be disabled permanently through a programmable contact at the time when the mask is manufactured.

The ST ANDBY and HALT low-power modes significantly reduce power consumption by reducing or stopping the activity of the various on-chip peripherals when processing is not required. Each of the low-power modes is entered by executing the IDLE instruction when the PWRDWN/IDLE bit in SCCR2 has been set to 1. The HALT/STANDBY bit in SCCR2 controls which low-power mode is entered.

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low-power and IDLE modes (continued)

In the ST ANDBY mode (HAL T/STANDBY = 0), all CPU activity and most peripheral module activity is stopped; however, the oscillator, internal clocks, timer 1, and the receive start-bit detection circuit of the serial communications interface remain active. System processing is suspended until a qualified interrupt (hardware RESET, external interrupt on INT1, INT2, INT3, timer 1 interrupt, or low level on the receive pin of the serial communications interface) is detected.

In the HAL T mode (HALT/STANDBY = 1), the TMS370Cx6x is placed in its lowest power-consumption mode. The oscillator and internal clocks are stopped, causing all internal activity to be halted. System activity is suspended until a qualified interrupt (hardware RESET , external interrupt on the INT1, INT2, INT3, or low level on the receive pin of the serial communications interface) is detected. The low-power mode selection bits are summarized in Table 13.

Table 13. Low-Power/Idle Control Bits

POWER-DOWN CONTROL BITS

PWRDWN/IDLE

(SCCR2.6)

HALT/STANDBY

(SCCR2.7)

MODE SELECTED

1

0

STANDBY

1

HALT

0

X

IDLE

X = don’t care

When low-power modes are disabled through a programmable contact in the mask-ROM devices, writing to the SCCR2.6 –7 bits is ignored. In addition, if an idle instruction executes when low-power modes are disabled through a programmable contact, the device always enters the IDLE mode.

T o provide a method of always exiting low-power modes for mask-ROM devices, INT1 is automatically enabled as a nonmaskable interrupt (NMI) during low-power modes when the hard watchdog mode is selected. This means that the NMI always is generated, regardless of the interrupt-enable flags.

The following information is preserved throughout both the STANDBY and HALT modes: RAM (register file), CPU registers (stack pointer, program counter , and status register), I/O pin direction and output data, and status registers of all on-chip peripheral functions. Since all CPU instruction processing is stopped during the STANDBY and HALT modes, the clocking of the watchdog timer is inhibited.

clock modules

The ‘x6x family provides two clock options which are referred to as divide-by-1 (PLL) and divide-by-4 (standard oscillator). Both the divide-by-1 and divide-by-4 options are configurable during the manufacturing process of a TMS370 microcontroller. The ‘x6x ROM-masked devices offer both options to meet system engineering requirements. Only one of the two clock options is allowed on each ROM device. An EPROM has only the divide-by-1.

The divide-by-1 clock module option provides the capability for reduced electromagnetic interference (EMI) with no added cost.

The divide-by-1 provides a 1-to-1 match between the external resonator frequency and the internal system clock (SYSCLK) frequency. The divide-by-4 produces a SYSCLK which is one-fourth the frequency of the external resonator. Inside the divide-by-1 module, the frequency of the external resonator is multiplied by four . The clock module then divides the resulting signal by four to provide the four-phased internal system clock signals. The resulting SYSCLK is equal to the resonator frequency. The frequencies are formulated as follows:

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clock modules (continued)

Divide-by-4 option : SYSCLK

+

external resonator frequency

4

+

CLKIN

4

Divide-by-1 option : SYSCLK

+

external resonator frequency 4

4

+

CLKIN

The main advantage of choosing a divide-by-1 oscillator is the improved EMI performance. The harmonics of low-speed resonators extend through less of the emissions spectrum than the harmonics of faster resonators. The divide-by-1 provides the capability of reducing the resonator speed by four times, and this results in a steeper decay of emissions produced by the oscillator.

system configuration registers

Table 14 contains system configuration and control functions and registers for controlling EEPROM programming. The privileged bits are shown in bold typeface and shaded.

Table 14. Peripheral File Frame 1: System Configuration Registers

PF

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

REG

P010

COLD

START

OSC

POWER

PF AUTO

WAIT

OSC FLT

FLAG

MC PIN

WPO

MC PIN

DATA

—

µP/µC MODE

SCCR0

Á

P011

ÁÁÁ

Á

—

ÁÁ

Á

—

ÁÁÁ

Á

—

AUTOWAIT

DISABLE

ÁÁ

Á

—

MEMORY

DISABLE

ÁÁ

Á

—

ÁÁÁ

Á

—

ÁÁ

Á

SCCR1

P012

HALT/

STANDBY

PWRDWN/

IDLE

—

BUS

STEST

CPU

STEST

—

INT1

NMI

PRIVILEGE

DISABLE

SCCR2

P013 Reserved P014

BUSY

VPPS

—

W0

EXE

EPCTLH

Á

P015

to

P016

Reserved

ÁÁ

Á

P017

ÁÁÁ

Á

INT1

FLAG

ÁÁ

Á

INT1

PIN DATA

ÁÁÁ

Á

—

ÁÁ

Á

—

ÁÁ

Á

—

ÁÁÁ

Á

INT1

POLARITY

ÁÁ

Á

INT1

PRIORITY

ÁÁÁ

Á

INT1

ENABLE

ÁÁ

Á

INT1

Á

P018

ÁÁÁ

Á

INT2

FLAG

ÁÁ

Á

INT2

PIN DATA

ÁÁÁ

Á

—

ÁÁ

Á

INT2

DATA DIR

ÁÁ

Á

INT2

DATA OUT

ÁÁÁ

Á

INT2

POLARITY

ÁÁ

Á

INT2

PRIORITY

ÁÁÁ

Á

INT2

ENABLE

ÁÁ

Á

INT2

P019

INT3

FLAG

INT3

PIN DATA

—

INT3

DATA DIR

INT3

DATA OUT

INT3

POLARITY

INT3

PRIORITY

INT3

ENABLE

INT3

P01A

BUSY

—

AP

W1W0

EXE

DEECTL P01B Reserved P01C

BUSY

VPPS

—

W0

EXE

EPCTLM P01D Reserved P01E

BUSY

VPPS

—

W0

EXE

EPCTLL

P01F Reserved

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digital port control

Peripheral file frame 2 contains the digital I/O pin configuration and control registers. T able 15 lists the specific addresses, registers, and control bits within this peripheral file frame.

Table 15. Peripheral File Frame 2: Digital Port Control Registers

PF

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

REG

P020

Reserved

APORT1

P021

Port A Control Register 2

APORT2

P022

Port A Data

ADATA

P023

Port A Direction

ADIR

P024

Reserved

BPORT1

P025

Port B Control Register 2

BPORT2

P026

Port B Data

BDATA

P027

Port B Direction

BDIR

P028

Reserved

CPORT1

P029

Port C Control Register 2

CPORT2

P02A

Port C Data

CDATA

P02B

Port C Direction

CDIR

P02C

Port D Control Register 1

—

DPORT1

P02D

Port D Control Register 2

†

—

DPORT2

P02E

Port D Data

—

DDATA

P02F

Port D Direction

—

DDIR

†

To configure pin D3 as SYSCLK, set port D control register 2 = 08h.

Table 16. Port Configuration Register Setup

INPUT OUTPUT FUNCTION A

FUNCTION B

(µP MODE)

PORT PIN

XPORT1 = 0‡

XPORT2 = 0

XDATA = y

XDIR = 0

XPORT1 = 0

‡

XPORT2 = 0

XDATA = q

XDIR = 1

XPORT1 = 0

‡

XPORT2 = 1

XDATA = x

XDIR = x

XPORT1 = 1

‡

XPORT2 = 1

XDATA = x

XDIR = x A 0–7 Data In y Data Out q Data Bus Reserved B 0–7 Data In y Data Out q Low ADDR Reserved C 0–7 Data In y Data Out q Hi ADDR Reserved

D

3 4 5 6 7

Data In y Data Out q

SYSCLK

R/W CSPF CSH1 CSE1

SYSCLK

R/W

—

EDS

WAIT

XPORT1 = 1

XPORT2 =0

XDATA = x

XDIR = x

Not defined

‡

DPORT only

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timer 1 module

The programmable timer 1 (T1) module of the TMS370Cx6x provides the designer with the enhanced timer resources required to perform real-time system control. The T1 module contains the general-purpose timer and the watchdog (WD) timer. The two independent 16-bit timers (T1 and WD) allow program selection of input clock sources (real-time, external-event, or pulse-accumulate) with multiple 16-bit registers (input-capture and compare) for special timer function control. The T1 module includes three external device pins that can be used for multiple counter functions (operation mode dependent) or used as general-purpose I/O pins. The T1 module is shown in Figure 5.

T1IC/CR

Edge

Select

16-Bit

Counter

T1EVT

MUX

16-Bit

Register

T1PWM

PWM

Toggle

16

16-Bit

Watchdog Counter

(Aux. Timer)

Interrupt

Logic

Capt/Comp

16-Bit

Register

Compare

Interrupt

Logic

8-Bit

Prescaler

Figure 5. Timer 1 Block Diagram

D

Three T1 I/O pins – T1IC/CR: Timer 1 input capture/counter reset input pin, or general-purpose bidirectional I/O pin – T1PWM: Timer 1 pulse-width-modulation (PWM) output pin, or general-purpose bidirectional I/O pin – T1EVT: Timer 1 event input pin, or general-purpose bidirectional I/O pin

D

Two operation modes: – Dual–compare mode: Provides PWM signal – Capture/compare mode: Provides input capture pin

D

One 16-bit general-purpose resettable counter

D

One 16-bit compare register with associated compare logic

D

One 16-bit capture / compare register, which, depending on the mode of operation, operates as either capture or compare register

D

One 16-bit watchdog counter can be used as an event counter, a pulse accumulator, or an interval timer if watchdog feature is not needed.

D

Prescaler/clock sources that determine one of eight clock sources for general-purpose timer

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timer 1 module (continued)

D

Selectable edge-detection circuitry that, depending on the mode of operation, senses active transitions on the input capture pins (T1IC/CR)

D

Interrupts that can be generated on the occurrence of: – A capture – A compare equal – A counter overflow – An external edge detection

D

Sixteen T1 module control registers: Located in the PF frame beginning at address P040

TMS370Cx6x 8-BIT MICROCONTROLLER

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timer 1 module (continued)

Table 17 shows the T1 module control register memory map.

Table 17. Timer 1 Module Register Memory Map

PF

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

REG

Modes: Dual-Compare and Capture/Compare

P040

Bit 15

T1 Counter MSbyte

Bit 8

T1CNTR

P041

Bit 7

T1 Counter LSbyte

Bit 0

P042

Bit 15

Compare Register MSbyte

Bit 8

T1C

P043

Bit 7

Compare Register LSbyte

Bit 0

P044

Bit 15

Capture/Compare Register MSbyte

Bit 8

T1CC

P045

Bit 7

Capture/Compare Register LSbyte

Bit 0

P046

Bit 15

Watchdog Counter MSbyte

Bit 8

WDCNTR

P047

Bit 7

Watchdog Counter LSbyte

Bit 0

P048

Bit 15

Watchdog Reset Key

Bit 0

WDRST

Á

P049

ÁÁÁ

Á

ÁÁÁ

Á

WD OVRFL

TAP SEL

†

ÁÁ

Á

ÁÁ

Á

WD

INPUT

SELECT2

†

ÁÁÁ

Á

ÁÁÁ

Á

WD

INPUT

SELECT1

†

ÁÁ

Á

ÁÁ

Á

WD

INPUT

SELECT0

†

ÁÁ

Á

ÁÁ

Á

—

ÁÁÁ

Á

ÁÁÁ

Á

T1

INPUT

SELECT2

ÁÁ

Á

ÁÁ

Á

T1

INPUT

SELECT1

ÁÁÁ

Á

ÁÁÁ

Á

T1 INPUT SELECT0

ÁÁ

Á

ÁÁ

Á

T1CTL1

P04A

WD OVRFL

RST ENA

†

WD OVRFL

INT ENA

WD OVRFL

INT FLAG

T1 OVRFL

INT ENA

T1 OVRFL INT FLAG

—

T1 SW

RESET

T1CTL2

Mode: Dual-Compare

Á

P04B

ÁÁÁ

Á

T1EDGE

INT FLAG

ÁÁ

Á

T1C2

INT FLAG

ÁÁÁ

Á

T1C1

INT FLAG

ÁÁ

Á

—

ÁÁ

Á

—

ÁÁÁ

Á

T1EDGE INT ENA

ÁÁ

Á

T1C2

INT ENA

ÁÁÁ

Á

T1C1

INT ENA

ÁÁ

Á

T1CTL3

P04C

T1

MODE = 0

T1C1

OUT ENA

T1C2

OUT ENA

T1C1

RST ENA

T1CR

OUT ENA

T1EDGE

POLARITY

T1CR

RST ENA

T1EDGE

DET ENA

T1CTL4

Mode: Capture/Compare

Á

P04B

ÁÁÁ

Á

T1EDGE

INT FLAG

ÁÁ

Á

—

ÁÁÁ

Á

T1C1

INT FLAG

ÁÁ

Á

—

ÁÁ

Á

—

ÁÁÁ

Á

T1EDGE INT ENA

ÁÁ

Á

—

ÁÁÁ

Á

T1C1

INT ENA

ÁÁ

Á

T1CTL3

P04C

T1

MODE = 1

T1C1

OUT ENA

—

T1C1

RST ENA

—

T1EDGE

POLARITY

—

T1EDGE

DET ENA

T1CTL4

Modes: Dual-Compare and Capture/Compare

Á

P04D

ÁÁÁ

Á

—

ÁÁ

Á

—

ÁÁÁ

Á

—

ÁÁ

Á

—

ÁÁ

Á

T1EVT

DATA IN

ÁÁÁ

Á

T1EVT

DATA OUT

ÁÁ

Á

T1EVT

FUNCTION

ÁÁÁ

Á

T1EVT

DATA DIR

ÁÁ

Á

T1PC1

P04E

T1PWM

DATA IN

T1PWM

DATA OUT

T1PWM

FUNCTION

T1PWM

DATA DIR

T1IC/CR

DATA IN

T1IC/CR

DATA OUT

T1IC/CR

FUNCTION

T1IC/CR

DATA DIR

T1PC2

Á

P04F T1 STEST

T1

PRIORITY

ÁÁÁ

Á

—

ÁÁ

Á

—

ÁÁ

Á

—

ÁÁÁ

Á

—

ÁÁ

Á

—

ÁÁÁ

Á

—

ÁÁ

Á

T1PRI

†

Once the WD OVRFL RST ENA bit is set, these bits cannot be changed until a reset; this applies only to the standard watchdog and to simple counter. In the hard watchdog, these bits can be modified at any time; the WD INPUT SELECT2 bits are ignored.

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timer 1 module (continued)

The timer 1 capture/compare mode block diagram is illustrated in Figure 6. The annotations in Figure 6 identify the register and the bit(s) in the peripheral frame. For example, the actual address of T1CTL2.0 is 104Ah, bit 0, in the T1CTL2 register.

T1CTL4.2

16

Compare=

Edge

Select

T1IC/CR

T1EDGE POLARITY

T1EDGE DET ENA

Prescale

Clock

Source

16-Bit

Counter

MSB

LSB

T1CNTR.15-0

Reset

T1C1

RST ENA

T1 SW

RESET

T1CTL2.0

T1CTL4.4

T1PC2.3-0

T1CTL4.0

T1EDGE INT FLAG

T1EDGE INT ENA

T1CTL3.7

T1CTL3.2

T1 OVRFL INT FLAG

T1 OVRFL INT ENA

T1CTL2.3

T1CTL2.4

T1C1 INT FLAG

T1C1 INT ENA

T1CTL3.5

T1CTL3.0

T1C1

OUT ENA

T1PWM

T1CTL4.6

Toggle

T1PC2.7-4

16-Bit

Capt/Comp

MSB

LSB

Register

T1CC.15-0

T1C.15-0

16-Bit

Compare

MSB

LSB

Register

T1 PRIORITY

T1PRI.6

Level 1 Int Level 2 Int

0

1

Figure 6. Capture/Compare Mode

TMS370Cx6x 8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

timer 1 module (continued)

The timer 1 dual-compare mode block diagram is illustrated in Figure 7. The annotations in Figure 7 identify the register and the bit(s) in the peripheral frame. For example, the actual address of T1CTL2.0 is 104Ah, bit 0, in the T1CTL2 register.

T1CTL4.1

T1CTL4.4

Prescaler

Clock

Source

16-Bit

Counter

16-Bit

16

Compare=

Reset

T1C1

RST ENA

T1 SW

RESET

Edge

Select

T1EDGE DET ENA

Output Enable

Capt/Comp

Register

MSB

LSB

MSB

LSB

T1CR OUT ENA

T1IC/CR

T1EDGE POLARITY

Toggle

16-Bit

Compare

MSB

LSB

Register

T1CC.15-0

T1C1 INT FLAG

T1CTL3.0

T1CTL3.5

T1C1 INT ENA

T1C2 INT FLAG

T1CTL3.1

T1CTL3.6

T1C2 INT ENA

T1 OVRFL INT FLAG

T1CTL2.4

T1CTL2.3

T1 OVRFL INT ENA

T1EDGE INT FLAG

T1CTL3.2

T1CTL3.7

T1EDGE INT ENA

T1 PRIORITY

T1C2 OUT ENA

T1C1 OUT ENA

T1CTL4.3

T1CTL4.6

T1CTL4.5

T1PWM

T1PC2.7-4

T1PRI.6

T1C.15-0

T1CNTR.15-0

T1CTL2.0

T1CR

RST ENA

T1PC2.3-0

T1CTL4.0

T1CTL4.2

Level 1 Int Level 2 Int

0 1

Figure 7. Dual-Compare Mode

TMS370Cx6x

8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

29

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

timer 1 module (continued)

The TMS370Cx6x device includes a 24-bit watchdog (WD) timer, contained in the T1 module, which can be software programmed as an event counter, pulse accumulator, or interval timer if the watchdog function is not desired. The WD function is to monitor software and hardware operation and to implement a system reset when the WD counter is not serviced properly (WD counter overflow or WD counter is reinitialized by an incorrect value). The WD can be configured as one of three mask options: standard watchdog, hard watchdog, or simple counter.

D

Standard watchdog configuration (see Figure 8) – for ’76xA EPROM and mask-ROM devices – Watchdog mode

– Ten different WD overflow rates ranging from 6.55 ms to 3.35 s at 5-MHz SYSCLK – A WD reset key (WDRST) register is used to clear the watchdog counter (WDCNTR) when a correct

value is written.

– Generates a system reset if an incorrect value is written to the watchdog reset key or if the counter

overflows

– A watchdog overflow flag (WD OVRFL INT FLAG) bit that indicates whether the WD timer initiated a

system reset

– Non-watchdog mode

– Watchdog timer can be configured as an event counter, pulse accumulator, or an interval timer.

16-Bit

Watchdog Counter

Reset

Prescaler

Clock

Watchdog Reset Key

WD OVRFL

TAP SEL

WD OVRFL

RST ENA

System Reset

T1CTL1.7

WDRST.7-0

WDCNTR.15-0

T1CTL2.7

T1CTL2.5

WD OVRFL

Interrupt

T1CTL2.6

WD OVRFL

INT FLAG

Figure 8. Standard Watchdog

TMS370Cx6x 8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

timer 1 module (continued)

D

Hard watchdog configuration (see Figure 9) – for mask-ROM devices – Eight different WD overflow rates ranging from 26.2 ms to 3.35 s at 5-MHz SYSCLK – A WD reset key (WDRST) register is used to clear the watchdog counter (WDCNTR) when a correct

value is written.

– Generates a system reset if an incorrect value is written to the watchdog reset key or if the counter

overflows – Automatic activation of the WD timer upon power-up reset – INT1 is enabled as nonmaskable interrupt during low-power modes – A watchdog overflow flag (WD OVRFL INT FLAG) bit that indicates whether the WD timer initiated a

system reset

16-Bit

Watchdog Counter

Reset

Prescaler

Clock

Watchdog Reset Key

WD OVRFL

TAP SEL

System Reset

T1CTL1.7

WDRST.7-0

WDCNTR.15-0

T1CTL2.5

WD OVRFL

INT FLAG

Figure 9. Hard Watchdog

TMS370Cx6x

8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

timer 1 module (continued)

D

Simple-counter configuration (see Figure 10) – for mask-ROM devices only – Simple counter can be configured as an event counter, pulse accumulator, or an interval timer

16-Bit

Watchdog Counter

Reset

Prescaler

Clock

Watchdog Reset Key

WD OVRFL

TAP SEL

T1CTL1.7

WDRST.7-0

WDCNTR.15-0

T1CTL2.5

WD OVFL INT FLAG

WD OVRFL

INT ENA

Interrupt

T1CTL2.6

Figure 10. Simple Counter

timer 2n modules (T2A and T2B)

The TMS370Cx6x device includes two 16-bit general-purpose timer 2 modules (T2A and T2B). The T2A or T2B are referred to as T2n throughout this section. The T2n module contains a 16-bit resettable counter, 16-bit compare register with associated compare logic, 16-bit capture register, and a 16-bit register that functions as a capture register in one mode and as a compare register in the other mode. The T2n module adds additional timers that provide event counts, input captures, and compare functions. The T2n module includes three external-device pins that can be dedicated as timer functions or used as general-purpose I/O pins. The T2n module is shown in Figure 11.

TMS370Cx6x 8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

timer 2n modules (T2A and T2B) (continued)

16–Bit

Register

16

INT

Logic

Capt/Comp

16–Bit

Capture

Edge

Detect

PWM

Toggle

T2nIC2/PWM

(Dual-Compare Mode)

Edge

Detect

Register

16–Bit

Register

Compare

16–Bit

Counter

Clock

Select

(Dual-Capture Mode)

T2nIC1/CR

T2nIC2/PWM

T2nEVT

Figure 11. Timer 2n Block Diagram

The T2n module features include the following:

D

Three T2A I/O pins – T2nIC1/CR: Timer 2n input capture 1/counter-reset input pin, or general-purpose bidirectional I/O pin – T2nIC2/PWM: Timer 2n input capture 2/pulse-width-modulation (PWM) output pin, or general-purpose

bidirectional I/O pin – T2nEVT: Timer 2n event-input pin, or general-purpose bidirection I/O pin

D

Two operation modes: – Dual-compare mode: Provides PWM signal – Dual-capture mode: Provides input-capture pin

D

One 16-bit general-purpose resettable counter

D

One 16-bit compare register with associated compare logic

D

One 16-bit capture register with associated capture logic

D

One 16-bit capture/compare register, which, depending on the mode of operation, operates as either capture or compare registers

D

T2n clock sources can be any of the following: – System clock – No clock (the counter is stopped) – External clock synchronized to the system clock (event counter) – System clock while external input is high (pulse accumulation)

TMS370Cx6x

8-BIT MICROCONTROLLER

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

timer 2n modules (T2A and T2B) (continued)

D

Selectable edge-detection circuitry that, depending on the mode of operation, senses active transitions on the input-capture pins (T2nIC1/CR)

D

Interrupts that can be generated on the occurrence of: – A compare equal for dedicated-compare register – A compare equal for capture-compare register – A counter overflow – An external edge 1 detection – An external edge 2 detection

D

Fourteen control registers for each Timer 2 module: Located in the PF frame beginning at address P060 and P080 for T2A and T2B, respectively.

The timer 2n module control registers are illustrated in Table 18.

Table 18. Timer 2n Module Register Memory Map

ÁÁ

PF

ÁÁ

PF

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

REG

Modes: Dual-Compare and Dual-Capture

P060

ÁÁ

P080

Bit 15

T2n Counter MSbyte

Bit 8

P061

ÁÁ

P081

Bit 7

T2n Counter LSbyte

Bit 0

T2nCNTR

P062

ÁÁ

P082

Bit 15

Compare Register MSbyte

Bit 8

P063

ÁÁ

P083

Bit 7

Compare Register LSbyte

Bit 0

T2nC

P064

ÁÁ

P084

Bit 15

Capture/Compare Register MSbyte

Bit 8

P065

ÁÁ

P085

Bit 7

Capture/Compare Register LSbyte

Bit 0

T2nCC

P066

ÁÁ

P086

Bit 15

Capture Register 2 MSbyte

Bit 8

P067

P087

Bit 7

Capture Register 2 LSbyte

Bit 0

T2nIC

Á

P06A

ÁÁ

P08A

ÁÁÁ

Á

ÁÁÁ

Á

—

ÁÁ

Á

ÁÁ

Á

—

ÁÁÁ

Á

ÁÁÁ

Á

—

ÁÁ

Á

ÁÁ

Á

T2n OVRFL

INT ENA

ÁÁÁ

Á

ÁÁÁ

Á

T2n

OVRFL

INT FLAG

ÁÁ

Á

ÁÁ

Á

T2n

INPUT

SELECT1

ÁÁ

Á

ÁÁ

Á

T2n INPUT

SELECT0

ÁÁ

Á

ÁÁ

Á

T2n SW

RESET

Á

T2nCTL1

Mode: Dual-Compare

Á

P06B

ÁÁ

P08B

ÁÁÁ

Á

T2nEDGE1

INT FLAG

ÁÁ

Á

T2nC2

INT FLAG

ÁÁÁ

Á

T2nC1

INT FLAG

ÁÁ

Á

—

ÁÁÁ

Á

—

ÁÁ

Á

T2nEDGE1

INT ENA

ÁÁ

Á

T2nC2

INT ENA

ÁÁ

Á

T2nC1

INT ENA

Á

T2nCTL2

P06C

ÁÁ

P08C

T2n

MODE = 0

T2nC1

OUT ENA

T2nC2

OUT ENA

T2nC1

RST ENA

T2nEDGE1

OUT ENA

T2nEDGE1

POLARITY

T2nEDGE1

RST ENA

T2nEDGE1

DET ENA

T2nCTL3

Mode: Dual-Capture

Á

P06B

ÁÁ

P08B

ÁÁÁ

Á

T2nEDGE1

INT FLAG

ÁÁ

Á

T2nEDGE2

INT FLAG

ÁÁÁ

Á

T2nC1

INT FLAG

ÁÁ

Á

—

ÁÁÁ

Á

—

ÁÁ

Á

T2nEDGE1

INT ENA

ÁÁ

Á

T2nEDGE2

INT ENA

ÁÁ

Á

T2nC1

INT ENA

Á

T2nCTL2

P06C

ÁÁ

P08C

T2n

MODE = 1

—

T2nC1

RST ENA

T2nEDGE2 POLARITY

T2nEDGE1

POLARITY

T2nEDGE2

DET ENA

T2nEDGE1

DET ENA

T2nCTL3

Modes: Dual-Compare and Dual-Capture

P06D

ÁÁ

P08D

—

T2nEVT

DATA IN

T2nEVT

DATA OUT

T2nEVT

FUNCTION

T2nEVT

DATA DIR

T2nPC1

Á

P06E

ÁÁ

P08E

ÁÁÁ

Á

T2nIC2/PWM

DATA IN

ÁÁ

Á

T2nIC2/PWM

DATA OUT

ÁÁÁ

Á

T2nIC2/PWM

FUNCTION

ÁÁ

Á

T2nIC2/PWM

DATA DIR

ÁÁÁ

Á

T2nIC1/CR

DATA IN

ÁÁ

Á

T2nIC1/CR DATA OUT

ÁÁ

Á

T2nIC1/CR FUNCTION

ÁÁ

Á

T2nIC1/CR

DATA DIR

Á

T2nPC2

P06F

ÁÁ

P08F T2n STEST

T2n

PRIORITY

—

T2nPRI

ÁÁ

TMS370Cx6x 8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

timer 2n modules (T2A and T2B) (continued)

The timer 2n dual-compare mode block diagram is illustrated in Figure 12. The annotations on the diagram identify the register and the bit(s) in the peripheral frame. For example, the actual address of T2nCTL2.0 is 106Bh (n = A) or 108Bh (n = B), bit 0, in the T2nCTL2 register.

16

T2nC.15-0

T2nCTL2.1

T2nCTL3.2

T2nCTL3.1

T2nCTL3.5

T2nCTL3.3

Clock

Source

16-Bit

Counter

16-Bit

Compare=

Reset

T2nC1

RST ENA

T2n SW

RESET

Edge 1

Select

T2nEDGE1 DET ENA

Output Enable

Capt/Comp

Register

MSB

LSB

MSB

LSB

T2nEDGE1 OUT ENA

T2nIC1/CR

T2nEDGE1 POLARITY

Toggle

16-Bit

Compare

MSB

LSB

Register

T2nCC.15-0

T2nC1 INT FLAG

T2nCTL2.0

T2nCTL2.5

T2nC1 INT ENA

T2nC2 INT FLAG

T2nCTL2.6

T2nC2 INT ENA

T2n OVRFL INT FLAG

T2nCTL1.4

T2n CTL1.3

T2n OVRFL INT ENA

T2nEDGE1 INT FLAG

T2nCTL2.2

T2n CTL2.7

T2nEDGE1 INT ENA

T2n PRIORITY

T2nC2 OUT ENA

T2nC1 OUT ENA

T2nCTL3.6

T2nIC2/PWM

T2nPC2.7-4

T2nPRI.6

T2nCNTR.15-0

T2nCTL1.0

T2nCTL3.4

T2nEDGE1

RST ENA

T2nPC2.3-0

T2nCTL3.0

Level 1 Int Level 2 Int

0 1

Figure 12. Dual-Compare Mode

TMS370Cx6x

8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

35

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

timer 2n modules (T2A and T2B) (continued)

The timer 2n dual-capture mode block diagram is illustrated in Figure 13. The annotations on the diagram identify the register and the bit(s) in the peripheral frame. For example, the actual address of T2nCTL2.0 is 106Bh (n = A) or 108Bh (n = B), bit 0, in the T2nCTL2 register.

T2nCTL2.5

T2nCTL3.3

0

Capt/Comp

T2nPC2.3–0

Compare =

Clock

Source

16-Bit

Counter

MSB

LSB

T2nCNTR.15–0

Reset

T2nC1

RST ENA

T2n SW RESET

T2nCTL1.0

T2nCTL3.4

T2nCTL2.6

T2nCTL2.1

T2nCTL2.7

T2nCTL2.2

T2nCTL2.0

16-Bit

MSB

LSB

Register 1

T2nC.15–0

16-Bit

Compare

MSB

LSB

Register

T2n PRIORITY

Level 1 Int

Level 2 Int

1

T2nCTL1.3

T2nCTL1.4

16-Bit

Capture

MSB

LSB

Register 23

T2nIC.15–0

Edge 2

Select

T2nIC2/PWM

T2nPC2.7–4

T2nCTL3.1

Edge1 Select

T2nIC1/CR

T2nCTL3.2

T2nCTL3.0

16

T2nEDGE1 POLARITY

T2nEDGE1 DET ENA

T2nEDGE2 DET ENA

T2nEDGE2 POLARITY

T2nC1 INT FLAG

T2nC1 INT ENA

T2n OVRFL INT FLAG

T2n OVRFL INT ENA

T2nEDGE1 INT FLAG

T2nEDGE1 INT ENA

T2nEDGE2 INT ENA

T2nEDGE2 INT FLAG

T2nPRI.6

T2nCC.15–0

Figure 13. Dual-Capture Mode

TMS370Cx6x 8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

serial peripheral interface (SPI) module

The SPI is a high-speed, synchronous, serial I/O port that allows a serial bit stream of programmed length (1 to 8 bits) to be shifted into and out of the device at a programmable bit-transfer rate.The SPI is used normally for communications between the microcontroller and external peripherals or another microcontroller. Typical applications include external I/O or peripheral expansion using devices such as shift registers, display drivers, and analog-to-digital (A/D) converters. The master/slave operation of the SPI supports multi-device communications. The SPI module features include the following:

D

Three external pins: – SPISOMI: SPI slave output/master input pin or general-purpose bidirectional I/O pin – SPISIMO: SPI slave input/master output pin or general-purpose bidirectional I/O pin – SPICLK: SPI serial-clock pin or general-purpose bidirectional I/O pin

D

Two operational modes: master and slave

D

Baud rate: Eight different programmable rates – Maximum baud rate in master mode: 2.5M bps at 5-MHz SYSCLK

SPI BAUD RATE

+

SYSCLK

2 2

b

where b = bit rate in SPICCR.5-3 (range 0–7) – Maximum baud rate in slave mode: 625K bps at 5-MHz SYSCLK

For maximum slave SPI BAUD RA TE < SYSCLK/8

D

Data-word format: one to eight data bits

D

Simultaneous receiver and transmitter operation (transmit function can be disabled in software)

D

Transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithms.

D

Seven SPI module-control registers: located in control register frame beginning at address P030h

TMS370Cx6x

8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

37

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

serial peripheral interface (SPI) module (continued)

The SPI module control registers are illustrated in Table 19.

Table 19. SPI Module Control Register Memory Map

PF

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

REG

P030

SPI SW

RESET

CLOCK

POLARITY

SPI BIT

RATE2

SPI BIT

RATE1

SPI BIT

RATE0

SPI

CHAR2

SPI

CHAR1

SPI

CHAR0

SPICCR

Á

P031

ÁÁ

Á

RECEIVER

OVERRUN

ÁÁÁ

Á

SPI INT

FLAG

ÁÁ

Á

—

ÁÁÁ

Á

—

ÁÁ

Á

—

ÁÁ

Á

MASTER/

SLAVE

ÁÁÁ

Á

TALK

ÁÁ

Á

SPI INT

ENA

ÁÁ

Á

SPICTL

Á

P032

to

P036

Reserved

ÁÁ

Á

P037

RCVD7

RCVD6

RCVD5

RCVD4

RCVD3

RCVD2

RCVD1

RCVD0

SPIBUF P038 Reserved P039

SDAT7

SDAT6

SDAT5

SDAT4

SDAT3

SDAT2

SDAT1

SDAT0

SPIDAT

Á

P03A

to

P03C

Reserved

ÁÁ

Á

P03D

ÁÁ

Á

—

ÁÁÁ

Á

—

ÁÁ

Á

—

ÁÁÁ

Á

—

ÁÁ

Á

SPICLK

DATA IN

ÁÁ

Á

SPICLK

DATA OUT

ÁÁÁ

Á

SPICLK

FUNCTION

ÁÁ

Á

SPICLK

DATA DIR

ÁÁ

Á

SPIPC1

P03E

SPISIMO

DATA IN

SPISIMO

DATA OUT

SPISIMO

FUNCTION

SPISIMO

DATA DIR

SPISOMI

DATA IN

SPISOMI

DATA OUT

SPISOMI

FUNCTION

SPISOMI

DATA DIR

SPIPC2

Á

P03F

SPI

STEST

SPI

PRIORITY

SPI

ESPEN

ÁÁÁ

Á

—

ÁÁ

Á

—

ÁÁ

Á

—

ÁÁÁ

Á

—

ÁÁ

Á

—

ÁÁ

Á

SPIPRI

TMS370Cx6x 8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

serial peripheral interface (SPI) module (continued)

The SPI block diagram is illustrated in Figure 14.

SPIBUF Buffer

Register

SPIDAT

Data Register

SPIBUF.7-0

State Control

SPI CHAR

SPI BIT RATE

CLOCK POLARITY

SPI INT FLAG

SPICTL.6

SPIINT ENA

SPICTL.0

RECEIVER

OVERRUN

8

SPIDAT.7-0

SPICTL.1

TALK

201

3

4

5

SPICCR.2-0

SPICCR.5-3

System

Clock

SPICCR.6

SPICLK

MASTER/SLAVE

†

SPICTL.7

Level 2 INT

SPIPRI.6

1

SPIPC2.7-4

SPISIMO

SPICTL.2

SPIPC1.3-0

SPISOMI

SPIPC2.3-0

Level 1 INT

0

†

The diagram is shown in slave mode.

Figure 14. SPI Block Diagram

serial communications interface 1 (SCI1) module

The TMS370x6x devices include a serial communications interface (SCI1) module. The SCI1 module supports digital communications between the TMS370 devices and other asynchronous peripherals and uses the standard non-return-to-zero (NRZ) format. The SCI1’s receiver and transmitter are double buffered, and each has its own separate enable and interrupt bits. Both can be operated independently or simultaneously in the full-duplex mode. To ensure data integrity, the SCI1 checks received data for break detection, parity, overrun, and framing errors. The speed of bit rate (baud) is programmable to over 65,000 different speeds through a 16-bit baud-select register.

TMS370Cx6x

8-BIT MICROCONTROLLER

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

serial communications interface 1 (SCI1) module (continued)

Features of the SCI1 module include:

D

Three external pins: – SCITXD: SCI transmit output pin or general-purpose bidirectional I/O pin – SCIRXD: SCI receive input pin or general-purpose bidirectional I/O pin – SCICLK: SCI bidirectional serial clock pin, or general-purpose bidirectional I/O pin

D

Two communications modes: asynchronous and isosynchronous

†

D

Baud rate: 64K different programmable rates – Asynchronous mode: 3 bps to 156K bps at 5-MHz SYSCLK

ASYNCHRONOUS BAUD

+

SYSCLK

(BAUD REG)1) 32

– Isosynchronous mode: 39 bps to 2.5M bps at 5-MHz SYSCLK

ISOSYNCHRONOUS BAUD

+

SYSCLK

(BAUD REG)1) 2

D

Data-word format – One start bit – Data-word length programmable from one to eight bits – Optional even/odd/no parity bit – One or two stop bits

D

Four error-detection flags: parity, overrun, framing, and break detection

D

Two wake-up multiprocessor modes: Idle-line and address bit

D

Half or full-duplex operation

D

Double-buffered receive and transmit functions

D

Interrupt driven or polled algorithms with status flags accomplish transmitter and receiver operations. – Transmitter: TXRDY flag (transmitter buffer register is ready to receive another character) and TX

EMPTY flag (transmitter shift register is empty)

– Receiver: RXRDY flag (receive buffer register ready to receive another character), BRKDT flag (break

condition occurred), and RX ERROR monitoring four interrupt conditions – Separate enable bits for transmitter and receiver interrupts – NRZ (non-return-to-zero) format

D

Eleven SCI1 module control registers are located in control register frame beginning at address P050h.

†

Isosynchronous = Isochronous

TMS370Cx6x 8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

40

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

serial communications interface 1 (SCI1) module (continued)

The SCI1 module control registers are illustrated in Table 20.

Table 20. SCI1 Module Control Register Memory Map

PF

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

REG

Á

P050

ÁÁÁ

Á

STOP BITS

ÁÁ

Á

EVEN/ODD

PARITY

ÁÁÁ

Á

PARITY

ENABLE

ÁÁ

Á

ASYNC/

ISOSYNC

ÁÁ

Á

ADDRESS/

IDLE WUP

ÁÁÁ

Á

SCI CHAR2

ÁÁ

Á

SCI CHAR1

ÁÁÁ

Á

SCI CHAR0

ÁÁ

Á

SCICCR

Á

P051

ÁÁÁ

Á

—

ÁÁ

Á

—

ÁÁÁ

Á

SCI SW

RESET

ÁÁ

Á

CLOCK

ÁÁ

Á

TXWAKE

ÁÁÁ

Á

SLEEP

ÁÁ

Á

TXENA

ÁÁÁ

Á

RXENA

ÁÁ

Á

SCICTL

P052

BAUDF

(MSB)

BAUDE

BAUDD

BAUDC

BAUDB

BAUDA

BAUD9

BAUD8

BAUD MSB

Á

P053

ÁÁÁ

Á

BAUD7

ÁÁ

Á

BAUD6

ÁÁÁ

Á

BAUD5

ÁÁ

Á

BAUD4

ÁÁ

Á

BAUD3

ÁÁÁ

Á

BAUD2

ÁÁ

Á

BAUD1

ÁÁÁ

Á

BAUD0

(LSB)

ÁÁ

Á

BAUD LSB

P054

TXRDY

TX EMPTY

—

SCI TX

INT ENA

TXCTL

Á

P055

ÁÁÁ

Á

RX

ERROR

ÁÁ

Á

RXRDY

ÁÁÁ

Á

BRKDT

ÁÁ

Á

FE

ÁÁ

Á

OE

ÁÁÁ

Á

PE

ÁÁ

Á

RXWAKE

ÁÁÁ

Á

SCI RX

INT ENA

ÁÁ

Á

RXCTL

P056

Reserved

P057

RXDT7

RXDT6

RXDT5

RXDT4

RXDT3

RXDT2

RXDT1

RXDT0

RXBUF

P058

Reserved

P059

TXDT7

TXDT6

TXDT5

TXDT4

TXDT3

TXDT2

TXDT1

TXDT0

TXBUF

Á

P05A P05B P05C

БББББББББББББББББББББББББББ

Á

Reserved

ÁÁ

Á

P05D

ÁÁÁ

Á

—

ÁÁ

Á

—

ÁÁÁ

Á

—

ÁÁ

Á

—

ÁÁ

Á

SCICLK

DATA IN

ÁÁÁ

Á

SCICLK

DATA OUT

ÁÁ

Á

SCICLK

FUNCTION

ÁÁÁ

Á

SCICLK

DATA DIR

ÁÁ

Á

SCIPC1

Á

P05E

ÁÁÁ

Á

SCITXD

DATA IN

ÁÁ

Á

SCITXD

DATA OUT

ÁÁÁ

Á

SCITXD

FUNCTION

ÁÁ

Á

SCITXD

DATA DIR

ÁÁ

Á

SCIRXD

DATA IN

ÁÁÁ

Á

SCIRXD

DATA OUT

ÁÁ

Á

SCIRXD

FUNCTION

ÁÁÁ

Á

SCIRXD

DATA DIR

ÁÁ

Á

SCIPC2

P05F SCI STEST

SCITX

PRIORITY

SCIRX

PRIORITY

SCI

ESPEN

—

SCIPRI

The SCI1 module block diagram is illustrated in Figure 15.

TMS370Cx6x

8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

41

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

serial communications interface 1 (SCI1) module (continued)

RXCTL.4–2

FE OE PE

RX ERROR

SCICTL.3

TXWAKE

SCICCR.6 SCICCR.5

EVEN/ODD ENABLE

PARITY

Frame Format and Mode

WUT

TXBUF.7–0

Transmit Data

Buffer Reg.

TXSHF Reg.

TXCTL.7

TXCTL.6

TXRDY

TX EMPTY

SCI TX Interrupt

TXCTL.0

TXENA

8

SCICTL.4

BAUD MSB. 7–0

Baud Rate

MSbyte Reg.

BAUD LSB. 7–0

Baud Rate

LSbyte Reg.

CLOCK

SCICTL.1

SCITXD

SCI TX INT ENA

RXCTL.7

ERR

RXSHF Reg.

RXCTL.1

8

Receive Data

Buffer Reg.

RXBUF.7–0

RXENA

RXCTL.6

RXCTL.5

RXRDY

BRKDT

SCI RX Interrupt

RXCTL.0

SCI RX INT ENA

SCIPRI.6

SCIPRI.5

Level 1 INT Level 2 INT

Level 1 INT

Level 2 INT

SCITX PRIORITY

SCIRX PRIORITY

SCITXD

SCIPC2.7–4

SCICLK

SCIPC1.3–0

SCIRXD

SCIPC2.3–0

SCICTL.0

RXWAKE

1

SYSCLK

0

1

0

1

Figure 15. SCI1 Block Diagram

analog-to-digital converter 1 (ADC1) module

The analog-to-digital (ADC1) converter module is an 8-bit, successive approximation converter with internal sample-and-hold circuitry . The module has eight multiplexed analog input channels that allow the processor to convert the voltage levels from up to eight different sources. The ADC1 module features include the following:

D

Minimum conversion time: 32.8 µs at 5-MHz SYSCLK

D

Ten external pins: – Eight analog input channels (AN0–AN7), any of which can be software configured as digital inputs

(E0–E7) if not needed as analog channels – AN1–AN7 also can be configured as positive-input voltage reference. –V

CC3

: ADC1 module high-voltage reference input

–V

SS3

: ADC1 module low-voltage reference input

TMS370Cx6x 8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

42

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

analog-to-digital converter 1 (ADC1) module (continued)

D

The ADDATA register, which contains the digital result of the last ADC1 conversion

D

ADC1 operations can be accomplished through either interrupt driven or polled algorithms.

D

Six ADC1 module control registers are located in the control register frame beginning at address 1070h.

The ADC1 module control registers are illustrated in Table 21.

Table 21. ADC1 Module Control Register Memory Map

PF

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

REG

ÁÁ

Á

P070

ÁÁ

Á

CONVERT

START

ÁÁ

Á

SAMPLE

START

ÁÁÁ

Á

REF VOLT

SELECT2

ÁÁ

Á

REF VOLT

SELECT1

ÁÁÁ

Á

REF VOLT

SELECT0

ÁÁ

Á

AD INPUT

SELECT2

ÁÁ

Á

AD INPUT SELECT1

ÁÁÁ

Á

AD INPUT

SELECT0

ÁÁ

Á

ADCTL

P071

—

AD READY

AD INT

FLAG

AD INT

ENA

ADSTAT

P072

A-to-D Conversion Data Register

ADDATA

ÁÁ

Á

P073

to

P07C

ББББББББББББББББББББББББББ

Á

Reserved

ÁÁ

Á

P07D

Port E Data Input Register

ADIN

P07E

Port E Input Enable Register

ADENA

ÁÁ

Á

P07F AD STEST

AD

PRIORITY

AD ESPEN

ÁÁ

Á

—

ÁÁÁ

Á

—

ÁÁ

Á

—

ÁÁ

Á

—

ÁÁÁ

Á

—

ÁÁ

Á

ADPRI

TMS370Cx6x

8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

43

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

analog-to-digital converter 1 (ADC1) module (continued)

The ADC1 module block diagram is illustrated in Figure 16.

ADCTL.5–3

5 4 3

ADENA.0

REF VOLTS SELECT

ADCTL.2–0

2 1 0

AD INPUT SELECT

ADIN.0

Port E Input

ENA 0

Port E Data

AN 0

AN0

ADENA.1

ADIN.1

Port E Input

ENA 1

Port E Data

AN 1

AN1

ADENA.2

ADIN.2

Port E Input

ENA 2

Port E Data

AN 2

AN2

ADENA.3

ADIN.3

Port E Input

ENA 3

Port E Data

AN 3

AN3

ADENA.4

ADIN.4

Port E Input

ENA 4

Port E Data

AN 4

AN4

ADENA.5

ADIN.5

Port E Input

ENA 5

Port E Data

AN 5

AN5

ADENA.6

ADIN.6

Port E Input

ENA 6

Port E Data

AN 6

AN6

ADENA.7

ADIN.7

Port E Input

ENA 7

Port E Data

AN 7

AN7

V

CC3

V

SS3

ADCTL.6

SAMPLE

START

ADCTL.7

CONVERT

START

ADDATA.7–0

A-to-D

Conversion

Data Register

ADSTAT.2

AD READY

AD PRIORITY

ADPRI.6

0

1

Level 1 INT

Level 2 INT

AD INT FLAG

ADSTAT.1

AD INT ENA

ADSTAT.0

ADC1

Figure 16. ADC1 Block Diagram

TMS370Cx6x 8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

44

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

instruction set overview

Table 22 provides an opcode-to-instruction cross-reference of all 73 instructions and 274 opcodes of the ‘370Cx6x instruction set. The numbers at the top of this table represent the most significant nibble of the opcode while the numbers at the left side of the table represent the least significant nibble. The instruction of these two opcode nibbles contains the mnemonic, operands, and byte/cycle particular to that opcode.

For example, the opcode B5h points to the CLR A instruction. This instruction contains one byte and executes in eight SYSCLK cycles.

TMS370Cx6x

8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443

• 45

Table 22. TMS370 Family Opcode/Instruction Map

†

MSN

01 2 3 4 5 6 7 8 9 A B C D E F

0

JMP

#ra 2/7

INCW #ra,Rd

3/11

MOV Ps,A

2/8

CLRC /

TST A

1/9

MOV

A,B 1/9

MOV A,Rd

2/7

TRAP

15

1/14

LDST

n

2/6

1JNra

2/5

MOV A,Pd

2/8

MOV B,Pd

2/8

MOV

Rs,Pd

3/10

MOV Ps,B

2/7

MOV B,Rd

2/7

TRAP

14

1/14

MOV

#ra[SP],A

2/7

2JZra

2/5

MOV Rs,A

2/7

MOV #n,A

2/6

MOV Rs,B

2/7

MOV

Rs,Rd

3/9

MOV #n,B

2/6

MOV

B,A 1/8

MOV

#n,Rd

3/8

MOV

Ps,Rd

3/10

DEC

A

1/8

DEC

B

1/8

DEC

Rd

2/6

TRAP

13

1/14

MOV

A,*ra[SP]

2/7

3JCra

2/5

AND Rs,A

2/7

AND #n,A

2/6

AND Rs,B

2/7

AND

Rs,Rd

3/9

AND #n,B

2/6

AND

B,A 1/8

AND

#n,Rd

3/8

AND A,Pd

2/9

AND B,Pd

2/9

AND #n,Pd

3/10

INC

A

1/8

INC

B

1/8

INC

Rd

2/6

TRAP

12

1/14

CMP

*n[SP],A

2/8

4JPra

2/5

OR

Rs,A

2/7

OR

#n,A

2/6

OR

Rs,B

2/7

OR

Rs,Rd

3/9

OR

#n,B

2/6

OR B,A 1/8

OR

#n,Rd

3/8

OR

A,Pd

2/9

OR

B,Pd

2/9

OR

#n,Pd

3/10

INV

A

1/8

INV

B

1/8

INV

Rd

2/6

TRAP

11

1/14

extend

inst,2

opcodes

L S

5

JPZ

ra

2/5

XOR Rs,A

2/7

XOR #n,A

2/6

XOR Rs,B

2/7

XOR

Rs,Rd

3/9

XOR #n,B

2/6

XOR

B,A 1/8

XOR

#n,Rd

3/8

XOR A,Pd

2/9

XOR B,Pd

2/9

XOR #n,Pd

3/10

CLR

A

1/8

CLR

B

1/8

CLR

Rn

2/6

TRAP

10

1/14

N

6

JNZ

ra

2/5

BTJO

Rs,A,ra

3/9

BTJO

#n,A,ra

3/8

BTJO

Rs,B,ra

3/9

BTJO

Rs,Rd,ra

4/11

BTJO

#n,B,ra

3/8

BTJO B,A,ra

2/10

BTJO

#n,Rd,ra

4/10

BTJO

A,Pd,ra

3/11

BTJO

B,Pd,ra

3/10

BTJO

#n,Pd,ra

4/11

XCHB

A

1/10

XCHB A /

TST B

1/10

XCHB

Rn

2/8

TRAP

9

1/14

IDLE

1/6

7

JNC

ra

2/5

BTJZ

Rs.,A,ra

3/9

BTJZ

#n,A,ra

3/8

BTJZ

Rs,B,ra

3/9

BTJZ

Rs,Rd,ra

4/11

BTJZ

#n,B,ra

3/8

BTJZ B,A,ra

2/10

BTJZ

#n,Rd,ra

4/10

BTJZ

A,Pd,ra

3/10

BTJZ

B,Pd,ra

3/10

BTJZ

#n,Pd,ra

4/11

SWAP

A

1/11

SWAP

B

1/11

SWAP

Rn

2/9

TRAP

8

1/14

MOV #n,Pd

3/10

8JVra

2/5

ADD Rs,A

2/7

ADD #n,A

2/6

ADD Rs,B

2/7

ADD

Rs,Rd

3/9

ADD #n,B

2/6

ADD

B,A 1/8

ADD

#n,Rd

3/8

MOVW #16,Rd

4/13

MOVW

Rs,Rd

3/12

MOVW

#16[B],Rpd

4/15

PUSH

A

1/9

PUSH

B

1/9

PUSH

Rd

2/7

TRAP

7

1/14

SETC

1/7

9JLra

2/5

ADC Rs,A

2/7

ADC #n,A

2/6

ADC Rs,B

2/7

ADC

Rs,Rd

3/9

ADC #n,B

2/6

ADC

B,A 1/8

ADC

#n,Rd

3/8

JMPL

lab 3/9

JMPL

*Rp

2/8

JMPL

*lab[B]

3/11

POP

A

1/9

POP

B

1/9

POP

Rd

2/7

TRAP

6

1/14

RTS

1/9

A

JLE

ra

2/5

SUB Rs,A

2/7

SUB #n,A

2/6

SUB Rs,B

2/7

SUB

Rs,Rd

3/9

SUB #n,B

2/6

SUB

B,A 1/8

SUB

#n,Rd

3/8

MOV

& lab,A

3/10

MOV

*Rp,A

2/9

MOV

*lab[B],A

3/12

DJNZ

A,#ra 2/10

DJNZ B,#ra

2/10

DJNZ

Rd,#ra

3/8

TRAP

5

1/14

RTI

1/12

B

JHS

ra

2/5

SBB

Rs,A

2/7

SBB #n,A

2/6

SBB Rs,B

2/7

SBB

Rs,Rd

3/9

SBB #n,B

2/6

SBB

B,A 1/8

SBB

#n,Rd

3/8

MOV

A, & lab

3/10

MOV

A, *Rp

2/9

MOV

A,*lab[B]

3/12

COMPL

A

1/8

COMPL

B

1/8

COMPL

Rd

2/6

TRAP

4

1/14

PUSH

ST 1/8

†

All conditional jumps (opcodes 01– 0F), BTJO, BTJZ, and DJNZ instructions use two additional cycles if the branch is taken. The BTJO, BTJZ, and DJNZ instructions have a relative address as the last operand.

TMS370C6x

8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

Template Release Date: 7–11–94

46

POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443

•

Table 22. TMS370 Family Opcode/Instruction Map† (Continued)

MSN

01 2 3 4 5 6 7 8 9 A B C D E F

C

JNV

ra

2/5

MPY Rs,A

2/46

MPY #n,A 2/45

MPY Rs,B 2/46

MPY

Rs,Rd

3/48

MPY

#n,B 2/45

MPY

B,A

1/47

MPY

#n,Rs

3/47

BR

lab

3/9

BR *Rp 2/8

BR

*lab[B]

3/11

RR

A

1/8

RR

B

1/8

RR

Rd

2/6

TRAP

3

1/14

POP

ST

1/8

L

D

JGE

ra

2/5

CMP Rs,A

2/7

CMP #n,A

2/6

CMP Rs,B

2/7

CMP

Rs,Rd

3/9

CMP

#n,B

2/6

CMP

B,A 1/8

CMP

#n,Rd

3/8

CMP

& lab,A

3/11

CMP

*Rp,A

2/10

CMP

*lab[B],A

3/13

RRC

A

1/8

RRC

B

1/8

RRC

Rd

2/6

TRAP

2

1/14

LDSP

1/7

S

N

EJGra

2/5

DAC Rs,A

2/9

DAC #n,A

2/8

DAC Rs,B

2/9

DAC

Rs,Rd

3/11

DAC #n,B

2/8

DAC

B,A

1/10

DAC

#n,Rd

3/10

CALL

lab

3/13

CALL

*Rp

2/12

CALL

*lab[B]

3/15

RL

A

1/8

RL

B

1/8

RL Rd

2/6

TRAP

1

1/14

STSP

1/8

F

JLO

ra

2/5

DSB Rs,A

2/9

DSB #n,A

2/8

DSB Rs,B

2/9

DSB

Rs,Rd

3/11

DSB #n,B

2/8

DSB

B,A

1/10

DSB

#n,Rd

3/10

CALLR

lab

3/15

CALLR

*Rp

2/14

CALLR

*lab[B]

3/17

RLC

A

1/8

RLC

B

1/8

RLC

Rd

2/6

TRAP

0

1/14

NOP

1/7

Second byte of two-byte instructions (F4xx): F4 8

MOVW

*n[Rn]

4/15

DIV

Rn.A

3/14-63

F4 9

JMPL

*n[Rn]

4/16

Legend: * = Indirect addressing operand prefix & = Direct addressing operand prefix

F4 A

MOV

*n[Rn],A

4/17

# = immediate operand #16 = immediate 16-bit number lab = 16-label

F4 B

MOV

A,*n[Rn]

4/16 n = immediate 8-bit number Pd = Peripheral register containing destination type Pn = Peripheral register

p

F4 C

BR

*n[Rn]

4/16

Ps=Peri heral register containing source byte

ra = Relative address Rd = Register containing destination type Rn = Re

g

ister file

F4 D

CMP

*n[Rn],A

4/18

Rn Register file

Rp = Register pair Rpd= Destination register pair Rps = Source Register pair

F4 E

CALL

*n[Rn]

4/20 Rs = Register containing source byte

F4 F

CALLR

*n[Rn]

4/22

†

All conditional jumps (opcodes 01– 0F), BTJO, BTJZ, and DJNZ instructions use two additional cycles if the branch is taken. The BTJO, BTJZ, and DJNZ instructions have a relative address as the last operand.

TMS370Cx6x

8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

47

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

development system support

The TMS370 family development support tools include an assembler, a C compiler, a linker, compact development tool, and an EEPROM/UVEPROM programmer.

D

Assembler/linker (Part No. TMDS3740850–02 for PC) – Provides extensive macro capability – Allows high-speed operation – Includes format conversion utilities for popular formats

D

ANSI C Compiler (Part No. TMDS3740855–02 for PC, Part No. TMDS3740555–09 for HP700, Sun-3 or Sun-4)

– Generates assembly code for the TMS370 that can be inspected easily – Improves code execution speed and reduces code size with optional optimizer pass – Enables the user to directly reference the TMS370 port registers by using a naming convention – Provides flexibility in specifying the storage for data objects – Interfaces C functions and assembly functions easily – Includes assembler and linker

D

CDT370 (compact development tool) Timer real-time in-circuit emulation – Base (Part No. EDSCDT37T – for PC, requires cable)

– Cable for 68-pin PLCC (Part No. EDSTRG68PLCC) – Provides EEPROM and EPROM programming support – Allows inspection and modification of memory locations – Uploads/downloads program and data memory – Executes programs and software routines – Includes 1024 samples trace buffer – Includes single-step executable instructions – Uses software breakpoints to halt program execution at selected address

D

Microcontroller programmer – Base (Part No. TMDS3760500A – for PC, requires programmer head)

– Single unit head for 68-pin PLCC (Part No. TMDS3780510A) – PC-based, window/function-key-oriented user interface for ease of use and rapid learning environment

D

Starter Kit (Part No. TMDS37000 – for PC) – Includes TMS370 Assembler diskette and documentation – Includes TMS370 Simulator – Includes programming adapter board and programming software – Not included – to be supplied by the user:

HP700 is a trademark of Hewlett-Packard Company. Sun-3 and Sun-4 are trademarks of Sun Microsystems, Inc.

TMS370Cx6x 8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

48

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

development system support (continued)

– + 5 V power supply – ZIF sockets – 9-pin RS232 cable

device numbering conventions

Figure 17 illustrates the numbering and symbol nomenclature for the TMS370Cx6x family.

0370 6 7C

Prefix: TMS = Standard prefix for fully qualified devices

SE = System evaluator (window EPROM) that is used for

prototyping purpose.

Family: 370 = TMS370 8-Bit Microcontroller Family

Technology: C = CMOS

Program Memory Types: 0 = Mask ROM

7 = EPROM

Device Type: 6 = x6x device containing the following modules:

– Timer 1 – Timer 2A – Timer 2B – Serial Peripheral Interface – Serial Communications Interface (SCI1) – Analog-to-Digital Converter (ADC1)

Memory Size: 7 = 24K Bytes

8 = 32K Bytes 9 = 48K Bytes

Temperature Ranges: A = –40°Cto 85°C

L= 0°Cto 70°C T=–40°Cto 105°C

Packages: FN = Plastic Leaded Chip Carrier

FZ = Ceramic Leaded Chip Carrier

ROM and EPROM Option: A = For ROM device, the watchdog timer can be configured

as one of the three different mask options:

– A standard watchdog – A hard watchdog – A simple watchdog

The clock can be either:

– Divide-by-4 clock – Divide-by-1 (PLL) clock

The low-power modes can be either:

– Enabled – Disabled

A = For EPROM device, a standard watchdog, a divide-by-

4 clock, and low-power modes are enabled

TMS

AFNL

Figure 17. TMS370Cx6x Family Nomenclature

TMS370Cx6x

8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

49

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

device part numbers

T able 23 lists all the ‘x6x devices available. The device part number nomenclature is designed to assist ordering. Upon ordering, the customer must specify not only the device part number, but also the clock and watchdog timer options desired. Remember that each device can have only one of the possible three watchdog timer options and one of the two clock options. The options to be specified pertain solely to orders involving ROM devices.

T able 23. Device Part Numbers

DEVICE PART NUMBERS

FOR 68 PINS

БББББББББ

Á

TMS370C067AFNA TMS370C067AFNL TMS370C067AFNT

БББББББББ

Á

БББББББББ

Á

TMS370C068AFNA TMS370C068AFNL TMS370C068AFNT

БББББББББ

Á

TMS370C069AFNA TMS370C069AFNL TMS370C069AFNT

TMS370C768AFNT TMS370C769AFNT

SE370C768AFZT

†

SE370C769AFZT

†

System evaluators are for use only in prototype environment and their reliability has not been characterized.

TMS370Cx6x 8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

50

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

new code release form

Figure 18 shows a sample of the new code release form.

NEW CODE RELEASE FORM

TEXAS INSTRUMENTS

TMS370 MICROCONTROLLER PRODUCTS

DATE:

T o release a new customer algorithm to TI incorporated into a TMS370 family microcontroller, complete this form and submit with the following information:

1. A ROM description in object form on Floppy Disk, Modem XFR, or EPROM (Verification file will be returned via same media)

2. An attached specification if not using TI standard specification as incorporated in TI’s applicable device data book.

Company Name: Street Address: Street Address: City: State Zip

Contact Mr./Ms.: Phone: ( ) Ext.:

Customer Purchase Order Number:

Customer Part Number: Customer Application:

Customer Print Number *Yes: #

No: (Std. spec to be followed) *If Yes: Customer must provide ”print” to TI w/NCRF for approval before ROM code processing starts.

TMS370 Device: TI Customer ROM Number:

(provided by T exas Instruments)

CONTACT OPTIONS FOR THE ’A’ VERSION TMS370 MICROCONTROLLERS

OSCILLAT OR FREQUENCY

MIN TYP MAX [] External Drive (CLKIN) [] Crystal [] Ceramic Resonator

Low Power Modes [] Enabled [] Disabled

Watchdog counter [] Standard [] Hard Enabled [] Simple Counter

Clock Type [] Standard (/4) [] PLL (/1)

[] Supply Voltage MIN: MAX: (std range: 4.5V to 5.5V)

NOTE: Non ’A’ version ROM devices of the TMS370 microcontrollers will have the “Low-power modes Enabled”, “Divide-by-4” Clock, and “Standard” Watchdog options. See the

TMS370 Family User’s Guide

(literature number SPNU127)

or the

TMS370 Family Data Manual

(literature number SPNS014B).

TEMPERATURE RANGE

[] ’L’: 0° to 70°C (standard) [] ’A’: –40° to 85°C [] ’T’: –40° to 105°C

PACKAGE TYPE

[] ’N’ 28-pin PDIP [] “FN” 44-pin PLCC [] “FN” 28-pin PLCC [] “FN” 68-pin PLCC [] “N” 40-pin PDIP [] “NM” 64-pin PSDIP [] “NJ” 40-pin PSDIP (formerly known as N2)

SYMBOLIZA TION BUS EXPANSION

[] TI standard symbolization [] TI standard w/customer part number [] Customer symbolization

(per attached spec, subject to approval)

[] YES [] NO

NON-STANDARD SPECIFICATIONS: ALL NON-STANDARDS SPECIFICA TIONS MUST BE APPROVED BY THE TI ENGINEERING ST AFF: If the customer requires expedited production material

(i.e., product which must be started in process prior to prototype approval and full production release) and non-standard spec issues are not resolved to the satisfaction of both the customer and TI in time for a scheduled shipment, the specification parameters in question will be processed/tested to the standard TI spec. Any such devices which are shipped without conformance to a mutually approved spec, will be identified by a ’P’ in the symbolization preceding the TI part number.

RELEASE AUTHORIZATION: This document, including any referenced attachments, is and will be the controlling document for all orders placed for this TI custom device. Any changes must

be in writing and mutually agreed to by both the customer and TI. The prototype cycletime commences when this document is signed off and the verification code is approved by the customer.

1. Customer: Date: 2. TI: Field Sales: Marketing: Prod. Eng.: Proto. Release:

Figure 18. Sample New Code Release Form

TMS370Cx6x

8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

51

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Table 24 is a collection of all the peripheral file frames using the ’Cx6x, (provided for a quick reference).

Table 24. Peripheral File Frame Compilation

ÁÁÁ

PF

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

REG

System Configuration Registers

ÁÁÁ

Á

P010

ÁÁ

Á

COLD

START

OSC

POWER

PF AUTO

WAIT

ÁÁ

Á

OSC FLT

FLAG

ÁÁÁ

Á

MC PIN

WPO

ÁÁ

Á

MC PIN

DATA

ÁÁÁ

Á

—

ÁÁÁ

Á

µP/µC

MODE

ÁÁÁ

Á

SCCR0

P011

—

AUTOWAIT

DISABLE

—

MEMORY DISABLE

—

ÁÁÁ

SCCR1

Á

P012

HALT/

STANDBY

PWRDWN/

IDLE

ÁÁ

Á

—

BUS

STEST

CPU

STEST

ÁÁ

Á

—

INT1

NMI

PRIVILEGE

DISABLE

ÁÁÁ

Á

SCCR2

P013 Reserved

ÁÁÁ

P014

BUSY

VPPS

—

W0

EXE

ÁÁÁ

EPCTLH

Á

P015

to

P016

Reserved

ÁÁÁ

Á

P017

INT1

FLAG

INT1

PIN DATA

—

INT1

POLARITY

INT1

PRIORITY

INT1

ENABLE

ÁÁÁ

INT1

Á

P018

ÁÁ

Á

INT2

FLAG

ÁÁÁ

Á

INT2

PIN DATA

ÁÁ

Á

—

ÁÁ

Á

INT2

DATA DIR

ÁÁÁ

Á

INT2

DATA OUT

ÁÁ

Á

INT2

POLARITY

ÁÁÁ

Á

INT2

PRIORITY

ÁÁÁ

Á

INT2

ENABLE

ÁÁÁ

Á

INT2

P019

INT3

FLAG

INT3

PIN DATA

—

INT3

DATA DIR

INT3

DATA OUT

INT3

POLARITY

INT3

PRIORITY

INT3

ENABLE

ÁÁÁ

INT3

P01A

BUSY

—

AP

W1W0

EXE

ÁÁÁ

DEECTL

P01B Reserved

ÁÁÁ

P01C

BUSY

VPPS

—

W0

EXE

ÁÁÁ

EPCTLM

P01D Reserved

ÁÁÁ

P01E

BUSY

VPPS

—

W0

EXE

ÁÁÁ

EPCTLL

P01F Reserved

ÁÁÁ

Digital Port Control Registers

P020

Reserved

ÁÁÁ

APORT1

P021

Port A Control Register 2

ÁÁÁ

APORT2

P022

Port A Data

ÁÁÁ

ADATA

P023

Port A Direction

ÁÁÁ

ADIR

P024

Reserved

ÁÁÁ

BPORT1

P025

Port B Control Register 2

ÁÁÁ

BPORT2

P026

Port B Data

ÁÁÁ

BDATA

P027

Port B Direction

ÁÁÁ

BDIR

P028

Reserved

CPORT1

P029

Port C Control Register 2

ÁÁÁ

CPORT2

P02A

Port C Data

ÁÁÁ

CDATA

P02B

Port C Direction

ÁÁÁ

CDIR

P02C

Port D Control Register 1

—

ÁÁÁ

DPORT1

P02D

Port D Control Register 2

†

—

ÁÁÁ

DPORT2

P02E

Port D Data

—

ÁÁÁ

DDATA

P02F

Port D Direction

—

ÁÁÁ

DDIR

†

To configure pin D3 as SYSCLK, set port D control register 2 = 08h.

TMS370Cx6x 8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

52

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Table 24. Peripheral File Frame Compilation (Continued)

PF

BIT 7

BIT 6

ÁÁÁÁ

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

REG

SPI Module Control Memory Map

P030

SPI SW

RESET

CLOCK

POLARITY

ÁÁÁÁ

SPI BIT

RATE2

SPI BIT

RATE1

SPI BIT

RATE0

SPI

CHAR2

SPI

CHAR1

SPI

CHAR0

SPICCR

ÁÁ

Á

P031

ÁÁ

Á

RECEIVER OVERRUN

ÁÁÁ

Á

SPI INT

FLAG

ÁÁÁÁ

Á

ÁÁ

Á

—

ÁÁ

Á

—

ÁÁÁ

Á

—

ÁÁ

Á

MASTER/

SLAVE

ÁÁ

Á

TALK

ÁÁÁ

Á

SPI INT

ENA

ÁÁ

Á

SPICTL

ÁÁ

Á

P032

to

P036

Reserved

ÁÁ

Á

P037

RCVD7

RCVD6

ÁÁÁÁ

RCVD5

RCVD4

RCVD3

RCVD2

RCVD1

RCVD0

SPIBUF P038 Reserved P039

SDAT7

SDAT6

ÁÁÁÁ

SDAT5

SDAT4

SDAT3

SDAT2

SDAT1

SDAT0

SPIDAT

ÁÁ

Á

P03A

to

P03C

Reserved

ÁÁ

Á

P03D

—

ÁÁÁÁ

—

SPICLK DATA IN

SPICLK

DATA OUT

SPICLK

FUNCTION

SPICLK

DATA DIR

SPIPC1

ÁÁ

Á

P03E

ÁÁ

Á

SPISIMO

DATA IN

ÁÁÁ

Á

SPISIMO

DATA OUT

ÁÁÁÁ

Á

ÁÁ

Á

SPISIMO

FUNCTION

ÁÁ

Á

SPISIMO

DATA DIR

ÁÁÁ

Á

SPISOMI

DATA IN

ÁÁ

Á

SPISOMI

DATA OUT

ÁÁ

Á

SPISOMI

FUNCTION

ÁÁÁ

Á

SPISOMI

DATA DIR

ÁÁ

Á

SPIPC2

P03F

SPI

STEST

SPI

PRIORITY

SPI

ESPEN

—

SPIPRI

Timer 1 Module Register Memory Map

Modes: Dual-Compare and Capture/Compare

P040

Bit 15

T1 Counter MSbyte

Bit 8

T1CNTR P041

Bit 7

T1 Counter LSbyte

Bit 0

P042

Bit 15

Compare Register MSbyte

Bit 8

T1C P043

Bit 7

Compare Register LSbyte

Bit 0

P044

Bit 15

Capture/Compare Register MSbyte

Bit 8

T1CC P045

Bit 7

Capture/Compare Register LSbyte

Bit 0

P046

Bit 15

Watchdog Counter MSbyte

Bit 8

WDCNTR P047

Bit 7

Watchdog Counter LSbyte

Bit 0

P048

Bit 15

Watchdog Reset Key

Bit 0

WDRST

ÁÁ

Á

P049

ÁÁ

Á

WD OVRFL

TAP SEL

†

ÁÁÁ

Á

WD

INPUT

SELECT2

†

ÁÁÁÁ

Á

ÁÁ

Á

WD

INPUT

SELECT1

†

ÁÁ

Á

WD

INPUT

SELECT0

†

ÁÁÁ

Á

—

ÁÁ

Á

T1

INPUT

SELECT2

ÁÁ

Á

T1

INPUT

SELECT1

ÁÁÁ

Á

T1 INPUT SELECT0

ÁÁ

Á

T1CTL1

ÁÁ

Á

P04A

ÁÁ

Á

WD OVRFL

RST ENA

†

ÁÁÁ

Á

WD OVRFL

INT ENA

ÁÁÁÁ

Á

ÁÁ

Á

WD OVRFL

INT FLAG

ÁÁ

Á

T1 OVRFL

INT ENA

ÁÁÁ

Á

T1 OVRFL INT FLAG

ÁÁ

Á

—

ÁÁ

Á

—

ÁÁÁ

Á

T1 SW

RESET

ÁÁ

Á

T1CTL2

Mode: Dual-Compare

ÁÁ

Á

P04B

ÁÁ

Á

T1EDGE

INT FLAG

ÁÁÁ

Á

T1C2

INT FLAG

ÁÁÁÁ

Á

ÁÁ

Á

T1C1

INT FLAG

ÁÁ

Á

—

ÁÁÁ

Á

—

ÁÁ

Á

T1EDGE INT ENA

ÁÁ

Á

T1C2

INT ENA

ÁÁÁ

Á

T1C1

INT ENA

ÁÁ

Á

T1CTL3

ÁÁ

P04C

ÁÁ

T1

MODE = 0

ÁÁÁ

T1C1

OUT ENA

ÁÁÁÁ

ÁÁ

T1C2

OUT ENA

ÁÁ

T1C1

RST ENA

ÁÁÁ

T1CR

OUT ENA

ÁÁ

T1EDGE

POLARITY

ÁÁ

T1CR

RST ENA

ÁÁÁ

T1EDGE

DET ENA

ÁÁ

T1CTL4

Mode: Capture/Compare

ÁÁ

Á

P04B

ÁÁ

Á

T1EDGE

INT FLAG

ÁÁÁ

Á

—

ÁÁÁÁ

Á

ÁÁ

Á

T1C1

INT FLAG

ÁÁ

Á

—

ÁÁÁ

Á

—

ÁÁ

Á

T1EDGE INT ENA

ÁÁ

Á

—

ÁÁÁ

Á

T1C1

INT ENA

ÁÁ

Á

T1CTL3

†

Once the WD OVRFL RST ENA bit is set, these bits cannot be changed until a reset; this applies only to the standard watchdog and to simple counter. In the hard watchdog, these bits can be modified at any time; the WD INPUT SELECT2 bits are ignored.

TMS370Cx6x

8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

53

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Table 24. Peripheral File Frame Compilation (Continued)

PF

BIT 7

BIT 6

ÁÁÁÁ

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

REG

Modes: Dual-Compare and Capture/Compare

P04C

T1

MODE = 1

T1C1

OUT ENA

ÁÁÁÁ

—

T1C1

RST ENA

—

T1EDGE

POLARITY

—

T1EDGE DET ENA

T1CTL4

Á

P04D

ÁÁ

Á

—

ÁÁÁ

Á

—

ÁÁÁÁ

Á

ÁÁ

Á

—

ÁÁ

Á

—

ÁÁÁ

Á

T1EVT

DATA IN

ÁÁ

Á

T1EVT

DATA OUT

ÁÁÁ

Á

T1EVT

FUNCTION

ÁÁ

Á

T1EVT DATA

DIR

ÁÁ

Á

T1PC1

P04E

T1PWM

DATA IN

T1PWM

DATA OUT

ÁÁÁÁ

T1PWM

FUNCTION

T1PWM

DATA DIR

T1IC/CR

DATA IN

T1IC/CR

DATA OUT

T1IC/CR

FUNCTION

T1IC/CR

DATA DIR

T1PC2

Á

P04F T1 STEST

T1

PRIORITY

ÁÁÁÁ

Á

ÁÁ

Á

—

ÁÁ

Á

—

ÁÁÁ

Á

—

ÁÁ

Á

—

ÁÁÁ

Á

—

ÁÁ

Á

—

ÁÁ

Á

T1PRI

Serial Communications Interface 1 Memory Map

P050

STOP BITS

EVEN/ODD

PARITY

ÁÁÁÁ

PARITY

ENABLE

ASYNC/

ISOSYNC

ADDRESS/

IDLE WUP

SCI CHAR2

SCI CHAR1

SCI CHAR0

SCICCR

Á

P051

ÁÁ

Á

—

ÁÁÁ

Á

—

ÁÁÁÁ

Á

ÁÁ

Á

SCI SW

RESET

ÁÁ

Á

CLOCK

ÁÁÁ

Á

TXWAKE

ÁÁ

Á

SLEEP

ÁÁÁ

Á

TXENA

ÁÁ

Á

RXENA

ÁÁ

Á

SCICTL

P052

BAUDF

(MSB)

BAUDE

ÁÁÁÁ

BAUDD

BAUDC

BAUDB

BAUDA

BAUD9

BAUD8

BAUD MSB

Á

P053

ÁÁ

Á

BAUD7

ÁÁÁ

Á

BAUD6

ÁÁÁÁ

Á

ÁÁ

Á

BAUD5

ÁÁ

Á

BAUD4

ÁÁÁ

Á

BAUD3

ÁÁ

Á

BAUD2

ÁÁÁ

Á

BAUD1

ÁÁ

Á

BAUD0

(LSB)

ÁÁ

Á

BAUD LSB

P054

TXRDY

TX EMPTY

ÁÁÁÁ

—

SCI TX

INT ENA

TXCTL

Á

P055

ÁÁ

Á

RX

ERROR

ÁÁÁ

Á

RXRDY

ÁÁÁÁ

Á

ÁÁ

Á

BRKDT

ÁÁ

Á

FE

ÁÁÁ

Á

OE

ÁÁ

Á

PE

ÁÁÁ

Á

RXWAKE

ÁÁ

Á

SCI RX

INT ENA

ÁÁ

Á

RXCTL

P056

Reserved

P057

RXDT7

RXDT6

ÁÁÁÁ

RXDT5

RXDT4

RXDT3

RXDT2

RXDT1

RXDT0

RXBUF

P058

Reserved

P059

TXDT7

TXDT6

ÁÁÁÁ

TXDT5

TXDT4

TXDT3

TXDT2

TXDT1

TXDT0

TXBUF

Á

P05A P05B P05C

ББББББББББББББББББББББББББ

Á

Reserved

ÁÁ

Á

P05D

ÁÁ

Á

—

ÁÁÁ

Á

—

ÁÁÁÁ

Á

ÁÁ

Á

—

ÁÁ

Á

—

ÁÁÁ

Á

SCICLK DATA IN

ÁÁ

Á

SCICLK

DATA OUT

ÁÁÁ

Á

SCICLK

FUNCTION

ÁÁ

Á

SCICLK

DATA DIR

ÁÁ

Á

SCIPC1

P05E

SCITXD

DATA IN

SCITXD

DATA OUT

ÁÁÁÁ

SCITXD

FUNCTION

SCITXD

DATA DIR

SCIRXD DATA IN

SCIRXD

DATA OUT

SCIRXD

FUNCTION

SCIRXD

DATA DIR

SCIPC2

Á

P05F SCI STEST

SCITX

PRIORITY

SCIRX

PRIORITY

SCI

ESPEN

ÁÁÁ

Á

—

ÁÁ

Á

—

ÁÁÁ

Á

—

ÁÁ

Á

—

ÁÁ

Á

SCIPRI

Timer 2A Control Registers Memory Map

Modes: Dual-Compare and Dual-Capture

P060

Bit 15

T2A Counter MSbyte

Bit 8

P061

Bit 7

T2A Counter LSbyte

Bit 0

T2ACNTR

P062

Bit 15

Compare Register MSbyte

Bit 8

P063

Bit 7

Compare Register LSbyte

Bit 0

T2AC

P064

Bit 15

Capture/Compare Register MSbyte

Bit 8

P065

Bit 7

Capture/Compare Register LSbyte

Bit 0

T2ACC

P066

Bit 15

Capture Register 2 MSbyte

Bit 8

P067

Bit 7

Capture Register 2 LSbyte

Bit 0

T2AIC

Á

P06A

ÁÁ

Á

—

ÁÁÁ

Á

—

ÁÁÁÁ

Á

ÁÁ

Á

—

ÁÁ

Á

T2A OVRFL

INT ENA

ÁÁÁ

Á

T2A OVRFL

INT FLAG

ÁÁ

Á

T2A

INPUT

SELECT1

ÁÁÁ

Á

T2A INPUT

SELECT0

ÁÁ

Á

T2A SW

RESET

ÁÁ

Á

T2ACTL1

TMS370Cx6x 8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

54

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Table 24. Peripheral File Frame Compilation (Continued)

PF

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

REG

Mode: Dual-Compare

P06B

T2AEDGE1

INT FLAG

T2AC2

INT FLAG

T2AC1

INT FLAG

—

T2AEDGE1

INT ENA

T2AC2

INT ENA

T2AC1

INT ENA

T2ACTL2

ÁÁ

Á

P06C

ÁÁ

Á

T2A

MODE = 0

ÁÁÁ

Á

T2AC1

OUT ENA

ÁÁÁ

Á

T2AC2

OUT ENA

ÁÁ

Á

T2AC1

RST ENA

ÁÁ

Á

T2AEDGE1

OUT ENA

ÁÁÁ

Á

T2AEDGE1

POLARITY

ÁÁ

Á

T2AEDGE1

RST ENA

ÁÁ

Á

T2AEDGE1

DET ENA

ÁÁ

Á

T2ACTL3

Mode: Dual-Capture

P06B

T2AEDGE1

INT FLAG

T2AEDGE2

INT FLAG

T2AC1

INT FLAG

—

T2AEDGE1

INT ENA

T2AEDGE2

INT ENA

T2AC1

INT ENA

T2ACTL2

ÁÁ

Á

P06C

ÁÁ

Á

T2A

MODE = 1

ÁÁÁ

Á

—

ÁÁÁ

Á

—

ÁÁ

Á

T2AC1

RST ENA

ÁÁ

Á

T2AEDGE2

POLARITY

ÁÁÁ

Á

T2AEDGE1

POLARITY

ÁÁ

Á

T2AEDGE2

DET ENA

ÁÁ

Á

T2AEDGE1

DET ENA

ÁÁ

Á

T2ACTL3

Modes: Dual-Compare and Dual-Capture

P06D

—

T2AEVT DATA IN

T2AEVT

DATA OUT

T2AEVT

FUNCTION

T2AEVT

DATA DIR

T2APC1

ÁÁ

Á

P06E

ÁÁ

Á

T2AIC2/PWM

DATA IN

ÁÁÁ

Á

T2AIC2/PWM

DATA OUT

ÁÁÁ

Á

T2AIC2/PWM

FUNCTION

ÁÁ

Á

T2AIC2/PWM

DATA DIR

ÁÁ

Á

T2AIC1/CR

DATA IN

ÁÁÁ

Á

T2AIC1/CR

DATA OUT

ÁÁ

Á

T2AIC1/CR

FUNCTION

ÁÁ

Á

T2AIC1/CR

DATA DIR

ÁÁ

Á

T2APC2

P06F T2A STEST

T2A

PRIORITY

—

T2APRI

Analog-To-Digital Converter 1 Control Registers

ÁÁ

Á

P070

ÁÁ

Á

CONVERT

STAR T

ÁÁÁ

Á

SAMPLE

STAR T

ÁÁÁ

Á

REF VOLT

SELECT2

ÁÁ

Á

REF VOLT

SELECT1

ÁÁ

Á

REF VOLT

SELECT0

ÁÁÁ

Á

AD INPUT

SELECT2

ÁÁ

Á

AD INPUT

SELECT1

ÁÁ

Á

AD INPUT

SELECT0

ÁÁ

Á

ADCTL

P071

—

AD READY

AD INT

FLAG

AD INT

ENA

ADSTAT

P072

A-to-D Conversion Data Register

ADDATA

ÁÁ

Á

P073

to

P07C

ББББББББББББББББББББББББББ

Á

Reserved

ÁÁ

Á

P07D

Port E Data Input Register

ADIN P07E

Port E Input Enable Register

ADENA P07F AD STEST

AD

PRIORITY

AD ESPEN

—

ADPRI

Timer 2B Control Registers Memory Map

Modes: Dual-Compare and Dual-Capture

P080

BIT 15

T2B Counter MSbyte

BIT 8

P081

BIT 7

T2B Counter LSbyte

BIT 0

T2BCNTR

P082

BIT 15

Compare Register MSbyte

BIT 8

P083

BIT 7

Compare Register LSbyte

BIT 0

T2BC

P084

BIT 15

Capture/Compare Register MSbyte

BIT 8

P085

BIT 7

Capture/Compare Register LSbyte

BIT 0

T2BCC

P086

BIT 15

Capture Register 2 MSbyte

BIT 8

P087

BIT 7

Capture Register 2 LSbyte

BIT 0

T2BIC

ÁÁ

Á

P08A

ÁÁ

Á

—

ÁÁÁ

Á

—

ÁÁÁ

Á

—

ÁÁ

Á

T2B OVRFL

INT ENA

ÁÁ

Á

T2B

OVRFL INT

FLAG

ÁÁÁ

Á

T2B INPUT

SELECT1

ÁÁ

Á

T2B INPUT

SELECT0

ÁÁ

Á

T2B SW

RESET

ÁÁ

Á

T2BCTL1

TMS370Cx6x

8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Table 24. Peripheral File Frame Compilation (Continued)

PF

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

REG

Mode: Dual-Compare

P08B

T2BEDGE1

INT FLAG

T2BC2

INT FLAG

T2BC1

INT FLAG

—

T2BEDGE1

INT ENA

T2BC2

INT ENA

T2BC1

INT ENA

T2BCTL2

Á

P08C

ÁÁÁ

Á

T2B

MODE = 0

ÁÁ

Á

T2BC1

OUT ENA

ÁÁÁ

Á

T2BC2

OUT ENA

ÁÁÁ

Á

T2BC1

RST ENA

ÁÁ

Á

T2BEDGE1

OUT ENA

ÁÁ

Á

T2BEDGE1

POLARITY

ÁÁ

Á

T2BEDGE1

RST ENA

ÁÁ

Á

T2BEDGE1

DET ENA

ÁÁ

Á

T2BCTL3

Mode: Dual-Capture

P08B

T2BEDGE1

INT FLAG

T2BEDGE2

INT FLAG

T2BC1

INT FLAG

—

T2BEDGE1

INT ENA

T2BEDGE2

INT ENA

T2BC1

INT ENA

T2BCTL2

Á

P08C

ÁÁÁ

Á

T2B

MODE = 1

ÁÁ

Á

—

ÁÁÁ

Á

—

ÁÁÁ

Á

T2BC1

RST ENA

ÁÁ

Á

T2BEDGE2

POLARITY

ÁÁ

Á

T2BEDGE1

POLARITY

ÁÁ

Á

T2BEDGE2

DET ENA

ÁÁ

Á

T2BEDGE1

DET ENA

ÁÁ

Á

T2BCTL3

Modes: Dual-Compare and Dual-Capture

P08D

—

T2BEVT DATA IN

T2BEVT

DATA OUT

T2BEVT

FUNCTION

T2BEVT

DATA DIR

T2BPC1

Á

P08E

ÁÁÁ

Á

T2BIC2/PWM

DATA IN

ÁÁ

Á

T2BIC2/PWM

DATA OUT

ÁÁÁ

Á

T2BIC2/PWM

FUNCTION

ÁÁÁ

Á

T2BIC2/PWM

DATA DIR

ÁÁ

Á

T2BIC1/CR

DATA IN

ÁÁ

Á

T2BIC1/CR

DATA OUT

ÁÁ

Á

T2BIC1/CR FUNCTION

ÁÁ

Á

T2BIC1/CR

DATA DIR

ÁÁ

Á

T2BPC2

P08F T2B STEST

T2B

PRIORITY

—

T2BPRI

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range

‡

,V

CC1

, V

CC2

, V

CC3

(see Note 1) –0.6 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, All pins except MC –0.6 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC –0.6 V to 14 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, IIK (V

I

< 0 or V

I

> V

CC1)

±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, IOK (VO < 0 or VO > V

CC1

) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current per buffer, I

O

(VO = 0 to V

CC1

)(see Note 1) ±10 mA. . . . . . . . . . . . . . . . . . . . . . . . .

Maximum I

CC

current 170 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum I

SS

current – 170 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous power dissipation 1 W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, TA:L version 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A version – 40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

T version – 40°C to 105°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

‡

V

CC1

= V

CC

NOTE 1: Electrical characteristics are specified with all output buffers loaded with the specified IO current. Exceeding the specified IO current

in any buffer can affect the levels on other buffers.

TMS370Cx6x 8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

recommended operating conditions

MIN NOM MAX UNIT

Supply voltage (see Note 2) 4.5 5 5.5

V

CC1

RAM data-retention supply voltage (see Note 3) 3 5.5

V

CC2

Digital I/O supply voltage (see Note 2) 4.5 5 5.5

V

CC3

Analog supply voltage (see Note 2) 4.5 5 5.5

V

SS2

Digital I/O supply ground – 0.3 0 0.3 V

V

SS3

Analog supply ground – 0.3 0 0.3 V

p

All pins except MC V

SS1

0.8 V

VILLow-level input voltage

MC, normal operation V

SS1

0.3 V

All pins except MC, XTAL2/CLKIN, and RESET

2 V

CC1

V

High-level input voltage

MC (non-WPO mode)

V

CC1

–0.3 V

CC1

+0.3

V

IH

gg

XTAL2/CLKIN 0.8 V

CC1

V

CC1

RESET 0.7 V

CC1

V

CC1

EEPROM write protect override (WPO) 11.7 12 13

MC (mode control) voltage

EPROM programming voltage (VPP)

13 13.2 13.5

V

MC

()g

(see Note 4)

Microprocessor

V

CC1

–0.3 V

CC1

+0.3

V

Microcomputer V

SS1

0.3

L version 0 70

T

A

Operating free-air temperature

A version

– 40 85

°C

T version – 40 105

NOTES: 2. Unless otherwise noted, all voltage values are with respect to V

SS1

.

3. RESET

must be activated externally when V

CC1

or SYSCLK is out of the recommended operating range.

4. The basic microcomputer and microprocessor operating modes are selected by the voltage level applied to the dedicated MC pin two system-clock cycles (tc) before RESET

goes inactive (high). The WPO mode can be selected anytime that a sufficient voltage

is present on MC.

TMS370Cx6x

8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

OL

Low-level output voltage IOL = 1.4 mA 0.4 V

p

IOH = –50 µA 0.9 V

CC1

VOHHigh-level output voltage

IOH = –2 mA 2.4

V

0 V < VI ≤ 0.3 V 10

0.3 V < VI < V

CC1

–0.3 V 50

p

MC

V

CC1

–0.3 V ≤ VI ≤ V

CC1

+0.3 V 10

µ

A

IIInput current

V

CC1

+ 0.3 V < VI ≤ 13 V 650

12 V ≤ VI ≤ 13 V (See Note 6) 50 mA

I/O pins 0 V ≤ VI ≤ V

CC1

± 10 µA

I

OL

Low-level output current VOL = 0.4 V 1.4 mA

p

VOH = 0.9 V

CC1

– 50 µA

IOHHigh-level output current

VOH = 2.4 V – 2 mA

TMS370Cx67A TMS370Cx68A

SYSCLK = 5 MHz See Notes 7 and 8 35 56 mA

Supply current

(

operating mode

)

TMS370Cx67A TMS370Cx68A

SYSCLK = 3 MHz See Notes 7 and 8 25 36 mA

(o erating mode)

OSC POWER bit = 0

TMS370Cx69A SYSCLK = 3 MHz See Notes 5 and 7 46 55 mA

(see Note 9)

TMS370Cx67A TMS370Cx68A

SYSCLK = 0.5 MHz See Notes 7 and 8 13 18

mA

I

CC

TMS370Cx69A SYSCLK = 0.5 MHz See Notes 5 and 7 22 28

pp

SYSCLK = 5 MHz See Notes 7 and 8 12 17

Su ly current (STANDBY mode)

OSC POWER bit = 0

SYSCLK = 3 MHz See Notes 7 and 8 8 11

mA

(see Note 10)

SYSCLK = 0.5 MHz See Notes 7 and 8 2.5 3.5

Supply current (STANDBY mode)

SYSCLK = 3 MHz See Notes 7 and 8 6 8.6

y( )

OSC POWER bit = 1 (see Note 11)

SYSCLK = 0.5 MHz See Notes 7 and 8 2 3

mA

Supply current (HALT mode) XTAL2/CLKIN < 0.2 V See Note 7 2 30 µA

NOTES: 5. ’x69 operates up to 3 MHz SYSCLK. XTAL2/CLKIN is driven with an external square wave signal with 50% duty cycle and rise and

fall times less than 10 ns.

6. Input current IPP is a maximum of 50 mA only when programming EPROM.

7. Single chip mode, ports configured as inputs or outputs with no load. All inputs ≤ 0.2 V or ≥ V

CC1

– 0.2V .

8. XTAL2/CLKIN is driven with an external square wave signal with 50% duty cycle and rise and fall times less than 10 ns. Current can be higher with a crystal oscillator. At 5 MHz SYSCLK, this extra current = 0.01 mA x (total load capacitance + crystal capacitance in pF).

9. Maximum operating current for TMS370Cx6x = 10 (SYSCLK) + 5.8 mA.

10. Maximum standby current for TMS370Cx6x = 3 (SYSCLK) + 2 mA. (OSC POWER bit = 0).

11. Maximum standby current for TMS370Cx6x = 2.24 (SYSCLK) + 1.9 mA. (OSC POWER bit = 1, only valid up to 3 MHz SYSCLK).

TMS370Cx6x 8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

PARAMETER MEASUREMENT INFORMATION

External

Clock Signal

XTAL1XTAL2/CLKIN

C2 (see Note B)

C1

(see Note B)

Crystal/Ceramic

Resonator

(see Note A)

XTAL1XTAL2/CLKIN

C3 (see Note B)

NOTES: A. The crystal/ceramic resonator frequency is four times the reciprocal of the system clock period.

B. The values of C1 and C2 typically are 15 pF and the value of C3 is typically 50pF. See the manufacturer’s recommendations for

ceramic resonators.

Figure 19. Recommended Crystal/Clock Connections (See Note A)

1.2 kΩ

20 pF

V

O

Load Voltage

Case 1: VO = VOH = 2.4 V; Load Voltage = 0 V Case 2: VO = VOL = 0.4 V; Load Voltage = 2.1 V

NOTE A: All measurements are made with the pin loading as shown unless otherwise noted. All measurements are made with XTAL2/CLKIN

driven by an external square wave signal with a 50% duty cycle and rise and fall times less than 10 ns unless otherwise stated.

Figure 20. Typical Output Load Circuit

V

CC

GND

300 Ω

20 Ω

I/O

Pin Data Output

Enable

V

CC

GND

INT 1

6 kΩ

20 Ω

30 Ω

Figure 21. T yplcal Buffer Circuitry

TMS370Cx6x

8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

59

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

PARAMETER MEASUREMENT INFORMATION

timing parameter symbology

Timing parameter symbols have been created in accordance with JEDEC Standard 100. In order to shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows:

A Address RXD SCIRXD AR Array S Slave mode B Byte SC SYSCLK CI XTAL2/CLKIN SCC SCICLK D Data SIMO SPISIMO E EDS SOMI SPISOMI FE Final SPC SPICLK IE Initial TXD SCITXD M Master mode W Write PGM Program WT WAIT R Read

Lowercase subscripts and their meanings are:

c cycle time (period) r rise time d delay time su setup time f fall time v valid time h hold time w pulse duration (width)

The following additional letters are used with these meanings:

H High L Low V Valid Z High impedance

All timings are measured between high and low measurement points as indicated in Figure 22 and Figure 23.

0.8 V (Low)

2 V (High)

0.8 V (Low)

0.8 VCC V (High)

Figure 22. XTAL2/CLKIN Measurement Points Figure 23. General Measurement Points

TMS370Cx6x 8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

external clocking requirements for clock divided by 4† (see Figure 24)

NO. PARAMETER MIN MAX UNIT

1 t

w(Cl)

Pulse duration, XTAL2/CLKIN (see Note 12) 20 ns

2 t

r(Cl)

Rise time, XTAL2/CLKIN 30 ns

3 t

f(CI)

Fall time, XTAL2/CLKIN 30 ns

4 t

d(CIH-SCL)

Delay time, XTAL2/CLKIN rise to SYSCLK fall 100 ns

CLKIN

§

Crystal operating frequency 2 20 MHz

SYSCLK

¶

System clock

‡

0.5 5 MHz

†

For VIL and VIH, refer to recommended operating conditions table.

‡

SYSCLK = CLKIN/4

§

’x69A operates up to 12 MHz CLKIN

¶

’x69A operates up to 3 MHz SYSCLK

NOTE 12: This pulse can be either a high pulse, which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle, or a

low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle.

XTAL2/CLKIN

3

2

1

4

SYSCLK

Figure 24. External Clock Divide-by-4

external clocking requirements for clock divided by 1 (PLL)† (see Figure 25)

NO. PARAMETER MIN MAX UNIT

1 t

w(Cl)

Pulse duration, XTAL2/CLKIN (see Note 12) 20 ns

2 t

r(Cl)

Rise time, XTAL2/CLKIN 30 ns

3 t

f(CI)

Fall time, XTAL2/CLKIN 30 ns

4 t

d(CIH-SCH)

Delay time, XTAL2/CLKIN rise to SYSCLK rise 100 ns

CLKIN

#

Crystal operating frequency 2 5 MHz

SYSCLK

¶

System clock

||

2 5 MHz

†

For VIL and VIH, refer to recommended operating conditions table.

¶

’x69A operates up to 3 MHz SYSCLK

#

’x69A operates up to 3 MHz CLKIN (for divide-by-1 clock option)

||

SYSCLK = CLKIN/1

NOTE 12: This pulse can be either a high pulse, which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle, or a

low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle.

XTAL2/CLKIN

3

2

1

4

SYSCLK

Figure 25. External Clock Divide-by-1

TMS370Cx6x

8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

general purpose output signal switching time requirements (see Figure 26)

MIN NOM MAX UNIT

trRise time 30 ns tfFall time 30 ns

t

f

t

r

Figure 26. Signal Switching Timing

recommended EEPROM timing requirements for programming

MIN MAX UNIT

t

w(PGM)B

Pulse duration, programming signal to ensure valid data is stored (byte mode) 10 ms

t

w(PGM)AR

Pulse duration, programming signal to ensure valid data is stored (array mode) 20 ms

recommended EPROM operating conditions for programming

MIN NOM MAX UNIT

V

CC1

Supply voltage 4.75 5.5 6 V

V

PP

Supply voltage at MC pin 13 13.2 13.5 V

I

PP

Supply current at MC pin during programming (VPP = 13 V) 30 50 mA

Divide-by-4 0.5 5

SYSCLK

System clock

Divide-by-1 2 5

MH

z

recommended EPROM timing requirements for programming

MIN NOM MAX UNIT

t

w(EPGM)

Pulse duration, programming signal (see Note 13) 0.40 0.50 3 ms

NOTE 13: Programming pulse is active when both EXE (EPCTL.0) and V

PPS

(EPCTL.6) are set.

TMS370Cx6x 8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

switching characteristics and timing requirements for external read and write† (see Figure 27 and Figure 28)

NO. PARAMETER MIN MAX UNIT

Divide-by-4 clock 200 2000

5

tcCycle time, SYSCLK (system clock)

Divide-by-1 PLL 200 500

ns

6 t

w(SCL)

Pulse duration, SYSCLK low 0.5tc–25 0.5t

c

ns

7 t

w(SCH)

Pulse duration, SYSCLK high 0.5t

c

0.5tc+20 ns

8 t

d(SCL-A)

Delay time, SYSCLK low to address R/W and OCF valid

0.25tc+75 ns

9 t

v(A)

Valid time, address to EDS, CSE1, CSH1, and CSPF low

0.5tc–90 ns

10 t

su(D)

Setup time, write data time to EDS high 0.75tc–80

‡

ns

11 t

h(EH-A)

Hold time, address, R/W and OCF from EDS, CSE1, CSH1

and CSPF high

0.5tc–60 ns

12 t

h(EH-D)W

Hold time, write data time from EDS high 0.75tc+15 ns

13 t

d(DZ-EL)

Delay time, data bus high impedance to EDS low (read cycle)

0.25tc–35 ns

14 t

d(EH-D)

Delay time, EDS high to data bus enable (read cycle) 1.25tc–40 ns

15 t

d(EL-DV)R

Delay time, EDS low to read data valid tc–95

‡

ns

16 t

h(EH-D)R

Hold time, read time from EDS high 0 ns

17 t

su(WT-SCH)

Setup time, WAIT time to SYSCLK high 0.25tc+70

§

ns

18 t

h(SCH-WT)

Hold time, WAIT time from SYSCLK high 0 ns

19 t

d(EL-WTV)

Delay time, EDS low to WAIT valid 0.5tc–60 ns

20 t

w

Pulse duration, EDS, CSE1, CSH1 and CSPF low tc–80

‡

tc+40

‡

ns

21 t

d(AV-DV)R

Delay time, address valid to read data valid 1.5tc–115

‡

ns

22 t

d(AV-WTV)

Delay time, address valid to WAIT valid tc–115 ns

23 t

d(AV-EH)

Delay time, address valid to EDS high (end of write) 1.5tc–85

‡

ns

†

tc = system-clock cycle time = 1/SYSCLK

‡

If wait states, PFWait, or the autowait feature is used, add tc to this value for each wait state invoked.

§

If the autowait feature is enabled, the WAIT

input can assume a “don’t care” condition until the third cycle of the access. The WAIT signal must

be synchronized with the high pulse of the SYSCLK signal while still conforming to the minimum set-up time.

TMS370Cx6x

8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

18

17

16

13

8

OCF

R/W

WAIT

DATA

EDS

, CSE1, CSH1, CSPF

ADDRESS

SYSCLK

22

19

14

15

21

9

11

20

7

6

5

370 Drives Data Read Data Drive

Read Data

Valid

Read Data

Disable

370 Drives

Data

Figure 27. External-Read Timing

TMS370Cx6x 8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

64

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

18

17

8

R/W

WAIT

DATA

ADDRESS

SYSCLK

12

23

10

22

19

9

11

20

7

6

5

EDS

, CSE1, CSH1, CSPF

Figure 28. External-Write Timing

TMS370Cx6x

8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

65

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

SCI1 isosynchronous-mode timing characteristics and requirements for internal clock (see Note 14 and Figure 29)

NO. MIN MAX UNIT

24 t

c(SCC)

Cycle time, SCICLK 2t

c

131072t

c

ns

25 t

w(SCCL)

Pulse duration, SCICLK low tc– 45 0.5t

c(SCC)

+45 ns

26 t

w(SCCH)

Pulse duration, SCICLK high tc– 45 0.5t

c(SCC)

+45 ns

27 t

d(SCCL-TXDV)

Delay time, SCITXD valid after SCICLK low – 50 60 ns

28 t

v(SCCH-TXD)

Valid time, SCITXD data valid after SCICLK high t

w(SCCH)

– 50 ns

29 t

su(RXD-SCCH)

Setup time, SCIRXD to SCICLK high 0.25 tc + 145 ns

30 t

v(SCCH-RXD)

Valid time, SCIRXD data valid after SCICLK high 0 ns

NOTE 14: tc = system-clock cycle time = 1/SYSCLK

SCIRXD

SCITXD

SCICLK

29

28

24

26

25

Data Valid

27

30

Figure 29. SCI1 Isosynchronous-Mode Timing for Internal Clock

TMS370Cx6x 8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

SCI1 isosynchronous-mode timing characteristics and requirements for external clock (see Note 14 and Figure 30)

NO. MIN MAX UNIT

31 t

c(SCC)

Cycle time, SCICLK 10t

c

ns

32 t

w(SCCL)

Pulse duration, SCICLK low 4.25tc+ 120 ns

33 t

w(SCCH)

Pulse duration, SCICLK high tc + 120 ns

34 t

d(SCCL-TXDV)

Delay time, SCITXD valid after SCICLK low 4.25tc + 145 ns

35 t

v(SCCH-TXD)

Valid time, SCITXD data valid after SCICLK high t

w(SCCH)

ns

36 t

su(SIMO-SCCH)

Setup time, SCIRXD to SCICLK high 40 ns

37 t

v(SCCH-RXD)

Valid time, SCIRXD data after SCICLK high 2t

c

ns

NOTE 14: tc = system-clock cycle time = 1/SYSCLK

SCIRXD

SCITXD

SCICLK

36

35

31

33

32

Data Valid

34

37

Figure 30. SCI1 Isosynchronous-Mode Timing for External Clock

TMS370Cx6x

8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

67

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

SPI-master mode external timing characteristics and requirements (see Note 14 and Figure 31)

NO. MIN MAX UNIT

38 t

c(SPC)M

Cycle time, SPICLK 2t

c

256t

c

ns

39 t

w(SPCL)M

Pulse duration, SPICLK low tc– 45 0.5t

c(SPC)

+45 ns

40 t

w(SPCH)M

Pulse duration, SPICLK high tc– 55 0.5t

c(SPC)

+45 ns

41 t

d(SPCL-SIMOV)M

Delay time, SPISIMO valid after SPICLK low (polarity = 1) – 65 50 ns

42 t

v(SPCH-SIMO)M

Valid time, SPISIMO data valid after SPICLK high (polarity =1)

t

w(SPCH)

– 50 ns

43 t

su(SOMI-SPCH)M

Setup time, SPISOMI to SPICLK high (polarity = 1) 0.25 tc + 150 ns

44 t

v(SPCH-SOMI)M

Valid time, SPISOMI data valid after SPICLK high (polarity = 1)

0 ns

NOTE 14: tc = system-clock cycle time = 1/SYSCLK

Data Valid

SPISOMI

SPISIMO

SPICLK

44

43

4241

38

40

39

NOTE A: The diagram shows polarity = 1. SPICLK is inverted when polarity = 0.

Figure 31. SPI-Master External Timing

TMS370Cx6x 8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

68

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

SPI-slave mode external timing characteristics and requirements (see Note 14 and Figure 32)

NO. MIN MAX UNIT

45 t

c(SPC)S

Cycle time, SPICLK 8t

c

ns

46 t

w(SPCL)S

Pulse duration, SPICLK low 4tc– 45 0.5t

c(SPC)S

+45 ns

47 t

w(SPCH)S

Pulse duration, SPICLK high 4tc– 45 0.5t

c(SPC)S

+45 ns

48 t

d(SPCL-SOMIV)S

Delay time, SPISOMI valid after SPICLK low (polarity = 1) 3.25tc + 130 ns

49 t

v(SPCH-SOMI)S

Valid time, SPISOMI data valid after SPICLK high (polarity =1) t

w(SPCH)S

ns

50 t

su(SIMO-SPCH)S

Setup time, SPISIMO to SPICLK high (polarity = 1) 0 ns

51 t

v(SPCH-SIMO)S

Valid time, SPISIMO data after SPICLK high (polarity = 1) 3tc + 100 ns

NOTE 14: tc = system-clock cycle time = 1/SYSCLK

Data Valid

SPISOMI

SPISIMO

SPICLK

51

50

4948

45

47

46

NOTE A: The diagram shows polarity = 1. SPICLK is inverted when polarity = 0.

Figure 32. SPI-Slave External Timing

TMS370Cx6x

8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

69

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

analog-to-digital converter 1 (ADC1)

The ADC1 converter has a separate power bus for its analog circuitry . These pins are referred to as V

CC3

and

V

SS3

. The purpose is to enhance ADC1 performance by preventing digital switching noise of the logic circuitry

that can be present on V

SS1

and V

CC1

from coupling into the ADC1 analog stage. All ADC1 specifications are

given with respect to V

SS3

unless otherwise noted.

Resolution 8-bits (256 values). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Monotonic Yes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output conversion mode 00h to FFh (00 for VI ≤ V

SS3

≤; FF for VI ≤ V

ref)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Conversion time (excluding sample time) 164 t

c

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

recommended operating conditions

MIN NOM MAX UNIT

pp

4.5 5 5.5

V

CC3

Analog suppl

y v

oltage

V

CC1

–0.3 V

CC1

+0.3

V

SS3

Analog ground V

SS1

–0.3 V

SS1

+0.3 V

V

ref

Non-V

CC3

reference

†

2.5 V

CC3VCC3

+ 0.1 V

Analog input for conversion V

SS3

V

ref

V

†

V

ref

must be stable, within ± 1/2 LSB of the required resolution, during the entire conversion time.

operating characteristics over recommended ranges operating conditions

PARAMETER MIN MAX UNIT

Absolute accuracy

‡

V

CC3

= 5.5 V V

rerf

= 5.1 V ±1.5 LSB

Differential/integral linearity error

‡§

V

CC3

= 5.5 V V

rerf

= 5.1 V ±0.9 LSB

pp

Converting 2 mA

I

CC3

Analog supply current

Nonconverting 5 µA

Input current, AN0–AN7 0 V ≤ VI ≤ 5.5 V 2 µA

I

ref

input charge current 1 mA

p

SYSCLK ≤ 3 MHz 24 kΩ

Z

ref

Source impedance of V

ref

3 MHz < SYSCLK ≤ 5 MHz 10 kΩ

‡

Absolute resolution = 20 mV. At V

ref

= 5 V, this is one LSB. As V

ref

decreases, LSB size decreases. Therefore, the absolute accuracy and

differential/integral linearity errors in terms of LSBs increase.

§

Excluding quantization error of 1/2 LSB

TMS370Cx6x 8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

70

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

analog-to-digital converter 1 (ADC1) (continued)

The ADC1 module allows complete freedom in design of the sources for the analog inputs. The period of the sample time is user-defined so that the high-impedance can be accommodated without penalty to the low-impedance sources. The sample period begins when the SAMPLE ST ART bit of the ADC1 control register (ADCTL.6) is set to 1. The end of the signal sample period occurs when the conversion bit (CONVERT ST ART, ADCTL.7) is set to 1. After a hold time, the converter will reset the SAMPLE ST ART and CONVERT ST ART bits, signaling that a conversion has started and that the analog signal can be removed.

analog timing requirements

MIN MAX UNIT

t

su(S)

Setup time, analog to sample command 0 ns

t

h(AN)

Hold time, analog input from start of conversion 18t

c

ns

t

w(S)

Pulse duration, sample time per kilohm of source impedance

†

1 µs/kΩ

†

The value given is valid for a signal with a source impedance > 1 kΩ. If the source impedance is < 1kΩ, use a minimum sampling time of 1µs.

Analog In

Sample Start

Convert Start

Analog Stable

t

h(AN)

t

w(S)

t

su(S)

Figure 33. Analog Timing

Table 25 is designed to aid the user in referencing a device part number to a mechanical drawing. The table shows a cross-reference of the device part number to the TMS370 generic package name and the associated mechanical drawing by drawing number and name.

Table 25. TMS370Cx6x Family Package Type and Mechanical Cross-Reference

БББББ

Á

PKG TYPE

(mil pin spacing)

ББББББББ

Á

TMS370 GENERIC NAME

ББББББББББ

Á

PKG TYPE NO. AND

MECHANICAL NAME

ББББББ

Á

DEVICE PART NUMBERS

БББББ

Á

БББББ

Á

БББББ

Á

БББББ

Á

БББББ

Á

БББББ

Á

FN – 68 pin (50-mil pin spacing)

ББББББББ

Á

ББББББББ

Á

ББББББББ

Á

ББББББББ

Á

ББББББББ

Á

ББББББББ

Á

PLASTIC LEADED CHIP CARRIER (PLCC)

ББББББББББ

Á

ББББББББББ

Á

ББББББББББ

Á

ББББББББББ

Á

ББББББББББ

Á

ББББББББББ

Á

FN(S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER

ББББББ

Á

ББББББ

Á

ББББББ

Á

ББББББ

Á

ББББББ

Á

ББББББ

Á

TMS370C067AFNA TMS370C067AFNL TMS370C067AFNT TMS370C068AFNA TMS370C068AFNL TMS370C068AFNT TMS370C069AFNA TMS370C069AFNL TMS370C069AFNT TMS370C768AFNT TMS370C769AFNT

БББББ

Á

FZ – 68 pin (50-mil pin spacing)

ББББББББ

Á

CERAMIC LEADED CHIP CARRIER (CLCC)

ББББББББББ

Á

FZ(S-CQCC-J**) J-LEADED CERAMIC CHIP CARRIER

ББББББ

Á

SE370C768AFZT SE370C769AFZT

TMS370Cx6x

8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

71

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

MECHANICAL DATA

FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER

4040005/B 03/95

20 PIN SHOWN

0.026 (0,66)

0.032 (0,81)

D2/E2

0.020 (0,51) MIN

0.180 (4,57) MAX

0.120 (3,05)

0.090 (2,29)

D2/E2

0.013 (0,33)

0.021 (0,53)

Seating Plane

MAX

D2/E2

0.219 (5,56)

0.169 (4,29)

0.319 (8,10)

0.469 (11,91)

0.569 (14,45)

0.369 (9,37)

MAX

0.356 (9,04)

0.456 (11,58)

0.656 (16,66)

0.008 (0,20) NOM

1.158 (29,41)

0.958 (24,33)

0.756 (19,20)

0.191 (4,85)

0.141 (3,58)

MIN

0.441 (11,20)

0.541 (13,74)

0.291 (7,39)

0.341 (8,66)

18

19

14

13

D

D1

13

9

E1E

4

8

MINMAXMIN

PINS

**

20 28 44

0.385 (9,78)

0.485 (12,32)

0.685 (17,40) 52 68 84

1.185 (30,10)

0.985 (25,02)

0.785 (19,94)

D/E

0.395 (10,03)

0.495 (12,57)

1.195 (30,35)

0.995 (25,27)

0.695 (17,65)

0.795 (20,19)

NO. OF

D1/E1

0.350 (8,89)

0.450 (11,43)

1.150 (29,21)

0.950 (24,13)

0.650 (16,51)

0.750 (19,05)

0.004 (0,10)

M

0.007 (0,18)

0.050 (1,27)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice. C. Falls within JEDEC MS-018

TMS370Cx6x 8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

72

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

MECHANICAL DATA

FZ (S-CQCC-J**) J-LEADED CERAMIC CHIP CARRIER

4040219/B 03/95

0.180 (4,57)

0.140 (3,55)

C

0.020 (0,51)

0.032 (0,81)

A B

A

B

0.025 (0,64) R TYP

0.026 (0,66)

0.120 (3,05)

0.155 (3,94)

0.014 (0,36)

0.120 (3,05)

0.040 (1,02) MIN

0.090 (2,29)

0.040 (1,02)  45°

A

MIN MAX

0.485

(12,32) (12,57)

0.495

0.455

(11,56)(10,92)

0.430

MAXMIN

BC

MIN MAX

0.410

(10,41) (10,92)

0.430

0.6300.6100.630 0.6550.6950.685

(16,00)(15,49)(16,00) (16,64)(17,65)(17,40)

0.7400.6800.730 0.7650.7950.785

(18,79)(17,28)(18,54) (19,43)(20,19)(19,94)

PINS**

28

44

52

NO. OFJEDEC

MO-087AC

MO-087AB

MO-087AA

OUTLINE

28 LEAD SHOWN

Seating Plane

(at Seating

Plane)

1426

25

19

18

12

11

5

0.050 (1,27)

0.9300.9100.930 0.9550.9950.985

(23,62)(23,11)(23,62) (24,26)(25,27)(25,02)

68MO-087AD

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit.

IMPORTANT NOTICE

T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.

CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICA TIONS IS UNDERSTOOD T O BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Datasheet SE370C768AFZT, SE370C769AFZT Datasheet (Texas Instruments)

Specifications and Main Features

Frequently Asked Questions

User Manual