Texas Instruments SE370C768AFZT, SE370C769AFZT Datasheet

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TMS370Cx6x

8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

CMOS/EEPROM/EPROM Technologies on a Single Device – Mask-ROM Devices for High-Volume

Production

– One-Time-Programmable (OTP) EPROM

Devices for Low-Volume Production

– Reprogrammable EPROM Devices for

Prototyping Purposes

Internal System Memory Configurations – On-Chip Program Memory Versions

– ROM: 24K, 32K, or 48K Bytes

– EPROM: 32K or 48K Bytes – Data EEPROM: 256 Bytes – Static RAM: 1K or 3.5K Bytes – External Memory/Peripheral Wait States – Precoded External Chip-Select Outputs

in Microcomputer Mode

Flexible Operating Features – Low-Power Modes: STANDBY and HALT – Commercial, Industrial, and Automotive

T emperature Ranges

– Clock Options

– Divide-by-4 (0.5 MHz – 5 MHz SYSCLK)

– Divide-by-1 (2 MHz – 5 MHz SYSCLK)

PLL

– Supply Voltage (V

): 5 V ± 10%

Eight-Channel 8-Bit Analog-to-Digital Converter 1 (ADC1)

Three 16-Bit General Purpose Timers – Software Configurable as

Three 16-Bit Event Counters, or Three 16-Bit Pulse Accumulators, or Five 16-Bit Input Capture Functions, or Six Compare Registers, or Three Self-Contained PWM Functions

– One Timer Has an 8-Bit Prescaler,

Providing a 24-Bit Real-Time Timer

On-Chip 24-Bit Watchdog Timer – EPROM/OTP: Standard Watchdog – Mask-ROM Devices: Hard Watchdog,

Simple Counter, or Standard Watchdog

Serial Communications Interface (SCI1) – Asynchronous and Isosynchronous

†

Modes – Full Duplex, Double-Buffered RX and TX – Two Multiprocessor Communication

Formats

Serial Peripheral Interface (SPI) – Variable-Length High-Speed Shift

– Synchronous Master/Slave Operation

Flexible Interrupt Handling – Two S/W Programmable Interrupt Levels – Global- and Individual-Interrupt Masking – Programmable Rising- or Falling-Edge

Detect

TMS370 Series Compatibility – Register-to-Register Architecture – 256 General-Purpose Registers – 14 Powerful Addressing Modes – Instructions Upwardly Compatible With

All TMS370 Devices

CMOS/Package/TTL-Compatible I/O Pins – 46 Bidirectional Pins, 9 Input Pins – 68-Pin Plastic and Ceramic Leaded Chip

Carrier Packages

– All Peripheral Function Pins Are

Software Configurable for Digital I/O

Workstation/PC-Based Development System – C Compiler and C Source Debugger – Real-Time In-Circuit Emulation – Extensive Breakpoint/Trace Capability – Software Performance Analysis – Multi-Window User Interface – Microcontroller Programmer

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

FN/FZ PACKAGE

(TOP VIEW)

SS1

C2C1MCC0B6

T2AIC1/CR

SCICLK

SCIRXD

SCITXD

XTAL2/CLKIN

XTAL1

C3 C4 C5 C6 C7

SPISOMI

SPICLK

SPISIMO

T1IC/CR T1PWM T1EVT

9876543

10 11 12 13 14 15 16

B5B0B4B3B2B1V

CC2VSS2VCC1

2 1 686766 65 6463 62 61

2728293031323334 353637 38 394041 4243

CC3

SS3

CC1

17 18 19 20 21 22 23 24 25 26

60 59 58 57 56 55 54

53 52 51 50 49 48 47 46 45 44

CC2

SS2

A0 A1 A2 A3 A4 A5 A6 A7

T2AEVT

T2AIC2/PWM

INT1 INT2 INT3

T2BIC2/PWM T2BEVT D3/SYSCLK D4/R/W D5/CSPF D6/CSH1/EDS D7/CSE1/WAIT RESET

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

T2BIC1/CR

†

Isosynchronous = Isochronous

TMS370Cx6x 8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Pin Descriptions

NAME

ALTERNATE

FUNCTION

PLCC

(68)

I/O

†

DESCRIPTION

‡

ÁÁÁ

A0 A1 A2 A3 A4 A5 A6 A7

ÁÁÁÁ

DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7

17 18 19 20 21 22 23 24

I/O

ББББББББББББББББББББ

Single-chip mode: Port A is a general-purpose bidirectional I/O port. Expansion mode: Port A can be individually programmed as the external bidirectional data bus (DATA0–DATA7).

ÁÁÁ

B0 B1 B2 B3 B4 B5 B6 B7

ÁÁÁÁ

ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7

65 66 67 68

1 2 3 4

I/O

ББББББББББББББББББББ

Single-chip mode: Port B is a general-purpose bidirectional I/O port. Expansion mode: Port B can be individually programmed as the low-order address output bus (ADDR0–ADDR7).

ÁÁÁ

C0 C1 C2 C3 C4 C5 C6 C7

ÁÁÁÁ

ADDR8

ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15

5 7

8 10 11 12 13 14

I/O

ББББББББББББББББББББ

Single-chip mode: Port C is a general-purpose bidirectional I/O port. Expansion mode: Port C can be individually programmed as the high-order address output bus (ADDR8–ADDR15).

ÁÁÁ

INT1 INT2 INT3

ÁÁÁÁ

NMI

— —

52 51 50

I I/O I/O

ББББББББББББББББББББ

External (nonmaskable or maskable) interrupt/general-purpose input pin External maskable interrupt input/general-purpose bidirectional pin External maskable interrupt input/general-purpose bidirectional pin

ÁÁÁ

AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7

ÁÁÁÁ

E0 E1 E2 E3 E4 E5 E6 E7

36 37 38 39 40 41 42 43

ББББББББББББББББББББ

ADC1 analog input (AN0–AN7) or positive reference pins (AN1–AN7) Port E can be programmed individually as general-purpose input pins if not used as ADC1 analog input or positive reference input.

ÁÁÁ

CC3

SS3

ÁÁÁÁÁÁ

34 35

ББББББББББББББББББББ

ADC1 positive-supply voltage and optional positive-reference input pin ADC1 ground reference pin

ÁÁÁ

RESET

ÁÁÁÁÁÁ

I/O

ББББББББББББББББББББ

System reset bidirectional pin. RESET, as an input, initializes the microcontroller; as open-drain output, RESET

indicates an internal failure was detected by the watchdog or

oscillator fault circuit.

Mode control (MC) pin. MC enables EEPROM write-protection override (WPO) mode, also EPROM VPP.

ÁÁÁ

XTAL2/CLKIN XTAL1

ÁÁÁÁÁÁ

31 32IO

ББББББББББББББББББББ

Internal oscillator crystal input/external clock source input Internal oscillator output for crystal

CC1

33, 61

Positive supply voltage

CC2

15, 63

Positive supply voltage

†

I = input, O = output

‡

Ports A, B, C, and D can be configured only as general-purpose I/O pins. Also, port D3 can be configured as SYSCLK.

TMS370Cx6x

8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Pin Descriptions (Continued)

ÁÁÁ

NAME

ÁÁÁÁ

ALTERNATE

FUNCTION

PLCC

(68)

I/O

†

БББББББББББББББББББ

DESCRIPTION

‡

SS1

Ground reference for digital logic

SS2

16,62

Ground reference for digital I/O logic

ÁÁÁÁÁÁÁÁ

FUNCTION

БББББББББББББББББББ

Single-chip mode: Port D is a general-purpose bidirectional I /O port. Each of the port D pins can be configured individually as a general-purpose I/O pin, primary memory

control signal (function A), or secondary memory control signal (function B). All chip

selects are independent and can be used for memory-bank switching. See Table 1 for function A memory accesses.

SYSCLK

I/O pin A, B: Internal clock signal is 1/1 (PLL) or 1/4 XTAL2/CLKIN frequency

R/W

I/O pin A, B: Read/write output pin

ÁÁÁ

CSPF

ÁÁ

—

БББББББББББББББББББ

I / O pin A: Chip select peripheral output for peripheral file goes low during memory accesses I/O pin B: Reserved

ÁÁÁ

CSH1

ÁÁ

EDS

I/O

БББББББББББББББББББ

I/O pin A: Chip select half output 1 goes low during memory accesses I/O pin B: External data strobe output goes low during memory accesses from external memory and has the same timings as the five chip selects.

ÁÁÁ

CSE1

ÁÁ

WAIT

БББББББББББББББББББ

I/O pin A: Chip select eighth output goes low during memory accesses. I/O pin B: Wait-input pin extends bus signals.

ÁÁÁ

SCITXD SCIRXD SCICLK

ÁÁÁÁ

SCIIO1 SCIIO2 SCIIO3

30 29 28

I/O

БББББББББББББББББББ

SCI transmit data output pin/general-purpose bidirectional pin

SCI receive data input pin/general-purpose bidirectional pin SCI bidirectional serial clock pin/general-purpose bidirectional pin

ÁÁÁ

T1IC/CR T1PWM T1EVT

ÁÁÁÁ

T1IO1 T1IO2 T1IO3

46 45 44

I/O

БББББББББББББББББББ

Timer1 input capture/counter reset input pin/general-purpose bidirectional pin Timer1 pulse width modulation (PWM) output pin/general-purpose bidirectional pin Timer1 external event input pin/general-purpose bidirectional pin

ÁÁÁ

T2AIC1/CR T2AIC2/PWM T2AEVT

ÁÁÁÁ

T2AIO1 T2AIO2 T2AIO3

27 26 25

I/O

БББББББББББББББББББ

Timer2A input capture 1/counter-reset input pin/general-purpose bidirectional pin Timer2A input capture 2/PWM output pin/general-purpose bidirectional pin Timer2A external event input pin/general-purpose bidirectional pin

ÁÁÁ

T2BIC1/CR T2BIC2/PWM T2BEVT

ÁÁÁÁ

T2BIO1 T2BIO2 T2BIO3

64 60 59

I/O

БББББББББББББББББББ

Timer2B input capture 1/counter-reset input pin/general-purpose bidirectional pin Timer2B input capture 2/PWM output pin/general-purpose bidirectional pin Timer2B external event input pin/general-purpose bidirectional pin

ÁÁÁ

SPISOMI SPISIMO SPICLK

ÁÁÁÁ

SPIIO1 SPIIO2 SPIIO3

49 48 47

I/O

БББББББББББББББББББ

SPI slave output pin, master input pin/general-purpose bidirectional pin SPI slave input pin, master output pin/general-purpose bidirectional pin SPI bidirectional serial clock pin/general-purpose bidirectional pin

†

I = input, O = output

‡

Ports A, B, C, and D can be configured only as general-purpose I/O pins. Port D3 also can be configured as SYSCLK.

The three-pin configuration SCI is referred to as SCI1.

Table 1. Function A Memory-Access Locations for ‘x6x Devices

FUNCTION A

’X67

‘X68

‘X69

CSE1

A000h – BFFFh (8K bytes)

E000h – EFFFh (4K bytes)

CSH1

C000h – FFFFh (16K bytes)

F000h – FFFFh (4K bytes)

CSPF

10C0h – 10FFh (64 bytes)

TMS370Cx6x 8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

functional block diagram

Program Memory

ROM: 24K, 32K, or

48K Bytes

EPROM: 32K or

48K Bytes

SS1

CC1

RESET

MCXTAL2/

CLKIN

XTAL1INT3INT2INT1

E0–E7

AN0–AN7

CC2

SS2

Data EEPROM

256 Bytes

RAM

1K or 3.5K Bytes

CPU

Port D

Port C

Port B

Watchdog

Timer 1

Timer 2B

Serial

Communications

Interface 1

Serial

Peripheral

Interface

System Control

Clock Options:

Divide-by-4 or

Divide-by-1(PLL)

T1PWM

T1EVT

T1IC/CR

T2BIC2/PWM

T2BEVT

T2BIC1/CR

SCICLK

SCITXD

SCIRXD

SPICLK

SPISIMO

SPISOMI

SS3

CC3

Port A

Interrupts

5888

Memory Expansion

Data

Address LSbyte

Address MSbyte

Control

Timer 2A

T2AIC2/PWM

T2AEVT

T2AIC1/CR

Analog to Digital

Converter 1

description

The TMS370C067, TMS370C068, TMS370C069, TMS370C768, TMS370C769, SE370C768, and SE370C769 devices are members of the TMS370 family of single-chip 8-bit microcontrollers. Unless otherwise noted, the term TMS370Cx6x refers to these devices. The TMS370 family provides cost-effective real-time control through integration of advanced peripheral function modules and various on-chip memory configurations.

The TMS370Cx6x family of devices is implemented using high-performance silicon-gate CMOS EPROM and EEPROM technologies. The low-operating power, wide-operating temperature range, and noise immunity of CMOS technology, coupled with the high performance and extensive on-chip peripheral functions, make the TMS370Cx6x devices attractive in system designs for automotive electronics, industrial motor control, computer peripheral control, telecommunications, and consumer application.

All TMS370Cx6x devices contain the following on-chip peripheral modules:

8-channel, 8-bit analog-to-digital converter 1 (ADC1)

Serial communications interface 1 (SCI1)

Serial peripheral interface (SPI)

TMS370Cx6x

8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

description (continued)

One 24-bit general-purpose watchdog timer

Three 16-bit general-purpose timers (one with an 8-bit prescaler)

Table 2 provides a memory configuration overview of the TMS370Cx6x devices.

Table 2. Memory Configurations

DEVICE

PROGRAM

MEMORY

(BYTES)

OFF-CHIP

MEMORY

DATA MEMORY

(BYTES)

OPERATING

MODES

PACKAGES

68-PIN PLCC/CLCC

ROM EPROM

EXP. (BYTES)

RAM EEPROM µC†µP

†

TMS370C067A

24K

—

24K

256

√

FN – PLCC

TMS370C068A

32K

—

24K

256

√

FN – PLCC

TMS370C069A

48K

‡

—

3.5K

256

√

FN – PLCC

TMS370C768A

—

32K

24K

256

√

FN – PLCC

TMS370C769A

—

48K

‡

3.5K

256

√

FN – PLCC

SE370C768A

—

32K

24K

256

√

FZ – CLCC

SE370C769A

—

48K

‡

3.5K

256

√

FZ – CLCC

†

µC – Microcomputer mode µP – Microprocessor mode

‡

’x69 can only operate up to 3 MHz SYSCLK.

System evaluators and development tools are for use only in a prototype environment, and their reliability has not been characterized.

The suffix letter (A) appended to the device names shown in the device column of Table 2 indicates the configuration of the device. ROM or EPROM devices have different configurations as indicated in T able 3. ROM devices with the suffix letter A are configured through a programmable contact during manufacture.

Table 3. Suffix Letter Configuration

DEVICE

WATCHDOG TIMER CLOCK LOW-POWER MODE

EPROM A Standard Divide-by-4 (Standard oscillator) Enabled

Standard

ROM A

Hard

Divide-by-4 or Divide-by-1 (PLL) Enabled or disabled

Simple

Refer to the “device numbering conventions” section for device nomenclature and the “device part numbers” section for ordering.

The mask-programmable ROM in the associated TMS370C06x devices is replaced in the TMS370C76x with 32K or 48K bytes of EPROM while all the other available memory and on-chip peripherals are identical. One-time-programmable (OTP) (TMS370C768 and TMS370C769) and reprogrammable devices (SE370C768 and SE370C769) are available.

TMS370C768 and TMS370C769 are OTP devices that are available in plastic packages. This microcomputer is effective to use for immediate production updates for other members of the TMS370Cx6x family or for low-volume production runs when the mask charge or cycle time for low-cost mask-ROM devices is not practical.

The SE370C768 and SE370C769 have windowed ceramic packages to allow reprogramming of the program EPROM memory during the development / prototyping phase of design. The SE370C768 and SE370C769 devices allow quick updates to breadboards and prototype systems while iterating initial designs.

TMS370Cx6x 8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

description (continued)

The TMS370Cx6x family provides two low-power modes (STANDBY and HALT) for applications where low-power consumption is critical. Both modes stop all central processing unit (CPU) activity (i.e., no instructions are executed). In the ST ANDBY mode, the internal oscillator and the general-purpose timer remain active. In the HAL T mode, all device activity is stopped. The device retains all RAM data and peripheral configuration bits throughout both low-power modes.

The TMS370Cx6x features advanced register-to-register architecture that allows direct arithmetic and logical operations without requiring an accumulator (for example, ADD R24, R47; add the contents of register 24 to the contents of register 47 and store the result in register 47). The TMS370Cx6x family is fully instruction-set compatible, allowing easy transition between members of the TMS370 8-bit microcontroller family.

The SPI and the two operational modes of the SCI1 allow three methods of serial communications. The SCI1 allows standard RS-232-C communications interface between other common data transmission equipment, while the SPI gives high-speed communications between simpler shift-register type devices, such as display drivers, ADC1, phase-locked loop (PLL), I/O expansion, or other microcontrollers in the system.

For large memory applications, the TMS370Cx6x family provides an external bus with non-multiplexed address and data. Precoded memory chip-select outputs can be enabled, which allows minimum-chip-count system implementations. Wait-state support facilitates performance matching among the CPU, external memory, and the peripherals. All pins associated with memory expansion interface are individually software configurable for general purpose digital input/output (I/O) pins when operating in the microcomputer mode.

The TMS370Cx6x family provides the system designer with an economical, efficient solution to real-time control applications. The TMS370 family compact development tool (CDT) solves the challenge of efficiently developing the software and hardware required to design the TMS370Cx6x into an ever-increasing number of complex applications. The application source code can be written in assembly and C language, and the output code can be generated by the linker. The TMS370 family CDT development tool can communicate through a standard RS-232-C interface with an existing personal computer. This allows the use of the personal computer editors and software utilities already familiar to the designer. The TMS370 family CDT emphasizes extensive use of menus and screen windowing so that a system designer with minimal training can begin developing software. Precise real-time in-circuit emulation and extensive symbolic debug and analysis tools ensure efficient software and hardware implementation as well as reduced time-to-market cycle.

The TMS370Cx6x family together with the TMS370 family CDT370, starter kit, software tools, the SE370C76x reprogrammable devices, comprehensive product documentation, and customer support provide a complete solution to the needs of the system designer.

CDT is a trademark of Texas Instruments Incorporated.

TMS370Cx6x

8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

modes

The TMS370Cx6x has four operating modes, two basic modes with each mode having two memory configurations. The basic operating modes are the microcomputer and microprocessor modes, which are selected by the voltage level applied to the dedicated MC pin two cycles before RESET

goes inactive. The two memory configurations then are selected through software programming of the internal system configuration registers. The four operating modes are the microcomputer single chip, microcomputer with external expansion, microprocessor without internal program memory, and microprocessor with internal program memory. These modes are described in the following list.

Microcomputer single chip mode: – Operates as a self-contained microcomputer with all memory and peripherals on-chip – Maximizes the general-purpose I/O capability for real-time control applications

Microcomputer with external expansion mode: – Supports bus expansion to external memory or peripherals, while all on-chip memory (RAM, ROM,

EPROM, and data EEPROM) remains active

– Configures digital I/O ports (ports A, B, C, and D) through software, under control of the associated port

control, to become external memory as follows: – Port A: 8-bit data memory – Port B and Port C: 16-bit address memory – Port D: 5-bit control memory (pin not used as function A or B can be configured as I/O)

– Utilizes the pins available (not used for address, data, or control memory) as general-purpose

input/output by programming them individually

– Lowers the system cost by not requiring an external address/data latch (address memory and data

memory are nonmultiplexed)

– Reduces external interface decode logic by using the precoded chip select outputs that provide direct

memory/peripheral chip select or chip enable functions

– Function A maps up to 24K bytes of external memory into the address space by using CSE1

and CSH1

as memory-bank selects under software control.

– Function B maps up to 24K bytes of external memory into the address space by using EDS under

software control.

Microprocessor without internal program memory mode: – Ports A, B, C, and D (these ports are not programmable) become the address, data, and control buses

for interface to external memory and peripherals. – On-chip RAM and data EEPROM remain active, while the on-chip ROM or EPROM is disabled. – Program area and the reset, interrupt, and trap vectors are located in off-chip memory locations.

Microprocessor with internal program memory mode: – Configured as the microprocessor without internal program memory mode with respect to the external

bus interface – Application program in external memory enables the internal program ROM or EPROM to be active in

the system. (Writing a zero to the MEMORY DISABLED control bit (SCCR1.2) of the SCCR1 control

TMS370Cx6x 8-BIT MICROCONTROLLER

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

memory/peripheral wait operation

The TMS370Cx6x enhances interface flexibility by providing WAIT -state support, decoupling the cycle time of the CPU from the read/write access of the external memory or peripherals. External devices can extend the read/write accesses indefinitely by placing an active low on the WAIT

input pin. The CPU continues to wait as

long as WAIT remains active. Programmable automatic wait-state generation also is provided by the TMS370Cx6x on-chip bus controller.

Following a hardware reset, the TMS370Cx6x is configured to add one wait state to all external bus transactions and memory and peripheral accesses, thus making every external access a minimum of three system clock cycles. The designer can disable the automatic wait-state generation if the AUTOWAIT DISABLE bit in SCCR1 is set to 1. Also, all accesses to the upper four frames of the peripheral file can be extended independently to four system clock cycles if the PF AUTO WAIT bit in SCCR0 is set to one. Programmable wait states

can be

used in conjunction with the external WAIT pin. In applications where the external device read/write access can interface with the TMS370Cx6x CPU using one wait state, the automatic wait-state generation can eliminate external WAIT interface logic, lowering system cost.

TMS370Cx6x

8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

CPU

The CPU used on TMS370Cx6x devices is the high-performance 8-bit TMS370 CPU module. The ’x6x implements an efficient register-to-register architecture that eliminates the conventional accumulator bottleneck. The complete ’x6x instruction set is summarized in Table 22. Figure 1 illustrates the CPU registers and memory blocks.

0000h

0400h

1000h 10C0h 1100h

Interrupts and Reset Vectors;

Trap Vectors

FFFFh

RAM (Includes 256-Byte Registers File)

015

Program Counter (PC)

Legend:

Z=Zero

IE1=Level1 interrupts Enable

C=Carry

V=Overflow

N=Negative

IE2=Level2 interrupts Enable

IE1IE2ZNC

01234567

Status Register (ST)

Stack Pointer (SP)

R0(A) R1(B)

R127

0000h 0001h

0002h

007Fh

R255

0003h

00FFh

Reserved

†

24K-Byte ROM (2000h–7FFFh)

1F00h

0100h

0E00h

32K-Byte ROM/EPROM (2000h–9FFFh)

48K-Byte ROM/EPROM (2000h–DFFFh)

Memory Expansion

2000h

7FBEh

A000h

E000h

1K-Byte RAM (0000h–03FFh)

3.5K-Byte RAM (0000h–0DFFh)

Peripheral File

Peripheral Expansion

Reserved

256-Byte Data EEPROM

00FFh

03FFh

0FFFh 10BFh 10FFh

1EFFh

0DFFh

1FFFh

7FBDh

8000h

7FFFh

9FFFh

DFFFh

†

Reserved means the address space is reserved for future expansion.

Figure 1. Programmer’s Model

TMS370Cx6x 8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

CPU (continued)

The ’x6x CPU architecture provides the following components:

CPU registers: – A stack pointer that points to the last entry in the memory stack – A status register that monitors the operation of the instructions and contains the global-interrupt-enable

bits

– A program counter (PC) that points to the memory location of the next instruction to be executed

A memory map that includes : – 1K- or 3.5K-byte general-purpose RAM that can be used for data-memory storage, program

instructions, general-purpose register, or the stack (can be located only in the first 256 bytes)

– A peripheral file that provides access to all internal peripheral modules, system-wide control functions,

and EEPROM/EPROM programming control

– 256-byte EEPROM module that provides in-circuit programmability and data retention in power-off

conditions

– 24K-, 32K-, or 48K-byte ROM or 32K-, or 48K-byte EPROM program memory

stack pointer (SP)

The SP is an 8-bit CPU register. The stack operates as a last-in, first-out, read/write memory . The stack is used typically to store the return address on subroutine calls as well as the status-register contents during interrupt sequences.

The SP points to the last entry or to the top of the stack. The SP increments automatically before data is pushed onto the stack and decrements after data is popped from the stack. The stack can be located only in the first 256 bytes of the on-chip RAM memory.

status register (ST)

The ST monitors the operation of the instructions and contains the global-interrupt-enable bits. The ST includes four status bits (condition flags) and two interrupt-enable bits:

The four status bits indicate the outcome of the previous instruction; conditional instructions (for example, the conditional-jump instructions) use these status bits to determine program flow.

The two interrupt-enable bits control the two interrupt levels.

The ST register, status bit notation, and status bit definitions are shown in Table 4.

Table 4. Status Registers

IE2

IE1

Reserved

RW-0

R = read, W = write, 0 = value after reset

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CPU (continued)

program counter (PC)

The contents of the PC point to the memory location of the next instruction to be executed. The PC consists of two 8-bit registers in the CPU: the program counter high (PCH) and program counter low (PCL). These registers contain the most-significant byte (MSbyte) and least-significant byte (LSbyte) of a 16-bit address.

The contents of the reset vector (7FFEh, 7FFFh) are loaded into the program counter during reset. The PCH (MSbyte of the PC) is loaded with the contents of memory location 7FFEh, and the PCL (LSbyte of the PC) is loaded with the contents of memory location 7FFFh. Figure 2 shows this operation using an example value of 6000h as the contents of memory locations 7FFEh and 7FFFh (reset vector).

Memory

Program Counter

60 00

PCH PCL

60 00

0000h

7FFEh 7FFFh

Figure 2. Program Counter After Reset

memory map

The TMS370Cx6x architecture is based on the Von Neuman architecture, where the program memory and data memory share a common address space. All peripheral input/output is memory mapped in this same common address space. In the expansion mode, external memory peripherals are also memory-mapped into this common address. As shown in Figure 3, the TMS370Cx6x provides a 16 bit-address range to access internal or external RAM, ROM, data EEPROM, EPROM input/output pins, peripheral functions, and system-interrupt vectors.

The peripheral file contains all input/output port control, on- and off-chip peripheral status and control, EPROM, EEPROM programming, and system-wide control functions. The peripheral file consists of 256 contiguous addresses located from 1000h to 10FFh. The 256 contiguous addresses are logically divided into 16 peripheral file frames of 16 bytes each. Each on-chip peripheral is assigned to a separate frame through which peripheral control and data information is passed. The TMS370Cx6x has its on-chip peripherals and system control assigned to peripheral file frames 1 through 8, addresses 1010h through 108Fh.

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memory map (continued)

Memory Expansion

48K-Byte ROM/EPROM

(2000h–DFFFh)

Interrupts and Reset

Vectors; Trap Vectors

Peripheral File Control Registers

1000h–100Fh

Reserved

†

1F00h

24K-Byte ROM

(2000h–7FFFh)

256-Byte Data EEPROM

(1F00h–1FFFh)

Peripheral Expansion

Peripheral File

3.5K-Byte RAM

(0000h–0DFFh)

1K-Byte RAM

(0000h–03FFh)

0000h

0400h

10C0h

1100h

2000h

7FBEh

8000h

A000h

E000h FFFFh

Microprocessor Mode

Microprocessor With

Internal Program

Memory

Microcomputer

Mode With External

Expansion

ÚÚ

’X67

ÚÚ

Microcomputer

Single Chip Mode

FFFFh

E000h

A000h

8000h

1F00h

10C0h

1000h

0E00h

0400h

0000h

’X68’X69

Not Available

‡

(N/A)

Not Available

‡

Reserved

†

On-Chip For TMS370Cx69 Devices On-Chip For TMS370Cx68 Devices On-Chip For TMS370Cx67 Devices

ÚÚ

2000h

1100h

Reserved

†

’X67

’X68’X69

External

Reserved

†

External

N/A

‡

Reserved

†

’X67

’X68’X69

External

Reserved

†

External

N/A

‡

Reserved

†

’X67

’X68’X69

External

Reserved

†

External

Reserved

0E00h

1000h

Reserved

1010h–101Fh

System Control

1020h–102Fh

Digital Port Control

1030h–103Fh

SPI Peripheral Control

32K-Byte ROM/EPROM

(2000h–9FFFh)

1040h–104Fh

Timer 1 Peripheral Contr.

1050h–105Fh

SCI1 Peripheral Contr.

1060h–106Fh

Timer 2A Peripheral Contr.

1070h–107Fh

ADC1 Peripheral Contr.

1080h–108Fh

Timer 2B Periph. Contr.

1090h–109Fh

Reserved

Vectors

7FBEh–7FBFh

Timer 2B

7FC0h–7FCFh

Trap 15–0

7FE0h–7FEBh

Reserved

7FECh–7FEDh

A/D Converter

7FEEh–7FEFh

Timer 2A

7FF0h–7FF1h

Serial Comm I/F TX

7FF2h–7FF3h

Serial Comm I/F RX

7FF4h–7FF5h

Timer 1

7FF6h–7FF7h

Serial Peripferal I/F

7FF8h–7FF9h

Interrupt 3

7FFAh–7FFBh

Interrupt 2

7FFCh–7FFDh

Interrupt 1

7FFEh–7FFFh

Reset

†

Reserved = the address space is reserved for future expansion.

‡

Not available (N/A) = address space is unavailable in the mode illustrated.

Precoded chip select outputs available on external expansion bus.

Microprocessor mode is designed for ROM-less devices. ROM and EPROM devices also can be used in this mode, but all on-chip memory is ignored.

Figure 3. TMS370Cx6x Memory Map

TMS370Cx6x

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RAM/register file (RF)

Locations within RAM address space can serve as either register file or general-purpose read/write memory, program memory, or stack instructions. The TMS370Cx67 and TMS370Cx68 devices contain 1K bytes of internal RAM, mapped beginning at location 0000h and continuing through location 03FFh, which is shown in Table 5 along with ’x69 devices.

Table 5. RAM Memory Map

‘x67 and ‘x68

‘x69

RAM Size

1K Bytes

3.5K Bytes

Memory Mapped

0000h – 03FFh

0000h – 0DFFh

The first 256 bytes of RAM (0000h – 00FFh) are register files, R0 through R255 (see Figure 1). The first two registers, R0 and R1, are also called register A and B, respectively . Some instructions implicitly use register A or B; for example, the instruction LDSP (load SP) assumes that the value to be loaded into the stack pointer is contained in register B. Registers A and B are the only registers cleared on reset.

peripheral file (PF)

The TMS370Cx6x control registers contain all the registers necessary to operate the system and peripheral modules on the device. The instruction set includes some instructions that access the PF directly. These instructions designate the register by the number of the PF relative to 1000h, preceded by P0 for a hexadecimal designator or by P for a decimal designator. For example, the system control register 0 (SCCR0) is located at address 1010h; its peripheral file hexadecimal designator is P010, and its decimal designator is P16. Table 6 lists the TMS370Cx6x peripheral files.

Table 6. TMS370Cx6x Peripheral File Address Map

БББББ

ADDRESS RANGE

БББББББ

БББББ

PERIPHERAL FILE

DESIGNAT OR

БББББББББББББББББББ

DESCRIPTION

1000h–100Fh

БББББББ

P000–P00F

Reserved for factory test

1010h–101Fh

БББББББ

P010–P01F

System and EEPROM/EPROM control registers

1020h–102Fh

P020–P02F

Digital I/O port control registers

1030h–103Fh

БББББББ

P030–P03F

Serial peripheral interface registers

1040h–104Fh

БББББББ

P040–P04F

Timer 1 registers

1050h–105Fh

БББББББ

P050–P05F

Serial communication interface 1 registers

1060h–106Fh

БББББББ

P060–P06F

Timer 2A registers

1070h–107Fh

БББББББ

P070–P07F

Analog-to-digital converter 1 registers

1080h–108Fh

БББББББ

P080–P08F

Timer 2B registers

1090h–10BFh

БББББББ

P090–P0BF

Reserved

10C0h–10FFh

БББББББ

P0C0–P0FF

External peripheral control

data EEPROM

The TMS370Cx6x devices contain 256 bytes of data EEPROM, and the memory is mapped beginning at location 1F00h and continuing through location 1FFFh.

Writing to the data EEPROM module is controlled by the data-EEPROM control register (DEECTL) and the write-protection register (WPR). Programming algorithm examples are available in the

TMS370 Family User’s

Guide

(literature number SPNU127) or the

TMS370 Data Manual

(SPNS014B). The data EEPROM features

include the following:

Programming: – Bit, byte, and block write/erase modes

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data EEPROM (continued)

– Internal charge pump circuitry. No external EEPROM programming voltage supply is needed. – Control register: Data EEPROM programming is controlled by the data EEPROM control register

(DEECTL) located in the PF frame beginning at location P01A.

– In-circuit programming capability: There is no need to remove the device to program it.

Write-protection: Writes to the data EEPROM are disabled during the following conditions: – Reset: All programming of the data EEPROM module is halted. – Write protection active: there is one write-protect bit per 32-byte EEPROM block. – Low-power mode operation

Write protection can be overridden by applying 12 V to MC.

Table 7 shows the memory map of the control registers.

T able 7. Data EEPROM and Program EPROM Control Registers Memory Map

ADDRESS

SYMBOL

БББББББББББББББББББ

NAME

†

P014

EPCTLH

БББББББББББББББББББ

Program EPROM control register – high array

P015–P016

БББББББББББББББББББ

Reserved

P017

INT1

БББББББББББББББББББ

External interrupt 1 control register

P018

INT2

БББББББББББББББББББ

External interrupt 2 control register

P019

INT3

БББББББББББББББББББ

External interrupt 3 control register

P01A

DEECTL

БББББББББББББББББББ

Data EEPROM control register

P01B

БББББББББББББББББББ

Reserved

P01C

EPCTLM

Program EPROM control register – middle array

P01D

БББББББББББББББББББ

Reserved

P01E

EPCTLL

БББББББББББББББББББ

Program EPROM control register – low array

†

For the 24K- and 32K-byte EPROM device, the program memory is controlled by P01C and P01E; for the 48K-byte EPROM device, the program memory is controlled by P014, P01C, and P01E.

program EPROM

The ‘370C767 program EPROM consists of 24K bytes that are made up of one 16K-byte array and one 8K-byte array of EPROM; the 16K-byte array is located at address locations 2000h through 5FFFh, and the 8K-byte array is located at address locations 6000h through 7FFFh. The ‘370C768 program EPROM consists of 32K bytes that are made up of two 16K-byte arrays of EPROM; the first 16K-byte array is located at address locations 2000h through 5FFFh, and the second 16K-byte array is located at address locations 6000h through 9FFFh. The ’370C769 program EPROM consists of 48K bytes that are made up of three 16K-byte arrays of EPROM; the first 16K-byte array is located at address locations 2000h through 5FFFh, the second 16K-byte array is located at address locations 6000h through 9FFFh, the third 16K-byte array is located at address locations A000h through DFFFh as shown in Table 8.

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program EPROM (continued)

T able 8. EPROM Memory Map

’767

’768

’769

ÁÁ

EPROM size

БББББББ

24K Bytes

БББББББ

32K Bytes

ББББББББББББ

48K Bytes

Memory mapped

16K

2000h–5FFFh8K6000h–7FFFh

First 16K

2000h–5FFFh

Second 16K

6000h–9FFFh

First 16K

2000h–5FFFh

Second 16K

6000h–9FFFh

Third 16K

A000h–DFFFh

ÁÁ

Contol registers

ÁÁÁ

EPCTLL

P01E

ÁÁÁ

EPCTLM

P01C

ÁÁÁ

EPCTLL

P01E

ÁÁÁ

EPCTLM

P01C

ÁÁÁÁ

EPCTLL

P01E

ÁÁÁ

EPCTLM

P01C

ÁÁÁ

EPCTLH

P014

The EPROM memory map in Table 8 expresses the following:

– For the 24K-byte EPROM, the 16K-byte array is controlled by EPCTLL register, located at 101Eh

(P01E); the 8K-byte array is controlled by EPCTLM register, located at 101Ch (P01C). – For the 32K-byte EPROM, the first 16-byte array is controlled by EPCTLL register, located at 101Eh

(P01E); the second 16K-byte array is controlled by EPCTLM register, located at 101Ch (P01C). – For the 48K-bytes EPROM, the first 16K-byte array is controlled by EPCTLL register, located at 101Eh

(P01E); the second 16K-byte array is controlled by EPCTLM register, located at 101Ch (P01C); the third

16K-byte array is controlled by EPCTLH register, located at 1014h (P014).

Reading the program-EPROM modules is identical to reading other internal memory . During programming, the EPROM is controlled by the EPCTL. The program EPROM modules’ features include:

Programming – In-circuit programming capability if V

is applied to MC

– Control register: Program EPROM programming is controlled by the program EPROM control registers

(EPCTLL, EPCTLM, and EPCTLH) located in the PF frame as shown in Table 7. – Programming one EPROM module while executing the other

Write protection: Writes to the program EPROM are disabled under the following conditions: – Reset: All programming to the EPROM module is halted. – Low-power modes – 13 V not applied to MC

program ROM

The program ROM consists of 24K, 32K or 48K bytes of mask-programmable ROM. The program ROM is used for permanent storage of data or instructions. Programming of the mask ROM is performed at the time of device fabrication. Table 9 shows the program ROM memory map.

Table 9. ROM Memory Map

†

‘067

’068

‘069

ROM Size

24K Bytes

32K Bytes

48K Bytes

Memory Mapped

2000h – 7FFFh

2000h – 9FFFh

2000h – DFFFh

†

Memory addresses 7FE0h through 7FEBh are reserved for Texas Instruments Incorporated. Memory addresses 7FBEh through 7FBFh and 7FECh through 7FFFh are reserved for interrupts and reset vectors. Trap vectors, used with TRAP0 through TRAP15 instructions, are located at addresses 7FC0h and 7FCFh.

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system reset

The system-reset operation ensures an orderly start-up sequence for the TMS370Cx6x CPU-based device. There are up to three different actions that can cause a system reset to the device. Two of these actions are internally generated, while one (RESET) is controlled externally. These actions are as follows:

Watchdog (WD) timer. A watchdog-generated reset occurs if an improper value is written to the WD key register, or if the re-initialization does not occur before the watchdog timer timeout . See the

TMS370 Family

User’s Guide

(literature number SPNU127) or the

TMS370 Family Data Manual

(literature number

SPNS014B) for more information.

Oscillator reset. Reset occurs when the oscillator operates outside the recommended operating range. See the

TMS370 Family User’s Guide

(literature number SPNU127) or the

TMS370 Family Data Manual

(literature number SPNS014B) for more information.

External RESET Pin. A low level signal can trigger an external reset. T o ensure a reset, the external signal should be held low for one SYSCLK cycle. Signals of less than one SYSCLK can generate a reset. See the

TMS370 Family User’s Guide

(literature number SPNU127) or the

TMS370 Family Data Manual

(literature

number SPNS014B) for more information.

Once a reset source is activated, the external RESET pin is driven (active) low for a minimum of eight SYSCLK cycles. This allows the ’x6x device to reset external system components. Additionally , if a cold start (V

is off for several hundred milliseconds) condition or oscillator failure occurs or RESET pin is held low , then the reset logic holds the device in a reset state for as long as these actions are active.

After a reset, the program can check the oscillator fault flag (OSC FLT FLAG, SCCR0.4), the cold start flag (COLD ST ART , SCCR0.7) and the watchdog reset (WD OVRFL INT FLAG, T1CTL2.5) to determine the source of the reset. A reset does not clear these flags. Table 10 lists the reset sources.

Table 10. Reset Sources

ADDRESS

BIT NO.

БББББББББ

CONTROL BIT

SOURCE OF RESET

SCCR0

1010h

P010

БББББББББ

COLD START

Cold (power-up)

SCCR0

1010h

P010

OSC FLT FLAG

Oscillator out of range

T1CTL2

104Ah

P04A

БББББББББ

WD OVRFL INT FLAG

Watchdog timer timeout

Once a reset is activated, the following sequence of events occurs:

1. The CPU registers are initialized: ST = 00h, SP = 01h (reset state).

2. Registers A and B are initialized to 00h (no other RAM is changed).

3. The contents of the LSbyte of the reset vector (07FFh) are read and stored in the PCL.

4. The contents of the MSbyte of the reset vector (07FEh) are read and stored in the PCH.

5. Program execution begins with an opcode fetch from the address pointed to by the PC. The reset sequence takes 20 SYSCLK cycles from the time the reset pulse is released until the first opcode

fetch. During a reset, RAM contents (except for registers A and B) remain unchanged, and the module control register bits are initialized to their reset state. During RESET

, the two basic operating modes which are the microcomputer and microprocessor modes can be selected by applying the desired voltage level to the dedicated MC pin two cycles before RESET goes inactive. See the mode section for operating modes description.

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interrupts

The TMS370 family software programmable interrupt structure permits flexible on-chip and external interrupt configurations to meet real-time interrupt-driven application requirements. The hardware interrupt structure incorporates two priority levels as shown in Figure 4. Interrupt level 1 has a higher priority than interrupt level 2. The two priority levels can be independently masked by the global-interrupt mask bits (IE1 and IE2) of the status register.

Each system interrupt is independently configured to either the high- or low-priority chain by the application program during system initialization. Within each interrupt chain, the interrupt priority is fixed by the position of the system interrupt. However, since each system interrupt is selectively configured on either the high-or-low priority interrupt chain, the application program can elevate any system interrupt to the highest priority. Arbitration between the two priority levels is performed within the CPU. Arbitration within each of the priority chains is performed within the peripheral modules to support interrupt expansion for future modules. Pending interrupts are serviced upon completion of current instruction execution, depending on their interrupt mask and priority conditions.

The TMS370Cx6x has ten hardware system interrupts (plus RESET

) as shown in Table 11. Each system interrupt has a dedicated vector located in program memory through which control is passed to the interrupt service routines. A system interrupt can have multiple interrupt sources (e.g., SCI RXINT has two interrupt sources). All of the interrupt sources are individually maskable by local interrupt-enable control bits in the associated PF . Each interrupt source FLAG bit is individually readable for software polling or to determine which interrupt source generated the associated system interrupt. Interrupt control block diagram is illustrated in Figure 4.

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interrupts (continued)

SCI INT

BRKDT RXRDY

TXRDY

TXPRI

RXPRI

TIMER 2A

CPU

NMI

Logic

Enable

IE1

IE2

Level 1 INT Level 2 INT

T2A PRI

Priority

Overflow Compare1

Ext Edge Compare2 Input Capture 1

Input Capture 2

EXT INT 3

INT3 PRI

INT 3

STATUS REG

EXT INT1

INT1 PRI

INT1

SPI INT SPI PRI

SPI

EXT INT 2

INT2 PRI

INT 2

AD INT

AD PRI

A/D

TIMER 1

T1 PRI

Overflow Compare1

Ext Edge Compare2 Input Capture 1

Watchdog

TIMER 2B

T2B PRI

Overflow Compare1

Ext Edge Compare2 Input Capture 1 Input Capture 2

Figure 4. Interrupt Control

Seven of the system interrupts are generated by on-chip peripheral functions, and three external interrupts are supported. Software configuration of the external interrupts is performed through the INT1, INT2, and INT3 control registers in PF frame 1. Each external interrupt is individually software configurable for input polarity (rising or falling edge) for ease of system interface. External interrupt INT1 is software configurable as either a maskable or non-maskable interrupt. When INT1 is configured as nonmaskable, it cannot be masked by the individual- or global-enable-mask bits. Recall that the INT1 NMI bit is protected during non-privileged operation and therefore should be configured during the initialization sequence following reset. T o maximize pin flexibility , external interrupts INT2 and INT3 can be software configured as general-purpose input/output pins if the interrupt function is not required (INT1 can be similarly configured as an input pin). Table 11 shows the interrupt-vector sources, corresponding addresses, and hardware priorities.

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interrupts (continued)

T able 11. Hardware-System Interrupts

ББББББББ

INTERRUPT SOURCE

БББББББ

INTERRUPT FLAG

ÁÁÁÁ

SYSTEM

INTERRUPT

БББББ

VECTOR

ADDRESS

ÁÁÁ

PRIORITY

†

ББББББББ

External RESET Watchdog overflow Oscillator fault detect

БББББББ

COLD START WD OVRFL INT FLAG OSC FLT FLAG

ÁÁÁÁ

RESET

‡

БББББ

7FFEh, 7FFFh

ÁÁÁ

External INT1

INT1 FLAG

INT1

‡

7FFCh, 7FFDh

External INT2

INT2 FLAG

INT2

‡

7FFAh, 7FFBh

External INT3

INT3 FLAG

INT3

‡

7FF8h, 7FF9h

SPI RX/TX complete

SPI INT FLAG

SPIINT

7FF6h, 7FF7h

ББББББББ

Timer 1 overflow Timer 1 compare 1 Timer 1 compare 2 Timer 1 external edge Timer 1 input capture 1 Watchdog overflow

БББББББ

T1 OVRFL INT FLAG T1C1 INT FLAG T1C2 INT FLAG T1EDGE INT FLAG T1IC1 INT FLAG WD OVRFL INT FLAG

ÁÁÁÁ

T1INT

БББББ

7FF4h, 7FF5h

ÁÁÁ

SCI RX data register full SCI RX break detect

RXRDY FLAG BRKDT FLAG

RXINT

‡

7FF2h,7FF3h

SCI TX data register empty

TXRDY FLAG

TXINT

7FF0h, 7FF1h

ББББББББ

Timer 2A overflow Timer 2A compare 1 Timer 2A compare 2 Timer 2A external edge Timer 2A input capture 1 Timer 2A input capture 2

БББББББ

T2A OVRFL INT FLAG T2AC1 INT FLAG T2AC2 INT FLAG T2AEDGE INT FLAG T2AIC1 INT FLAG T2AIC2 INT FLAG

ÁÁÁÁ

T2AINT

БББББ

7FEEh, 7FEFh

ÁÁÁ

ADC1 conversion complete

AD INT FLAG

ADINT

7FECh, 7FEDh

ББББББББ

Timer 2B overflow Timer 2B compare 1 Timer 2B compare 2 Timer 2B external edge Timer 2B input capture 1 Timer 2B input capture 2

БББББББ

T2B OVRFL INT FLAG T2BC1 INT FLAG T2BC2 INT FLAG T2BEDGE INT FLAG T2BIC1 INT FLAG T2BIC2 INT FLAG

ÁÁÁÁ

T2BINT

БББББ

7FBEh, 7FBFh

ÁÁÁ

†

Relative priority within an interrupt level

‡

Release microcontroller from STANDBY and HALT low-power modes

Release microcontroller from STANDBY low-power mode

privileged operation and EEPROM write-protection override

The TMS370Cx6x family has significant flexibility to enable the designer to software-configure the system and peripherals to meet the requirements of a broad variety of applications. The nonprivileged mode of operation ensures the integrity of the system configuration, once it is defined for an application. Following a hardware reset, the TMS370Cx6x operates in the privileged mode, where all peripheral file registers have unrestricted read/write access, and the application program configures the system during the initialization sequence following reset. As the last step of system initialization, the PRIVILEGE DISABLE bit (SCCR2.0) should be set to 1 to enter the nonprivileged mode, disabling write operations to specific configuration control bits within the peripheral file. Table 12 lists the system configuration bits that are write-protected during the nonprivileged mode and must be configured by software prior to exiting the privileged mode.

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privileged operation and EEPROM write-protection override (continued)

Table 12. Privileged Bits

†

NAME

LOCATION

CONTROL BIT

ÁÁÁ

SCCRO

ÁÁÁ

P010.5 P010.6

БББББББББ

PF AUTOWAIT OSC POWER

SCCR1

P011.2 P011.4

MEMORY DISABLE AUTOWAIT DISABLE

ÁÁÁ

SCCR2

ÁÁÁ

P012.0 P012.1 P012.3 P012.4 P012.6 P012.7

БББББББББ

PRIVILEGE DISABLE INT1 NMI CPU STEST BUS STEST PWRDWN/IDLE HALT/STANDBY

ÁÁÁ

SPIPRI

ÁÁÁ

P03F.5 P03F.6 P03F.7

БББББББББ

SPI ESPEN SPI PRIORITY SPI STEST

ÁÁÁ

SCIPRI

ÁÁÁ

P05F.4 P05F.5 P05F.6 P05F.7

БББББББББ

SCI ESPEN SCIRX PRIORITY SCITX PRIORITY SCI STEST

ÁÁÁ

T1PRI

ÁÁÁ

P04F.6 P04F.7

БББББББББ

T1 PRIORITY T1 STEST

ÁÁÁ

T2APRI

ÁÁÁ

P06F.6 P06F.7

БББББББББ

T2A PRIORITY T2A STEST

ÁÁÁ

ADPRI

ÁÁÁ

P07F.5 P07F.6 P07F.7

БББББББББ

AD ESPEN AD PRIORITY AD STEST

T2BPRI

P08F.6 P08F.7

T2B PRIORITY T2B STEST

†

The privileged bits are shown in a bold typeface in Table 14.

The write-protect override (WPO) mode provides an external hardware method of overriding the write-protection registers of data EEPROM on the TMS370Cx6x.The WPO mode is entered by applying a 12-V input to MC after RESET

input goes high (logic 1). The high voltage on MC during the WPO mode is not the programming voltage for the data EEPROM or program EPROM. All EEPROM programming voltages are generated on-chip. The WPO mode provides hardware system-level capability to modify the content of the data EEPROM while the device remains in the application but only while requiring a 12-V external input on the MC pin (normally not available in the end application except in a service or diagnostic environment).

low-power and IDLE modes

The TMS370Cx6x devices have two low-power modes (STANDBY and HALT) and an IDLE mode. For mask-ROM devices, low-power modes can be disabled permanently through a programmable contact at the time when the mask is manufactured.

The ST ANDBY and HALT low-power modes significantly reduce power consumption by reducing or stopping the activity of the various on-chip peripherals when processing is not required. Each of the low-power modes is entered by executing the IDLE instruction when the PWRDWN/IDLE bit in SCCR2 has been set to 1. The HALT/STANDBY bit in SCCR2 controls which low-power mode is entered.

TMS370Cx6x

8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

low-power and IDLE modes (continued)

In the ST ANDBY mode (HAL T/STANDBY = 0), all CPU activity and most peripheral module activity is stopped; however, the oscillator, internal clocks, timer 1, and the receive start-bit detection circuit of the serial communications interface remain active. System processing is suspended until a qualified interrupt (hardware RESET, external interrupt on INT1, INT2, INT3, timer 1 interrupt, or low level on the receive pin of the serial communications interface) is detected.

In the HAL T mode (HALT/STANDBY = 1), the TMS370Cx6x is placed in its lowest power-consumption mode. The oscillator and internal clocks are stopped, causing all internal activity to be halted. System activity is suspended until a qualified interrupt (hardware RESET , external interrupt on the INT1, INT2, INT3, or low level on the receive pin of the serial communications interface) is detected. The low-power mode selection bits are summarized in Table 13.

Table 13. Low-Power/Idle Control Bits

POWER-DOWN CONTROL BITS

PWRDWN/IDLE

(SCCR2.6)

HALT/STANDBY

(SCCR2.7)

MODE SELECTED

STANDBY

HALT

IDLE

X = don’t care

When low-power modes are disabled through a programmable contact in the mask-ROM devices, writing to the SCCR2.6 –7 bits is ignored. In addition, if an idle instruction executes when low-power modes are disabled through a programmable contact, the device always enters the IDLE mode.

T o provide a method of always exiting low-power modes for mask-ROM devices, INT1 is automatically enabled as a nonmaskable interrupt (NMI) during low-power modes when the hard watchdog mode is selected. This means that the NMI always is generated, regardless of the interrupt-enable flags.

The following information is preserved throughout both the STANDBY and HALT modes: RAM (register file), CPU registers (stack pointer, program counter , and status register), I/O pin direction and output data, and status registers of all on-chip peripheral functions. Since all CPU instruction processing is stopped during the STANDBY and HALT modes, the clocking of the watchdog timer is inhibited.

clock modules

The ‘x6x family provides two clock options which are referred to as divide-by-1 (PLL) and divide-by-4 (standard oscillator). Both the divide-by-1 and divide-by-4 options are configurable during the manufacturing process of a TMS370 microcontroller. The ‘x6x ROM-masked devices offer both options to meet system engineering requirements. Only one of the two clock options is allowed on each ROM device. An EPROM has only the divide-by-1.

The divide-by-1 clock module option provides the capability for reduced electromagnetic interference (EMI) with no added cost.

The divide-by-1 provides a 1-to-1 match between the external resonator frequency and the internal system clock (SYSCLK) frequency. The divide-by-4 produces a SYSCLK which is one-fourth the frequency of the external resonator. Inside the divide-by-1 module, the frequency of the external resonator is multiplied by four . The clock module then divides the resulting signal by four to provide the four-phased internal system clock signals. The resulting SYSCLK is equal to the resonator frequency. The frequencies are formulated as follows:

TMS370Cx6x 8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

clock modules (continued)

Divide-by-4 option : SYSCLK

external resonator frequency

CLKIN

Divide-by-1 option : SYSCLK

external resonator frequency 4

CLKIN

The main advantage of choosing a divide-by-1 oscillator is the improved EMI performance. The harmonics of low-speed resonators extend through less of the emissions spectrum than the harmonics of faster resonators. The divide-by-1 provides the capability of reducing the resonator speed by four times, and this results in a steeper decay of emissions produced by the oscillator.

system configuration registers

Table 14 contains system configuration and control functions and registers for controlling EEPROM programming. The privileged bits are shown in bold typeface and shaded.

Table 14. Peripheral File Frame 1: System Configuration Registers

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

REG

P010

COLD

START

OSC

POWER

PF AUTO

WAIT

OSC FLT

FLAG

MC PIN

WPO

MC PIN

DATA

—

µP/µC MODE

SCCR0

P011

ÁÁÁ

—

ÁÁ

—

ÁÁÁ

—

AUTOWAIT

DISABLE

ÁÁ

—

MEMORY

DISABLE

ÁÁ

—

ÁÁÁ

—

ÁÁ

SCCR1

P012

HALT/

STANDBY

PWRDWN/

IDLE

—

BUS

STEST

CPU

STEST

—

INT1

NMI

PRIVILEGE

DISABLE

SCCR2

P013 Reserved P014

BUSY

VPPS

—

EXE

EPCTLH

P015

P016

Reserved

ÁÁ

P017

ÁÁÁ

INT1

FLAG

ÁÁ

INT1

PIN DATA

ÁÁÁ

—

ÁÁ

—

ÁÁ

—

ÁÁÁ

INT1

POLARITY

ÁÁ

INT1

PRIORITY

ÁÁÁ

INT1

ENABLE

ÁÁ

INT1

P018

ÁÁÁ

INT2

FLAG

ÁÁ

INT2

PIN DATA

ÁÁÁ

—

ÁÁ

INT2

DATA DIR

ÁÁ

INT2

DATA OUT

ÁÁÁ

INT2

POLARITY

ÁÁ

INT2

PRIORITY

ÁÁÁ

INT2

ENABLE

ÁÁ

INT2

P019

INT3

FLAG

INT3

PIN DATA

—

INT3

DATA DIR

INT3

DATA OUT

INT3

POLARITY

INT3

PRIORITY

INT3

ENABLE

INT3

P01A

BUSY

—

W1W0

EXE

DEECTL P01B Reserved P01C

BUSY

VPPS

—

EXE

EPCTLM P01D Reserved P01E

BUSY

VPPS

—

EXE

EPCTLL

P01F Reserved

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