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PGA2500
Technical data
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Technical data
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TEXAS INSTRUMENTS PGA2500 Technical data

SBOS289A − NOVEMBER 2003 − REVISED DECEMBER 2003
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
Digitally Controlled
Microphone Preamplifier
PGA2500

FEATURES

D Fully Differential Input-to-Output Architecture D Digitally Controlled Gain Using Serial Port
Interface:
− Unity (0dB) Gain Setting via Serial Port or Dedicated Control Pin
D Dynamic Performance:
− Equivalent Input Noise with ZS = 150Ω and Gain = 30dB: −128dBu
− Total Harmonic Distortion plus Noise (THD+N) with Gain = 30dB: 0.0004%
D Zero Crossing Detection Minimizes Audible
Artifacts when Gain Switching
D Integrated DC Servo Minimizes Output Offset
Voltage
D Common-Mode Servo Improves CMRR D Four-Wire Serial Control Port Interface:
− Simple Interface to Microprocessor or DSP Serial Ports
− Supports Daisy-Chaining of Multiple PGA2500 Devices
D Dedicated Input Pin for Selecting Unity Gain D Overload Output Pin Provides Clipping
Indication
D Four General-Purpose Digital Output Pins D Requires ±5V Power Supplies D Available in an SSOP-28 Package

APPLICATIONS

D Microphone Preamplifiers and Mixers D Digital Mixers and Recorders

DESCRIPTION

The PGA2500 is a digitall y controlled, analog microphone preamplifier designed for use as a front end for high­performance audio analog-to-digital converters (ADCs). The PGA2500 features include low noise, wide dynamic range, and a differential signal path. An on-chip DC servo loop is employed to minimize DC offset, while a common-mode servo function may be used to enhance common-mode rejection.
The PGA2500 features a gain range of 10dB through 65dB (1dB/step), along with a unity gain setting. The wide gain range allows the PGA2500 to be used with a variety of microphones. Gain settings and internal functions are programmed using a 16-bit control word, which is loaded using a simple seri al port interfac e. A serial data output pin provides support for daisy-chained connection of multiple PGA2500 devi ces. Four programmable digital outputs are provided for controlling the external switching of input pads, phantom power, high pass filters, and polarity reversal functions. The PGA2500 requires both +5V and −5V power supplies and is available in a small SSOP-28 package.
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
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Copyright 2003, Texas Instruments Incorporated
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PGA2500IDB
Rails, 48
PGA2500
SSOP-28
DB
−40°C to +85°C
PGA2500I
PGA2500
SSOP-28
DB
−40 C to +85 C
PGA2500I PGA2500IDBR
Tape and Reel, 1000
SBOS289A − NOVEMBER 2003 − REVISED DECEMBER 2003
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ABSOLUTE MAXIMUM RATINGS

Over operating free-air temperature range unless otherwise noted
PGA2500 UNIT
Supply Voltage, VA+ +5.5 V Supply Voltage, VA− −5.5 V Supply Voltage, VD− −5.5 V Voltage Dif ference, VA− to VD− Less than 300 mV Analog input voltage (VA−) −0.3 to (VA+) +0.3 V Digital input voltage −0.3 to (VA+) + 0.3 V Operating Temperature Range −40 to +85 °C Storage Temperature Range −60 to +150 °C
(1)
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only , an d functional operation of the device at these or any other conditions beyond those specified is not implied.

ORDERING INFORMATION

PRODUCT PACKAGE-LEAD
PACKAGE
DESIGNATOR
TEMPERATURE
(1)
(1)
SPECIFIED
RANGE
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe
proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more susceptible t o damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
(1)
For the most current specifications and package information, refer to our web site at www.ti.com.
2
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PARAMETER
TEST CONDITIONS
UNIT
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SBOS289A − NOVEMBER 2003 − REVISED DECEMBER 2003

ELECTRICAL CHARACTERISTICS

All parameters specified with TA = +25°C, VA+ = +5V, VA− = −5V, VD− = −5V, and V
DC Characteristics
Step Size Gain = 10dB through 65dB 1 dB Gain Error All Gain Settings 0.5 dB
AC Characteristics
THD+N with fIN = 1kHz
Gain = 0dB, V
Gain = 30dB, V
OUT
OUT
= 3.5V
= 3.5V
RMS
RMS
, V
, V
COM
COM
IN = 0V
IN = 0V
Analog Input
Maximum Input Voltage Gain = 0dB VA− +1.5 VA+ −2.0 V Input Resistance
Per Input Pin Differential
Analog Output
Output Voltage Range V
IN = 0V , RL = 600Ω VA− +0.9 VA+ −0.9 V
COM
Output Offset Voltage DC Servo On, Any Gain ±0.04 ±1 mV Input Referred Offset DC Servo Off, Gain = 30dB ±1 mV Output Resistive Loading 600 Ω
Load Capacitance Stability 100 pF Short Circuit Current 10-second duration 100 mA
Digital Characteristics
High-Level Input Voltage, V Low-Level Input Voltage, V High-Level Output Voltage, V Low-Level Output Voltage, V Input Leakage Current, I
IH
IL
OH
OL
IN
IO = 200µA (VA+) − 1.0 V
IO = −3.2mA 0.4 V
Switching Characteristics
Serial Clock (SCLK) Frequency f Serial Clock (SCLK) Pulse Width Low t Serial Clock (SCLK) Pulse Width High t
SCLK
PH PL
Input Timing
SDI Setup Time t SDI Hold Time t CS Falling to SCLK Rising t SCLK Falling to CS Rising t
SDS SDH
CSCR CFCS
Output Timing
CS Low to SDO Active t SCLK Falling to SDO Data Valid t
CS High to SDO High Impedance t
CSO
CFDO
CSZ
Power Supply
Operating Voltage VA+ +4.75 +5 +5.25 V VA− −4.75 −5 −5.25 V VD− −4.75 −5 −5.25 V Quiescent Current IA+ VA+ = +5V 30 40 mA IA− VA− = −5V 30 40 mA ID− VD− = −5V 1 2 mA
IN = 0V , unless otherwise noted.
COM
PGA2500
MIN TYP MAX
−114
−108
4600 9200
+2.0 VA+ V
−0.3 0.8 V
2 10 µA
0 6.25 MHz 80 ns 80 ns
20 ns 20 ns 90 ns 35 ns
−108
−102
35 ns 60 ns
100 ns
dB dB
Ω Ω
3
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SBOS289A − NOVEMBER 2003 − REVISED DECEMBER 2003

PIN CONFIGURATION

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PIN DESCRIPTIONS

PIN NUMBER NAME DESCRIPTION
1 GPO1 General-Purpose CMOS Logic Output 2 GPO2 General-Purpose CMOS Logic Output 3 GPO3 General-Purpose CMOS Logic Output 4 GPO4 General-Purpose CMOS Logic Output 5 OVR Over Range Output (Active High) 6 DGND Digital Ground 7 DCEN DC Servo Enable (Active Low) 8 0dB Unity Gain Enable (Active High)
9 ZCEN Zero Crossing Detector Enable (Active High) 10 SDI Serial Data Input 11 CS Chip Select Input (Active Low) 12 SCLK Serial Data Clock Input 13 SDO Serial Data Output 14 VD− −5V Digital Supply 15 VA− −5V Analog Supply 16 V 17 V 18 VA+ +5V Analog Supply 19 VA+ +5V Analog Supply 20 VA− −5V Analog Supply 21 C 22 C 23 C 24 C 25 V 26 VIN− Analog Input, Inverting 27 VIN+ Analog Input, Noninverting 28 AGND Analog Ground
1
GPO1
2
GPO2
3
GPO3
4
GPO4
5
OVR
6
DGND
7
DCEN
0dB
ZCEN
SDI
CS
SCLK
SDO
−
VD
− Analog Output, Inverting
OUT
+ Analog Output, Non-Inverting
OUT
S22
S21
S12
S11
IN Common Mode Voltage Input, 0V to +2.5V
COM
PGA2500
8
9 10 11 12 13 14
DC Servo Capacitor #2, Terminal 2 DC Servo Capacitor #2, Terminal 1 DC Servo Capacitor #1, Terminal 2 DC Servo Capacitor #1, Terminal 1
28
AGND
27
V
+
IN
−
26
V
IN
25
V
IN
COM
24
C
S11
23
C
S12
22
C
S21
21
C
S22
−
20
VA
19
VA+
18
VA+
17
V
+
OUT
−
16
V
OUT
−
15
VA
4
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EQUIVALENT INPUT NOISE (E.I.N.) AS A FUNCTION OF GAIN
THD+N vs GAIN
THD+N vs FREQUENCY
EQUIVALENT INPUT NOISE (E.I.N.) AS A FUNCTION OF GAIN
THD+N AND NOISE vs GAIN
THD+N vs FREQUENCY

TYPICAL CHARACTERISTICS

All specifications at TA = +25°C, VA+ = +5V, VA− = −5V, VD− = −5V, and V
SBOS289A − NOVEMBER 2003 − REVISED DECEMBER 2003
IN = 0V , unless otherwise noted.
COM
"#$%%
−
100
−
102
−
104
−
106
−
108
−
110
−
112
−
114
−
116
−
118
−
120
−
122
E.I.N. (dBu)
−
124
−
126
−
128
−
130
−
132
−
134
−
136
10 15 20 25 30 35 40 45 50 55 60 65
Gain (dB)
(with Z = 0Ω)
0.01
(with 4.0 V
Output and Z = 40Ω)
RMS
0.001
THD+N (%)
0.0001 10 15 20 25 30 35 40 45 50 55 60 65
Gain (dB)
−
100
−
102
−
104
−
106
−
108
−
110
−
112
−
114
−
116
−
118
E.I.N. (dBu)
−
120
−
122
−
124
−
126
−
128
−
130
10 15 20 25 30 35 40 45 50 55 60 65
Gain (dB)
(with Z = 150Ω)
−
(0dB = 4V
80
−
85
−
90
−
95
−
100
−
105
−
110
−
115
THD+N and Noise (dB)
−
120
−
125
−
130
)
RMS
THD+N
with Z = 40
Ω
10 15 20 25 30 35 40 45 50 55 60 65
Gain Set (dB)
Noise
with Z = 0
Ω
(RS=40Ω,RL=600Ω,V
0.1 V
= 4.0Vrms Differential
OUT
for Gains = 10, 20, 30, 40, 50, and 60dB
= 3.5Vrms Differential for Gain = 0dB
V
OUT
IN=0V,BW=22Hzto22kHz)
COM
0.01 60dB
0.001
THD+N Ratio (%)
0.0001
10dB
0dB
20dB
20 100 1k 10k 20k
50dB
40dB
Frequency (Hz)
30dB
(RS=40Ω,RL= 600Ω,V
0.1 V
= 2.0Vrms Differential
OUT
for Gains = 10, 20, 30, 40, 50, and 60dB
= 1.0Vrms Differential for Gain = 0dB
V
OUT
0.01
0.001
THD+N Ratio (%)
0dB
0.0001 20 100 1k 10k 20k
IN = +2.5V, BW = 22Hz to 22kHz)
COM
60dB
50dB
30dB
40dB
20dB
Frequency (Hz)
10dB
5
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THD+N vs FREQUENCY
SBOS289A − NOVEMBER 2003 − REVISED DECEMBER 2003
TYPICAL CHARACTERISTICS (continued)
All specifications at TA = +25°C, VA+ = +5V, VA− = −5V, VD− = −5V, and V
IN = 0V , unless otherwise noted.
COM
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THD+N Ratio (%)
0.0001
(RS=40Ω,RL= 600Ω,V
0.1 V
= 1.0Vrms Differential for All Gain Settings
OUT
0.01
0.001
20 100 1k 10k 20k
50dB
10dB
IN = +2.5V, BW = 22Hz to 22kHz)
COM
60dB
40dB
Frequency (Hz)
30dB
20dB
0.1
0.01
THD+N (%)
0.0003
Gain = 30dB f=1kHz
0.001
V R R
0.3 0.30 3.00 6.00
0dB
COM
S L
THD+N vs OUTPUT AMPLITUDE
IN = 0V
Ω
=40
Ω
= 600
Output Amplitude (Vrms)
7
6
5
4
3
Bandwidth (MHz)
2
1
0
10 15 20 25 30 35 40 45 50 55 60 65
BANDWIDTH vs GAIN
Gain (dB)
6
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