Texas Instruments PCM4201EVM User Manual
User's Guide
SBAU108A–January 2005 – Revised February 2005
PCM4201EVM User's Guide
This document provides the information needed to set up and operate the
PCM4201EVM evaluation module (EVM). For a more detailed description of the
PCM4201, please refer to the product datasheet available from the Texas Instruments
web site at www.ti.com. Additional support documents are listed in the section of this
guide entitled Related Documentation from Texas Instruments and Additional
Documentation. Throughout this document, the acronym EVM and the phrase
evaluation module are synonymous with the PCM4201EVM. This user’s guide
includes setup and configuration instructions, information regarding absolute operating
conditions, an electrical schematic, PCB layout drawings, and a bill of materials (BOM)
for the EVM.
Contents
1 Introduction .......................................................................................... 2
2 Getting Started ...................................................................................... 5
3 Hardware Description and Configuration ........................................................ 6
4 Schematic, PCB Layout, and Bill of Materials................................................. 10
List of Figures
1 PCM4201 Functional Block Diagram ............................................................ 2
2 PCM4201EVM Functional Block Diagram....................................................... 3
3 Transmitter Reset Circuitry ........................................................................ 9
4 PCM4201EVM Schematic ....................................................................... 11
5 Top Side Silkscreen .............................................................................. 12
6 Bottom Side Silkscreen........................................................................... 13
7 Top Layer (Component Side).................................................................... 14
8 Ground Layer ...................................................................................... 15
9 Power Plane Layer................................................................................ 16
10 Bottom Layer (Solder Side) ...................................................................... 17
List of Tables
1 Absolute Operating Conditions ................................................................... 5
2 System Clock Source Selection .................................................................. 7
3 Sampling Mode Selection ......................................................................... 7
4 Digital High-Pass Filter Configuration ........................................................... 7
5 Slave/Master Mode Configuration ............................................................... 8
6 System Clock Rates for Master Mode Operation .............................................. 8
7 System Clock Rates for Slave Mode Operation ............................................... 8
8 Digital Interface Transmitter Configuration ..................................................... 9
9 Transmitter Master Clock Configuration ........................................................ 9
10 PCM4201EVM Bill of Materials.................................................................. 18
PCM4201EVM User's GuideSBAU108A–January 2005–Revised February 2005 1
www.ti.com
HPF
Delta−Sigma
Modulator
Decimation
Filter
Voltage
Reference
V
REF
+
V
REF
−
VINR+
VINR
−
Power
V
DD
AGND
Reset
Logic
Clock
Control
Audio
Serial
Port
DGND
V
CC
FSYNC
BCK
DATA
S/M
RATE
SCKI
RST
HPFD
Introduction
1 Introduction
The PCM4201 is a low power, high-performance, single channel audio analog-to-digital (A/D) converter
designed for use in battery-operated or portable professional audio applications, including digital wireless
microphones and digital audio recorders/processors. The PCM4201 features a 24-bit linear PCM data
output, with a data format compatible with digital signal processors and digital audio interface transmitters
(including the DIT4096 and DIT4192 from Texas Instruments).
The PCM4201 includes three sampling modes, supporting sampling rates up to 108kHz. The Normal
Speed Low Power mode supports sampling rates up to 54kHz, and employs 64x oversampling to reduce
overall converter power. The Normal Speed High Performance mode supports sampling rates up to 54kHz
with 128x oversampling, resulting in higher dynamic range than the Low Power mode, at the expense of
increased power dissipation. The Double Speed mode supports sampling frequencies up to 108kHz, and
is provided for those cases where higher sampling rates may be required.
A digital high-pass filter is included for DC removal. Dedicated control pins are included for sampling mode
selection, Slave/Master mode port operation, digital high-pass filter enable/disable, and reset/power-down
functions.
A +5V power supply is required for the analog section of the device, while a +3.3V power supply is
typically utilized for the digital circuitry. The digital supply may operate at voltages as low as +1.8V, with a
corresponding 10mW to 20mW reduction in power dissipation, depending upon the sampling mode
selection. Figure 1 illustrates the functional block diagram for the PCM4201.
1.1 PCM4201EVM Features
The PCM4201EVM provides a convenient platform for evaluating the performance and functions of the
PCM4201 device. The primary EVM features include:
• Simple configuration using an onboard DIP switch
• Differential voltage input supporting 3-pin XLR or balanced TRS connections
• Differential input buffer and filter circuit utilizing the Texas Instruments OPA2134 dual op amp
• Flexible input buffer power supply connection (dual or single supply options) and resistor/capacitor
PCM4201EVM User's Guide2 SBAU108A – January 2005 – Revised February 2005
configuration allow for circuit experimentation and op amp substitution
Figure 1. PCM4201 Functional Block Diagram
www.ti.com
J1
Analog
Input
Analog
Input Buffer
U1
PCM4201
Switch
SW1
To
DIT Circuitry
and
Clock Enables
X1
22.5792M
J4
EXT CLOCK INPUT
System
Clock
X2
24.576M
S/M
U2
OPA2134
GND
J2
+5VA+15V
−
15V
−
15V
GND
+15V
GND
+5VA
U10
REG1117
+3.3V
J6
+5VD
+5VD
GND
EXT VDD
VDD
JMP4
BUF
S/M
PCM Data
HDR
J3
Audio
Serial Port
BUF
DIT
U7
DIT4096
J5
AES3 Output
• Buffered audio serial port output supports connection to external DSP hardware or audio test
equipment
• An onboard Texas Instruments DIT4096 provides an AES3-encoded digital output suitable for use with
audio test systems or commercial audio equipment, supporting output sampling rates up to 108kHz
• Onboard crystal oscillators, operating at 22.5792MHz and 24.576MHz, support 44.1kHz, 48kHz,
88.2kHz, and 96kHz sampling rates and all three sampling modes of the PCM4201
• An external clock input allows operation at alternative sampling frequencies
As shipped, the PCM4201EVM requires +15V, –15V, and +5V analog power supplies. Options are
provided to operate the analog section from a single power supply by utilizing alternative op amps for the
input buffer circuit. A +5V digital supply is required, with a +3.3V digital supply being derived onboard
using a Texas Instruments REG1117 voltage regulator IC. Connections are provided for an external digital
supply for the PCM4201, allowing digital operation down to +1.8V.
1.2 PCM4201EVM General Description and Functional Block Diagram
The PCM4201EVM provides a complete platform for evaluating the performance and features of the
PCM4201 single channel audio A/D converter. Figure 2 illustrates the functional block diagram for the
evaluation module.
Introduction
Figure 2. PCM4201EVM Functional Block Diagram
PCM4201EVM User's GuideSBAU108A – January 2005 – Revised February 2005 3
www.ti.com
Introduction
A differential analog input is supported at connector J1. The analog input supports either a 3-pin male XLR
or balanced TRS input plug. The analog input is buffered and filtered using a low noise input circuit,
utilizing a Texas Instruments' OPA2134 dual audio op amp IC. The output of the buffer circuit is connected
to the differential input of the PCM4201, which is then used to convert the analog signal to a 24-bit linear
PCM representation in the digital domain.
The 24-bit PCM output data is made available at header J3. The audio data can also be routed to the
DIT4096 digital interface transmitter, supporting an AES3-encoded output, which is provided at BNC
connector J5. The buffered header is convenient for interfacing to external development hardware or
digital signal processors, while the AES3-encoded outputs may be connected to audio test systems or
commercial audio equipment.
Power is connected to the board at either terminal block J2 for the analog supplies, or at terminal block J6
for the digital supplies.
Manual reset circuits are provided for both the PCM4201 (U1) and the DIT4096 (U7). The ADC RESET
switch (SW2) is utilized for resetting the A/D converter, while the DIT RESET switch (SW3) is utilized for
resetting the AES3 transmitter.
The system or master clock for the evaluation module may be generated onboard or by an external clock
source. Oscillators X1 and X2 operate at fixed clock frequencies of 22.5792MHz and 24.576MHz,
respectively. The oscillators provide low jitter clock sources for measuring the performance of the
PCM4201 in Master mode operation. Alternatively, an external clock source may be connected at J4 for
Master mode operation, supporting alternative sampling rates. For Slave mode operation, the system
clock is provided from an external source through header J3. Switch SW1 provides configuration control
for the PCM4201, the DIT4096, the onboard oscillators, and the external clock input at connector J4.
1.3 Related Documentation from Texas Instruments
The following documents provide information regarding Texas Instruments integrated circuits used in the
assembly of the PCM4201EVM. The latest revisions of these documents are available from the TI web
site at www.ti.com .
Data Sheet Literature Number
PCM4201 Datasheet SBAS342
DIT4096 Datasheet SBOS225
OPA2134 Datasheet SBOS058
REG1117 Datasheet SBVS001
SN74ALVC245 Datasheet SCES271
SN74LVC1G04 Datasheet SCES214
SN74LVC1G08 Datasheet SCES217
SN74LVC1G125 Datasheet SCES223
1.4 Additional Documentation
The following documents or references provide information regarding selected non-TI components used in
the assembly of the PCM4201EVM. These documents are available from the corresponding manufacturer.
Document/Reference Manufacturer
SM7745H Series CMOS Oscillators Pletronics (http://www.pletronics.com )
PCM4201EVM User's Guide4 SBAU108A – January 2005 – Revised February 2005
www.ti.com
2 Getting Started
This section provides information regarding handling, package contents, and absolute operating conditions
for the PCM4201EVM.
2.1 Electrostatic Discharge Warning
Failure to observe proper ESD handling precautions may result in damage
to EVM components.
Many of the components used in the assembly of the PCM4201EVM are susceptible to damage by
electrostatic discharge (ESD). Customers are advised to observe proper ESD handling procedure when
unpacking and handling the PCM4201EVM. All handling should be performed at an approved ESD
workstation or test bench, using a grounded wrist strap. Failure to observe proper handling procedure may
result in damage to the EVM and/or the module components.
2.2 EVM Package Contents
Upon opening the PCM4201EVM package, please check to make sure that these items are included:
• One PCM4201EVM evaluation module
• One printed copy of the PCM4201 product datasheet
• One printed copy of this PCM4201EVM User’s Guide
If any of these items are missing, please contact the TI Product Information Center in your region.
Getting Started
CAUTION
2.3 Absolute Operating Conditions
The user should be aware of the absolute operating conditions for the PCM4201EVM. Table 1
summarizes the critical data points.
Power Supplies
+15V +5.0 +18.0 V
-15V -5.0 -18.0 V
+5VA +4.5 +5.5 V
+5VD +4.5 +5.5 V
EXT VDD +1.8 +3.6 V
Audio Serial Port (J3)
VIH, Input High Voltage 0.7 x V
VIL, Input Low Voltage -0.3 0.3 x V
External Clock Input (J4)
VIH, Input High Voltage 0.7 x V
VIL, Input Low Voltage -0.3 0.3 x V
Analog Inputs (J1)
Input Voltage, Differential 0 18.5 V
CAUTION
Exceeding the absolute operating conditions may result in damage to the
evaluation module and/or the equipment connected to it.
Table 1. Absolute Operating Conditions
Min Max Units
DD
DD
+3.6 V
DD
+3.6 V
DD
V
V
PP
PCM4201EVM User's GuideSBAU108A – January 2005 – Revised February 2005 5
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Hardware Description and Configuration
3 Hardware Description and Configuration
This section provides hardware description and configuration information for the PCM4201EVM.
3.1 Power Supply Configuration
The PCM4201EVM requires three analog power supplies and one digital power supply for operation. The
analog supplies are connected at terminal block J2, while the digital supply is connected at terminal block
J6.
Analog supplies include +15V and –15V DC for powering the input buffer circuit, as well as +5.0V DC for
powering the analog section of the PCM4201. All supplies should be rated for at least 500mA of output
current.
The digital supply requires +5.0V DC and should be rated for at least 500mA of output current. The +5.0V
supply is regulated to +3.3V DC by an onboard Texas Instruments REG1117 linear voltage regulator
(U10), which is used to power the digital section of the PCM4201 and the majority of the support logic
circuitry. The core logic and line driver sections of the AES3 transmitter (U7) utilize the +5.0V digital
supply directly.
An optional external VDD power supply is supported at terminal block J6. Jumper JMP4 is utilized to
select either the onboard +3.3V voltage regulator (U10) or an external power source. Shorting pins 1 and
2 together using the supplied jumper block selects the onboard +3.3V voltage regulator. Shorting pins 3
and 4 together will select the external supply (EXT VDD) on terminal block J6. Only one source may be
selected at any time.
The External VDD may be operated as low as +1.8V. However, the DIT4096 transmitter will only operate
at voltages down to +2.0V. Use the audio serial port interface at header J3 when operating VDD at
voltages lower than +2.0V.
3.2 Analog Input
The PCM4201EVM includes a Neutrik combo XLR connector (J1), which accepts either a 3-pin male XLR
or a 1/4-inch TRS phono plug. The analog input can accept up to a 18.5V
signal is then attenuated by a factor of 3.7 by the input buffer circuit, which corresponds to the 5.0V
scale differential input voltage for the PCM4201 analog input.
The input buffer circuit is comprised of an OPA2134 dual audio operational amplifier and associated
passive components. The input buffer provides active attenuation and low-pass filtering for the analog
input signal. The OPA2134 is biased to approximately +2.5V, with the bias voltage being derived from the
+5V analog supply using a voltage divider.
The input buffer circuit may be configured to accept either dual or single supply op amps. Jumper JMP2
allows the –15V supply to be shorted to ground. The +15V may then be adjusted to the appropriate single
supply voltage for the op amp. When using a single supply op amp, it may be necessary to change the
values of the buffer feedback and input resistors in order to adjust the gain or attenuation to match the
maximum input/output voltage swing allowed by the single supply configuration.
3.3 System Clock Configuration
The OSC1 and OSC2 elements of switch SW1 are utilized to select the system clock source for the
PCM4201EVM. Table 2 summarizes the available options. The onboard oscillators support 44.1kHz,
48kHz, 88.2kHz, and 96kHz sampling rates for Master mode audio serial port operation. Alternatively, the
external clock input (J4) may be used to supply the system clock from an external source, supporting
additional sampling rates.
For Slave mode operation, the system clock is input at the SCKI pin of the audio serial port header (J3).
differential input signal. This
PP
full
PP
6 SBAU108A – January 2005 – Revised February 2005PCM4201EVM User's Guide
www.ti.com
F
3dB
f
S
48,000
, where fS output sampling rate
OSC2 OSC1 SYSTEM CLOCK SOURCE
LO HI X1, 22.5792MHz
HI LO X2, 24.576MHz
LO LO External Clock from connector J3 or J4
3.4 Sampling Mode Selection
The PCM4201 supports three sampling modes, allowing the user to select the best power/performance
combination for a given application.
The Normal Speed Low Power mode provides the lowest overall power dissipation while supporting
sampling rates up to 54kHz. The modulator oversampling rate is 64f
The Normal Speed High Performance mode provides the best dynamic performance at the expense of
increased power dissipation. Sampling rates up to 54kHz are supported. The modulator oversampling rate
is 128f
Power mode.
The Double Speed mode supports sampling frequencies up to 108kHz with power dissipation just slightly
higher than the Normal Speed High Performance mode. The modulator oversampling rate is 64f
mode.
The sampling mode is selected using the RATE VDD and RATE GND elements of switch SW1. Table 3
shows the settings required for each sampling mode.
Hardware Description and Configuration
Table 2. System Clock Source Selection
for this mode.
S
for this mode, improving the overall dynamic range and THD+N when compared to the Low
S
for this
S
RATE VDD RATE GND SAMPLING MODE
OFF ON Double Speed
ON OFF Normal Speed Low Power
OFF OFF Normal Speed High Performance
3.5 Digital High-Pass Filter
The PCM201 includes a digital high-pass filter, which is utilized to remove the DC component from the
digitized signal. The high-pass filter is located at the output of the digital decimation filter in the overall A/D
signal chain. The –3dB corner frequency of the high-pass filter is set by the following relationship:
The digital high-pass filter may be enabled or disabled using the HPFD element of switch SW1. Table 4
summarizes the HPFD switch settings. There may be a small increase distortion for low frequency inputs
(less than 100Hz) when the high-pass filter is enabled.
HPFD HIGH-PASS FILTER FUNCTION
LO Enabled
Table 3. Sampling Mode Selection
Table 4. Digital High-Pass Filter Configuration
HI Disabled
PCM4201EVM User's GuideSBAU108A – January 2005 – Revised February 2005 7
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