Texas Instruments PCM3070 Technical data

PCM3070 Application Reference Guide

Reference Guide

Literature Number: SLAU332

March 2011

Chapter 1

SLAU332–March 2011

PCM3070 Overview

• Chapter 1: Device Overview

• Chapter 2: PCM3070 Application

• Chapter 3: Device Initialization

• Chapter 4: Example Setups

• Chapter 5: Register Map and Descriptions

space

Features Applications

• Stereo Audio DAC with 100dB SNR • Soundbar

• Stereo Audio ADC with 93dB SNR • Flat Panel Television

• Extensive Signal Processing Options • MP3 Docking stations

• Embedded miniDSP • Cell Phone Docking Stations

• Six Single-Ended or 3 Fully-Differential Analog • Other Stereo or 2.1 Home Audio systems Inputs

• Stereo Headphone Outputs programmable inputs and outputs,

• Stereo Line Outputs

• Very Low-Noise PGA

• Analog Bypass Mode

• Programmable PLL

• Integrated LDO

• 5mm x 5mm 32-pin QFN Package

The PCM3070 is a flexible stereo audio codec with fully-programmable miniDSP, fixed predefined and

parameterizable signal processing blocks, integrated PLL, integrated LDOs and flexible digital interfaces.

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SPI_Select

IN1_R

IN2_R

IN3_R

IN3_L

IN2_L

IN1_L

SCL/SSZ

Left

ADC

DRC

Left DAC

AGC

ADC

Signal

Proc.

DAC

Signal

Proc.

Right

ADC

DRC

Right DAC

AGC

ADC

Signal

Proc.

DAC

Signal

Proc.

Vol. Ctrl

Data

Interface

Gain Adj.

0… +47.5 dB

0.5 dB steps

0…+47.5 dB

0.5 dB steps

-6...+29dB

1dB steps

-6...+29dB

1dB steps

-6...+29dB

1dB steps

-6...+29dB

1dB steps

SPI / I2C

Control Block

Pin Muxing/ Clock Routing

Secondary

I2S IF

Primary

I2S Interface

Interrupt

Ctrl

ALDO

DLDO

PLL

Ref

LDO Select

Supplies

LDO in

HPVdd

DVdd

AVdd

IOVdd

AVss

DVss

IOVss

SDA/MOSI

MISO

SCLK

MCLK

GPIO

DOUT

DIN

BCLK

WCLK

miniDSP miniDSP

HPL

LOL

HPR

LOR

Reset

-30...0 dB

-72...0dB

´ ´

´´

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1.1 Description

Description

Figure 1-1. Simplified Block Diagram

The PCM3070 features two fully-programmable miniDSP cores that support application-specific algorithms in the record and/or the playback path of the device. The miniDSP cores are fully software controlled. Target algorithms, like speaker EQ, Crossovers, Dynamic Range Controls, Intelligent volume controls and other post-processing algorithms are loaded into the device after power-up.

Extensive register-based control of input/output channel configuration, gains, effects, pin-multiplexing and clocks is included, allowing the device to be precisely targeted to its application.

The record path of the PCM3070 covers operations from 8kHz mono to 192kHz stereo recording, and contains programmable input channel configurations covering single-ended and differential setups, as well as floating or mixed input signals.

The playback path offers signal-processing blocks for filtering and effects, and supports flexible mixing of DAC and analog input signals as well as programmable volume controls. The playback path contains two high-power output drivers as well as two fully-differential outputs. The high-power outputs can be configured in multiple ways, including stereo and mono BTL.

The voltage supply range for the PCM3070 for analog is 1.5V–1.95V, and for digital it is 1.26V–1.95V. To ease system-level design, LDOs are integrated to generate the appropriate analog or digital supply from input voltages ranging from 1.8V to 3.6V. Digital I/O voltages are supported in the range of 1.5V–3.6V.

The required internal clock of the PCM3070 can be derived from multiple sources, including the MCLK pin, the BCLK pin, the GPIO pin or the output of the internal PLL, where the input to the PLL again can be derived from the MCLK pin, the BCLK or GPIO pins. The PLL is highly programmable and can accept available input clocks in the range of 512kHz to 50MHz.

The device is available in the 5mm × 5mm, 32-pin QFN package.

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PCM3070

SCL SDA

IN1_L

IN1_R

IN2_L

IN2_R

IN3_L

IN3_R

MCLK

BCLK

WCLK

DIN

DOUT

DIR9001

TAS57xx

LOL

LOR

HPL

HPR

100W

1 Fm

1KW

0.047 Fm

TPA3123

LDOIN

LDO_SELECT

IOVDD

IOVSS

DVSS

AVSS

REF

DVDD

AVDD

3V3

47 Fm

MSP430

Headphone

Output

47 Fm

1 Fm

100W

1KW

7.5KW

2.49KW

0.47 Fm

2.49KW

7.5KW

2.49KW

0.47 Fm

2.49KW

7.5KW

2.49KW

0.47 Fm

2.49KW

7.5KW

10 Fm

0.1 Fm

1 Fm

Typical Circuit Configuration

1.2 Typical Circuit Configuration

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Figure 1-2. Typical Circuit Configuration

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2.1 Terminal Descriptions

2.1.1 Digital Pins

Only a small number of digital pins are dedicated to a single function; whenever possible, the digital pins have a default function, and also can be reprogrammed to cover alternative functions for various applications.

The fixed-function pins are Reset and the SPI_Select pin, which are HW control pins. Depending on the state of SPI_Select, the two control-bus pins SCL/SS and SDA/MOSI are configured for either I2C or SPI protocol.

Other digital IO pins can be configured for various functions via register control. An overview of available functionality is given in Section 2.1.3.

2.1.2 Analog Pins

Chapter 2

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PCM3070 Application

Analog functions can also be configured to a large degree. Analog blocks are powered down by default. The blocks can be powered up with fine granularity according to the application needs.

2.1.3 Multifunction Pins

Table 2-1 shows the possible allocation of pins for specific functions. The PLL input, for example, can be

programmed to be any of 4 pins (MCLK, BCLK, DIN, GPIO).

Pin Function MCLK BCLK WCLK DIN DOUT MFP3/ MFP4/ GPIO

A PLL Input S B Codec Clock Input S C I2S BCLK input S D I2S BCLK output E E I2S WCLK input E, D F I2S WCLK output E G I2S ADC word clock input E E H I2S ADC WCLK out E E I I2S DIN E, D J I2S DOUT E, D K General Purpose Output I E K General Purpose Output II E

Table 2-1. Multifunction Pin Assignments

1 2 3 4 5 6 7 8

MFP1 MFP2 SCLK MISO MFP5

(1)

(1),D(4)

(2)

(5)

E S

(3)

(1)S(1)

: The MCLK pin can be used to drive the PLL and Codec Clock inputs simultaneously

(2)S(2)

: The BCLK pin can be used to drive the PLL and Codec Clock and audio interface bit clock inputs simultaneously

(3)S(3)

: The GPIO/MFP5 pin can be used to drive the PLL and Codec Clock inputs simultaneously

(4)

D: Default Function

(5)

E: The pin is exclusively used for this function, no other function can be implemented with the same pin (e.g. if GPIO/MFP5 has been allocated for General Purpose Output, it cannot be used as the INT1 output at the same time)

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Terminal Descriptions

Pin Function MCLK BCLK WCLK DIN DOUT MFP3/ MFP4/ GPIO

K General Purpose Output III E L General Purpose Input I E L General Purpose Input II E L General Purpose Input III E M INT1 output E E E N INT2 output E E E Q Secondary I2S BCLK input E E R Secondary I2S WCLK in E E S Secondary I2S DIN E E T Secondary I2S DOUT E U Secondary I2S BCLK OUT E E E V Secondary I2S WCLK OUT E E E W Reserved X Aux Clock Output E E E

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Table 2-1. Multifunction Pin Assignments (continued)

1 2 3 4 5 6 7 8

MFP1 MFP2 SCLK MISO MFP5

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2.1.4 Register Settings for Multifunction Pins

To configure the settings seen in Table 2-1, please see the letter/number combination in Table 2-2 for the appropriate registers to modify.

Please be aware that more settings may be necessary to obtain a full interface definition matching the application requirement (e.g. register Page 0 / Register 25 to 33).

Table 2-2. Multifunction Pin Register Configuration

Description Required Register Setting Description

A1 PLL Input on MCLK M5

A2 PLL Input on BCLK M7

A4 PLL Input on DIN/MFP1 M8

A8 PLL Input on GPIO/MFP5 N5 INT2 output DOUT/MFP2

Codec Clock Input on Page 0 / Register 4, Bits INT2 output on Page 0 / Register 55, Bits

B1 N7

MCLK D1-D0=00 MISO/MFP4 D4-D1=0101 Codec Clock Input on Page 0 / Register 4, Bits INT2 output on Page 0 / Register 52, Bits

B2 N8

BCLK D1-D0=01 GPIO/MFP5 D5-D2=0110

Codec Clock Input on D5-D2=0001 Secondary I2S BCLK input D2-D1=01

B8 Q6

GPIO/MPF5 Page 0 / Register 4, Bits on SCLK/MFP3 Page 0 / Register 31, Bits

C2 I2S BCLK input on BCLK Q8

D2 I2S BCLK output on BCLK R6

E3 I2S WCLK input on WCLK R8

F3 I2S WCLK output WCLK S6

I2S ADC word clock input D2-D1=01 Secondary I2S DIN on D5-D2=0001

G6 S8

on SCLK/MFP3 Page 0 / Register 31, Bits GPIO/MFP5 Page 0 / Register 31, Bit

I2S ADC word clock input D5-D2=0001 Secondary I2S DOUT on Page 0 / Register 55, Bits

G8 T7

on GPIO/MFP5 Page 0 / Register 31, Bits MISO/MFP4 D4-D1=1000

Page 0 / Register 4, Bits INT1 output on Page 0 / Register 53, Bits D3-D2=00 DOUT/MFP2 D3-D1=100

Page 0 / Register 4, Bits INT1 output on Page 0 / Register 55, Bits D3-D2=01 MISO/MFP4 D4-D1=0100

Page 0 / Register 54, Bits D2-D1=01 INT1 output on Page 0 / Register 52, Bits Page 0 / Register 4, Bits GPIO/MFP5 D5-D2=0101 D3-D2=11

Page 0 / Register 52, Bits D5-D2=0001 Page 0 / Register 53,Bits Page 0 / Register 4, Bits D3-D1=101 D3-D2=10

Page 0 / Register 52, Bits Page 0 / Register 56, Bits

D1-D0=10 D6-D5=01

Page 0 / Register 27, Bit Secondary I2S BCLK input D5-D2=0001 D3=0 on GPIO/MFP5 Page 0 / Register 31, Bits

Page 0 / Register 27, Bit Secondary I2S WCLK in on D2-D1=01 D3=1 SCLK/MFP3 Page 0 / Register 31, Bits

Page 0 / Register 27, Bit Secondary I2S WCLK in on D5-D2=0001 D2=0 GPIO/MFP50 Page 0 / Register 31, Bits

Page 0 / Register 27, Bit Secondary I2S DIN on D2-D1=01 D2=1 SCLK/MFP3 Page 0 / Register 31, Bit

Page 0 / Register 56, Bits Page 0 / Register 52, Bits

D2-D1=01 D0=0 Page 0 / Register 52, Bits

D2-D1=00

Terminal Descriptions

Required Register Setting

Page 0 / Register 52, Bits

D6-D5=00 Page 0 / Register 56, Bits

D4-D3=01 Page 0 / Register 52, Bits

D4-D3=0 Page 0 / Register 56, Bits

D0=1

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Analog Audio I/O

H7 U5

H8 U7

I4 I2S DIN on DIN/MFP1 U8

J5 V5

K5 V7

K7 V8

K8 W0 Reserved Reserved

L4 X5

L6 X7

L8 X8

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Table 2-2. Multifunction Pin Register Configuration (continued)

Description Required Register Setting Description

I2S ADC WCLK out on Page 0 / Register 55, Bits Secondary I2S BCLK OUT Page 0 / Register 53, Bits MISO/MFP4 D4-D1=0110 on DOUT/MFP2 D3-D1=110

I2S ADC WCLK out on Page 0 / Register 52, Bits Secondary I2S BCLK OUT Page 0 / Register 55, Bits GPIO/MFP5 D5-D2=0111 on MISO/MFP4 D4-D1=1001

Page 0 / Register 54, Bits Secondary I2S BCLK OUT Page 0 / Register 52, Bits D2-D1=01 on GPIO/MFP5 D5-D2=1000

I2S DOUT on Page 0 / Register 53, Bits Secondary I2S WCLK OUT Page 0 / Register 53, Bits DOUT/MFP2 D3-D1=001 on SCLK/MFP3 D3-D1=111

General Purpose Out I on Page 0 / Register 53, Bits Secondary I2S WCLK OUT Page 0 / Register 55, Bits DOUT/MFP2 D3-D1=010 on MISO/MFP4 D4-D1=1010

General Purpose Out II Page 0 / Register 55, Bits Secondary I2S WCLK OUT Page 0 / Register 52, Bits on MISO/MFP4 D4-D1=0010 on GPIO/MFP5 D5-D2=1001

General Purpose Out III Page 0 / Register 52, Bits on GPIO/MFP5 D5-D2=0011

General Purpose In I on Page 0 / Register 54, Bits Aux Clock Output on Page 0 / Register 53, Bits DIN/MFP1 D2-D1=10 DOUT/MFP2 D3-D1=011

General Purpose In II on Page 0 / Register 56, Bits Aux Clock Output on Page 0 / Register 55, Bits SCLK/MFP3 D2-D1=10 MISO/MFP4 D4-D1=0011

General Purpose In III on Page 0 / Register 52, Bits Aux Clock Output on Page 0 / Register 52, Bits GPIO/MFP5 D5-D2=0010 GPIO/MFP5 D5-D2=0100

Required Register Setting

2.2 Analog Audio I/O

The analog I/O path of the PCM3070 features a large set of options for signal conditioning as well as signal routing:

• 6 analog inputs which can be mixed and/or multiplexed in single-ended and/or differential configuration

• 2 programmable gain amplifiers (PGA) with a range of 0 to +47.5dB

• 2 mixer amplifiers for analog bypass

• 2 low power analog bypass channels

• Mute function

• Automatic gain control (AGC)

• Channel-to-channel phase adjustment

• Fast charge of ac-coupling capacitors

• Anti thump

2.2.1 Analog Bypass

The PCM3070 offers two analog-bypass modes. In either of the modes, an analog input signal can be routed from an analog input pin to an amplifier driving an analog output pin. Neither the ADC nor the DAC resources are required for such operation.

In analog low-power bypass mode, line-level signals can be routed directly from the analog inputs INL to the left headphone amplifier (HPL) and INR to HPR.

2.2.2 ADC Bypass Using Mixer Amplifiers

In addition to the analog bypass mode, there is a bypass mode that uses the programmable gain amplifiers of the input stage in conjunction with a mixer amplifier. With this mode, low-level signals can be amplified and routed to the line or headphone outputs, fully bypassing the ADC and DAC.

To enable this mode, the mixer amplifiers are powered on via software command.

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LADC

IN3_R

IN2_R

IN1_R

HPL

CM HP

MAR

LDAC

MAL

IN1L

IN1_L

IN2_L

IN3_L

LOL

MAL

HPR

CM HP

MAR

RDAC

HPL

IN1R

LOR

MAR

RDAC

LDAC

Left ADC LeftDAC

RightDAC

IN1_R

IN2_R

IN3_R

IN1_L

IN3_L

IN2_L

LeftChannel,InputOptions:

SingleEnded: IN1_L orIN2_L orIN3_L orIN1_R

Differential: IN2_L and IN2_Ror

IN3_L and IN3_R

RightChannel, InputOptions:

SingleEnded: IN1_RorIN2_RorIN3_RorIN2_L

Differential: IN1_Rand IN1_L or

IN3_Rand IN3_L

VolCtrl 0… -72dB

Headphone

Amplifier

-6dB … + 29 dB

CMLO

LineOut Amplifier

-6dB … + 29 dB

RDAC

LineOut Amplifier

-6dB … + 29 dB

LDAC

LADCLeft ADC

MixerAmp

0..-30dB

LDOIN

AVDD

LOR

1,10,6

CM2L

CM1L

CM1R

CM2R

Headphone

Amplifier

-6dB … + 29 dB

MicPGA

0...47.5 dB

MicPGA

0...47.5 dB

VolCtrl 0… -72dB

MixerAmp

0..-30dB

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Analog Audio I/O

Figure 2-1. Analog Routing Diagram

In analog low-power bypass mode, line-level signals can be routed directly from the analog inputs IN1L to the left headphone amplifier (HPL) and IN1R to HPR. This is configured on Page 1/ Register 12, Bit D2 for the left channel and Page 1 / Register 13, Bit D2 for the right channel.

To use the mixer amplifiers, power them on via Page / Register 9, Bits D1-D0.

2.2.3 Headphone Output

The stereo headphone drivers on pins HPL and HPR can drive loads with impedances down to 16Ω in single-ended AC-coupled headphone configurations, or loads down to 32Ω in differential mode, where a speaker is connected between HPL and HPR. In single-ended drive configuration these drivers can drive up to 15mW power into each headphone channel while operating from 1.8V analog supplies. While running from the AVdd supply, the output common-mode of the headphone driver is set by the common-mode setting of analog inputs in Page 1 / Register 10, Bit D6, to allow maximum utilization of the analog supply range while simultaneously providing a higher output-voltage swing. In cases when higher output-voltage swing is required, the headphone amplifiers can run directly from the higher supply voltage on LDOIN input (up to 3.6V). To use the higher supply voltage for higher output signal swing, the output common-mode can be adjusted to either 1.25V, 1.5V or 1.65V by configuring Page 1 / Register 10, Bits D5-D4. When the common-mode voltage is configured at 1.65V and LDOIN supply is 3.3V, the headphones can each deliver up to 40mW power into a 16Ω load.

The headphone drivers are capable of driving a mixed combination of DAC signal and bypass from analog input INL and INR by configuring Page 1 / Register 12 and Page 1 / Register 13 respectively. The analog input signals can be attenuated up to 72dB before routing by configuring Page 1 / Register 22 and 23. The level of the DAC signal can be controlled using the digital volume control of the DAC in Page 0, Reg 65

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HPL

HPR

LEFT DAC

RIGHT DAC

LEFT HEADPHONE AMP

RIGHT HEADPHONE AMP

INL

INR

Page 1 / Register 12

Page 1 / Register 13

Rload

Rpop

Output

Driver

PAD

Analog Audio I/O

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and 66. To control the output-voltage swing of headphone drivers, the digital volume control provides a range of –6.0dB to +29.0dB

(1)

in steps of 1dB. These can be configured by programming Page 1 / Register 16 and 17. These level controls are not meant to be used as dynamic volume control, but more to set output levels during initial device configuration. Refer to for recommendations for using headphone volume control for achieving 0dB gain through the DAC channel with various configurations.

2.2.4 Stereo Single Ended Configuration

Figure 2-2. Stereo Headphone Configuration

The left and right DAC channels are routed to the corresponding left and right headphone amplifier. This configuration is also used to drive line-level loads.

Figure 2-3. Conceptual Circuit for Pop-Free Power-up

The value of R

(1)

If the device must be placed into 'mute' from the –6.0dB setting, set the device at a gain of –5.0dB first, then place the device into mute.

can be chosen by setting register Page 1, Register 20, Bits D1-D0).

pop

Table 2-3. R

Page 1, Register 20, Bits D1-D0) R

00 2kΩ 01 6kΩ 10 25kΩ

pop

Values

pop

Value

According to the conceptual circuit in Figure 2-3, the voltage on PAD will exponentially settle to the output common-mode voltage based on the value of R power-up mode for time T, such that at the end of the slow power-on period, the voltage on V close to the common-mode voltage. The PCM3070 allows the time T to be adjusted to allow for a wide range of R value of Ccis assumed to be 47μF. N=5 is expected to yield good results.

PCM3070 Application SLAU332–March 2011

and Cc. Thus, the output drivers must be in slow

and Ccby programming Page 1, Register 20, Bits D5-D2). For the time adjustments, the

load

pop

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pad

is very

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Analog Audio I/O

Page 1, Register 20, Bits Slow Charging Time=N*Time – Constants(for R

D5-D2)

0000 N=0 0001 N=0.5 0010 N=0.625 0011 N=0.75 0100 N=0.875 0101 N=1.0 0110 N=2.0 0111 N=3.0 1000 N=4.0 1001 N=5.0 1010 N=6.0 1011 N=7.0 1100 N=8.0 1101 N=16 (Not valid for R 1110 N=24 (Not valid for R 1111 N=32 (Not valid for R

Again, for example, for R

=25kΩ)

pop

=25kΩ)

pop

=25kΩ)

pop

=32Ω, Cc=47μF and common mode of 0.9V, the number of time constants

load

and 47μF)

pop

required for pop-free operation is 5 or 6. A higher or lower Ccvalue will require higher or lower value for N. During the slow-charging period, no signal is routed to the output driver. Therefore, choosing a larger than

necessary value of N results in a delay from power-up to signal at output. At the same time, choosing N to be smaller than the optimal value results in poor pop performance at power-up.

The signals being routed to headphone drivers (e.g. DAC, MAL , MAR and IN1) often have DC offsets due to less-than-ideal processing. As a result, when these signals are routed to output drivers, the offset voltage causes a pop. To improve the pop-performance in such situations, a feature is provided to soft-step the DC-offset. At the beginning of the signal routing, a high-value attenuation can be applied which can be progressively reduced in steps until the desired gain in the channel is reached. The time interval between each of these gain changes can be controlled by programming Page 1, Register 20, Bits D7-D6). This gain soft-stepping is applied only during the initial routing of the signal to the output driver and not during subsequent gain changes.

Page 1, Register 20, Bits D7-D6 Soft-stepping Step Time During initial signal routing

00 0 ms (soft-stepping disabled) 01 50ms 10 100ms 11 200ms

It is recommended to use the following sequence for achieving optimal pop performance at power-up:

1. Choose the value of R

, N (time constants) and soft-stepping step time for slow power-up.

pop

2. Choose the configuration for output drivers, including common modes and output stage power

connections

3. Select the signals to be routed to headphones.

4. Power-up the blocks driving signals into HPL and HPR, but keep it muted

5. Unmute HPL and HPR and set the desired gain setting.

6. Power-on the HPL and HPR drivers.

7. Unmute the block driving signals to HPL and HPR after the Driver PGA flags are set to indicate

completion of soft-stepping after power-up. These flags can be read from Page 1, Register 63, Bits D7-D6).

It is important to configure the Headphone Output driver depop control registers before powering up the headphone; these register contents should not be changed when the headphone drivers are powered up.

Before powering down the HPL and HPR drivers, it is recommended that user read back the flags in Page

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LEFT

DAC

HPL

HPR

LEFT_DACP

LEFT_DACM

Analog Audio I/O

1, Register 63. For example. before powering down the HPL driver, ensure that bit D(7) = 1 and bit D(3) = 1 if INL is routed to HPL and bit D(1) = 1 if the Left Mixer is routed to HPL. The output driver should be powered down only after a steady-state power-up condition has been achieved. This steady state power-up condition also must be satisfied for changing the HPL/R driver mute control in Page 1, Register 16 and 17, Bits D7), i.e. muting and unmuting should be done after the gain and volume controls associated with routing to HPL/R finished soft-stepping.

In the differential configuration of HPL and HPR, when no coupling capacitor is used, the slow charging method for pop-free performance need not be used. In the differential load configuration for HPL and HPR, it is recommended to not use the output driver MUTE feature, because a pop may result.

During the power-down state, the headphone outputs are weakly pulled to ground using an approximately 50kΩ resistor to ground, to maintain the output voltage on HPL and HPR pins.

2.2.5 Mono Differential DAC to Mono Differential Headphone Output

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Figure 2-4. Low Power Mono DAC to Differential Headphone

This configuration supports the routing of the two differential outputs of the mono, left channel DAC to the headphone amplifiers in differential mode (Page 1 / Register 12, D3 =1 and Page 1 / Register 13, D4 =1).

2.2.6 Headphone Amplifier Class-D Mode

By default the headphone amplifiers in the PCM3070 work in Class-AB mode. By writing to Page 1, Register 3, Bits D7-D6) for the left headphone amplifier, and Page 1, Register 4, Bits D7-D6) with value 11, the headphone amplifiers enter a Class-D mode of operation.

In this mode a high frequency digital pulse-train representation of the DAC signal is fed to the load connected to HPL and HPR outputs.

Because the output signal is a pulse train switching between Power Supply and Ground, the efficiency of the amplifier is greatly improved. In this mode however, for good noise performance, care should be taken to keep the analog power supply clean.

For using the Class-D mode of operation, the following clock-divider condition should be met:

MDAC = I × 4, where I = 1, 2, ..., 32

When a direct digital pulse train is driven out as a signal, high frequencies as a function of pulse train frequency are also present which lead to power waste. To increase the efficiency and reduce power dissipation in the load due to these high frequencies, an LC filter should be used in series with the output and the load. The cutoff frequency of the LC filter should be adjusted to allow audio signals below 20kHz to pass through, but highly attenuate the high-frequency signal content.

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L =82 Hm

C =47 FCm

C=1 Fm

Rload=32 W

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Figure 2-5. Configuration for Using Headphone Amplifier in Class-D Mode

For using the headphones in the Class-D mode of operation, the headphones should first be powered up in default Class-AB mode to charge the AC-coupling capacitor to the set common mode voltage. Once the headphone amplifiers have been so powered up, the DAC should be routed to headphones and unmuted before they can be switched to the Class-D mode. After Class D mode has been turned on, the linear, Class AB mode amplifier must be turned off. For powering down the headphone amplifiers, the DAC should first be muted.

See Section 4.0.2 for an example setup script enabling Class-D mode.

2.2.7 Line Outputs

The stereo line level drivers on LOL and LOR pins can drive a wide range of line level resistive impedances in the range of 600Ω to 10kΩ. The output common modes of line level drivers can be configured to equal either the analog input common-mode setting or to 1.65V. With output common-mode setting of 1.65V and DRVdd_HP supply at 3.3V the line-level drivers can drive up to 1Vrms output signal. The line-level drivers can drive out a mixed combination of DAC signal and attenuated ADC PGA signal. Signal mixing is register-programmable.

ADC

2.3 ADC

The PCM3070 includes a stereo audio ADC, which uses a delta-sigma modulator with a programmable oversampling ratio, followed by a digital decimation filter. The stereo recording path can be powered up one channel at a time, to support the case where only mono record capability is required.

The ADC path of the PCM3070 features a large set of options for signal conditioning as well as signal routing:

• 2 ADCs

• 6 analog inputs which can be mixed and/or multiplexed in single-ended and/or differential configuration

• 2 programmable gain amplifiers (PGA) with a range of 0 to +47.5dB

• 2 mixer amplifiers for analog bypass

• 2 analog bypass channels

• Fine gain adjust of digital channels with 0.1 dB step size

• Digital volume control with a range of -12 to +20dB

• Mute function

• Automatic gain control (AGC) In addition to the standard set of ADC features the PCM3070 also offers the following special functions:

• Channel-to-channel phase adjustment

• Fast charge of ac-coupling capacitors

• Anti thump

• Adaptive filter mode Because of the oversampling nature of the audio ADC and the integrated digital decimation filtering,

requirements for analog anti-aliasing filtering are very relaxed. The PCM3070 integrates a second order analog anti-aliasing filter with 28-dB attenuation at 6MHz. This filter, combined with the digital decimation filter, provides sufficient anti-aliasing filtering without requiring additional external components.

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Analog

Gain

Analog

Input

Selection

ADC

Filtering

Digital

Volume

Control

Digital

Gain

Adjust

0...47.5 dB

Step =0.5 dB

0, -6, -12 dB -12...20 dB

Step =0.5 dB

0…-0.4 dB

Step= 0.1 dB

Frequency Response/

Gain

Fully

Programmable

Coefficients

Audio

Interface

ADC

PGA

ADC

2.3.1 ADC Signal Routing

As shown in Figure 2-1, the PCM3070 includes six analog inputs which can be configured as either 3 stereo single-ended pairs or 3 fully-differential pairs. These pins connect through series resistors and switches to the virtual ground terminals of two fully-differential amplifiers (one per ADC/PGA channel). By turning on only one set of switches per amplifier at a time, the inputs can be effectively multiplexed to each ADC PGA channel. By turning on multiple sets of switches per amplifier at a time, audio sources can be mixed. The PCM3070 supports the ability to mix up to four single-ended analog inputs or up to two fully-differential analog inputs into each ADC PGA channel.

The PCM3070 allows the user the flexibility of choosing the input impedance from 10kΩ, 20kΩ and 40kΩ. When multiple inputs are mixed together, by choosing different input impedances, level adjustment can be achieved. For example, if one input is selected with 10kΩ input impedance and the second input is selected with 20kΩ input impedance, then the second input is attenuated by half as compared to the first input. Note that this input level control is not intended to be a volume control, but instead used occasionally for level setting.

Mixing of multiple inputs can easily lead to PGA outputs that exceed the range of the internal amplifiers, resulting in saturation and clipping of the mixed output signal. Whenever mixing is being implemented, the system designer is advised to take adequate precautions to avoid such a saturation from occurring. In general, the mixed signal should not exceed 0dB.

Typically, voice or audio signal inputs are capacitively coupled to the device. This allows the device to independently set the common mode of the input signals to values chosen by register control of Page 1, Register 10, D(6) to either 0.9V or 0.75V. The correct value maximizes the dynamic range across the entire analog-supply range. Failure to capacitively connect the input to the device can cause high offset due to mismatch in source common-mode and device common-mode setting. In extreme cases it could also saturate the analog channel, causing distortion.

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2.3.2 ADC Gain Setting

When the gain of the ADC Channel is kept at 0dB and the common mode set to 0.75V, a single-ended input of 0.375V gain is kept at 0dB, and common mode is set to 0.9V, a single-ended input of 0.5V full-scale digital signal at the output of the ADC channel. However various block functions control the gain through the channel. The gain applied by the PGA is described in Table 2-4. Additionally, the digital volume control adjusts the gain through the channel as described in Section 2.3.2.2. A finer level of gain is controlled by fine gain control as described in Section 2.3.2.3. The decimation filters A, B and C along with the delta-sigma modulator contribute to a DC gain of 1.0 through the channel.

2.3.2.1 Analog Programmable Gain Amplifier (PGA)

The PCM3070 features a built-in low-noise PGA for boosting low-level signals to full-scale to achieve high SNR. This PGA can provide a gain in the range of 0dB to 47.5dB for single-ended inputs or 6dB to 53.5dB for fully-differential inputs (gain calculated w.r.t. input impedance setting of 10kΩ, 20kΩ input impedance will result in 6dB lower and 40kΩ will result in 12dB lower gain). This gain can be user controlled by writing to Page 1, Register 59 and Page 1, Register 60. In the AGC mode this gain can also be automatically controlled by the built-in hardware AGC.

results in a full-scale digital signal at the output of ADC channel. Similarly, when the

RMS

results in a

RMS

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Page 1, EFFECTIVE GAIN APPLIED BY PGA Register 59, D(6:0) Page 1, Register 60, D(6:0)

000 0000 0dB –6dB -12dB 6.0dB 0dB –6.0dB 000 0001 0.5dB –5.5dB –11.5dB 6.5dB 0.5dB -5.5dB 000 0010 1.0dB –5.0dB –11.0dB 7.0dB 7.5dB –5.0dB … … … … … … … 101 1110 47.0dB 41.0dB 35.0dB 53.0dB 47.0dB 41.0dB 101 1111 47.5dB 41.5dB 35.5dB 53.5dB 47.5dB 41.5dB

The gain changes are implemented with an internal soft-stepping algorithm that only changes the actual volume level by one 0.5dB step every one or two ADC output samples, depending on the register value (see registers Page 0, Reg 81, D(1:0)). This soft-stepping ensures that volume control changes occur smoothly with no audible artifacts. On reset, the PGA gain defaults to a mute condition, and at power down, the PGA soft-steps the volume to mute before shutting down. A read-only flag Page 0, Reg 36, D(7) and D(3) is set whenever the gain applied by the PGA equals the desired value set by the register. The soft-stepping control can also be disabled by programming Page 0, Reg 81, D(1:0).

2.3.2.2 Digital Volume Control

The PCM3070 also has a digital volume-control block with a range from -12dB to +20dB in steps of 0.5dB. It is set by programming Page 0, Register 83 and 84 respectively for left and right channels.

ADC

Table 2-4. Analog PGA vs Input Configuration

SINGLE-ENDED DIFFERENTIAL RIN= 10K RIN= 20K RIN= 40K RIN= RIN= RIN= 40K

10K 20K

Table 2-5. Digital Volume Control for ADC

Desired Gain Left / Right Channel dB Page 1, Register 83/84,

–12.0 110 1000 –11.5 110 1001 –11.0 110 1010 .. –0.5 111 1111

0.0 000 0000 (Default) +0.5 000 0001 .. +19.5 010 0111 +20.0 010 1000

D(6:0)

During volume control changes, the soft-stepping feature is used to avoid audible artifacts. The soft-stepping rate can be set to either 1 or 2 gain steps per sample. Soft-stepping can also be entirely disabled. This soft-stepping is configured via Page 1, Register 81, D(1:0), and is common to soft-stepping control for the analog PGA. During power-down of an ADC channel, this volume control soft-steps down to

-12.0dB before powering down. Due to the soft-stepping control, soon after changing the volume control setting or powering down the ADC channel, the actual applied gain may be different from the one programmed through the control register. The PCM3070 gives feedback to the user, through read-only flags Page 1, Reg 36, D(7) for Left Channel and Page 1, Reg 36, D(3) for the right channel.

2.3.2.3 Fine Digital Gain Adjustment

Additionally, the gains in each of the channels is finely adjustable in steps of 0.1dB. This is useful when trying to match the gain between channels. By programming Page 0, Register 82 the gain can be adjusted from 0dB to -0.4dB in steps of 0.1dB. This feature, in combination with the regular digital volume control allows the gains through the left and right channels be matched in the range of -0.5dB to +0.5dB with a resolution of 0.1dB.

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2.3.2.4 AGC

The PCM3070 includes Automatic Gain Control (AGC) for ADC recording. AGC can be used to maintain a nominally-constant output level. As opposed to manually setting the PGA gain, in the AGC mode, the circuitry automatically adjusts the PGA gain as the input signal becomes overly loud or very weak. The AGC algorithm has several programmable parameters, including target gain, attack and decay time constants, noise threshold, and max PGA applicable, that allow the algorithm to be fine tuned for any particular application. The algorithm uses the absolute average of the signal (which is the average of the absolute value of the signal) as a measure of the nominal amplitude of the output signal. Since the gain can be changed at the sample interval time, the AGC algorithm operates at the ADC sample rate.

1. Target Level represents the nominal output level at which the AGC attempts to hold the ADC output

signal level. The PCM3070 allows programming of eight different target levels, which can be programmed from –5.5dB to –24dB relative to a full-scale signal. Since the PCM3070 reacts to the signal absolute average and not to peak levels, it is recommended that the target level be set with enough margin to avoid clipping at the occurrence of loud sounds.

2. Attack Time determines how quickly the AGC circuitry reduces the PGA gain when the output signal

level exceeds the target level due to increase in input signal level. Wide range of attack time programmability is supported in terms of number of samples (i.e. number of ADC sample frequency clock cycles).

3. Decay Time determines how quickly the PGA gain is increased when the output signal level falls

below the target level due to reduction in input signal level. Wide range of decay time programmability is supported in terms of number of samples (i.e., number of ADC sample frequency clock cycles).

4. Gain Hysteresis is the hysteresis applied to the required gain calculated by the AGC function while

changing its mode of operation from attack to decay or vice-versa. For example, while attacking the input signal, if the current applied gain by the AGC is xdB, and suddenly because of input level going down, the new calculated required gain is ydB, then this gain is applied provided y is greater than x by the value set in Gain Hysteresis. This feature avoids the condition when the AGC function can fluctuate between a very narrow band of gains leading to audible artifacts. The Gain Hysteresis can be adjusted or disabled by the user.

5. Noise threshold determines the level below which if the input signal level falls, the AGC considers it

as silence, and thus brings down the gain to 0dB in steps of 0.5dB every FS and sets the noise threshold flag. The gain stays at 0dB unless the input speech signal average rises above the noise threshold setting. This ensures that noise is not 'gained up' in the absence of speech. Noise threshold level in the AGC algorithm is programmable from -30dB to -90dB of full-scale. When AGC Noise Threshold is set to –70dB, –80db, or –90dB, the microphone input Max PGA applicable setting must be greater than or equal to 11.5dB, 21.5dB, or 31.5dB respectively. This operation includes hysteresis and debounce to avoid the AGC gain from cycling between high gain and 0dB when signals are near the noise threshold level. The noise (or silence) detection feature can be entirely disabled by the user.

6. Max PGA applicable allows the designer to restrict the maximum gain applied by the AGC. This can

be used for limiting PGA gain in situations where environmental noise is greater than the programmed noise threshold. Microphone input Max PGA can be programmed from 0dB to 58dB in steps of 0.5dB.

7. Hysteresis, as the name suggests, determines a window around the Noise Threshold which must be

exceeded to either detect that the recorded signal is indeed noise or signal. If initially the energy of the recorded signal is greater than the Noise Threshold, then the AGC recognizes it as noise only when the energy of the recorded signal falls below the Noise Threshold by a value given by Hysteresis. Similarly, after the recorded signal is recognized as noise, for the AGC to recognize it as a signal, its energy must exceed the Noise Threshold by a value given by the Hysteresis setting. In order to prevent the AGC from jumping between noise and signal states, (which can happen when the energy of recorded signal is very close to the Noise threshold) a non-zero hysteresis value should be chosen. The Hysteresis feature can also be disabled.

8. Debounce Time (Noise and Signal) determines the hysteresis in time domain for noise detection.

The AGC continuously calculates the energy of the recorded signal. If the calculated energy is less than the set Noise Threshold, then the AGC does not increase the input gain to achieve the Target Level. However, to handle audible artifacts which can occur when the energy of the input signal is very close to the Noise Threshold, the AGC checks if the energy of the recorded signal is less than the Noise Threshold for a time greater than the Noise Debounce Time. Similarly the AGC starts increasing the input-signal gain to reach the Target Level when the calculated energy of the input signal is greater than the Noise Threshold. Again, to avoid audible artifacts when the input-signal energy is very close to Noise Threshold, the energy of the input signal needs to continuously exceed the Noise Threshold

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9. The AGC Noise Threshold Flag is a read-only flag indicating that the input signal has levels lower

10. Gain Applied by AGC is a ready-only register setting which gives a real-time feedback to the system

11. The AGC Saturation Flag is a read-only flag indicating that the ADC output signal has not reached its

12. The ADC Saturation Flag is a read-only flag indicating an overflow condition in the ADC channel. On

13. An AGC low-pass filter is used to help determine the average level of the input signal. This average

ADC

value for the Signal Debounce Time. If the debounce times are kept very small, then audible artifacts can result by rapid enabling and disabling the AGC function. At the same time, if the Debounce time is kept too large, then the AGC may take time to respond to changes in levels of input signals with respect to Noise Threshold. Both noise and signal debounce time can be disabled.

than the Noise Threshold, and thus is detected as noise (or silence). In such a condition the AGC applies a gain of 0dB.

on the gain applied by the AGC to the recorded signal. This, along with the Target Setting, can be used to determine the input signal level. In a steady state situation Target Level (dB ) = Gain Applied by AGC (dB) + Input Signal Level (dB) When the AGC noise threshold flag is set, then the status of gain applied by AGC should be ignored.

Target Level. However, the AGC is unable to increase the gain further because the required gain is higher than the Maximum Allowed PGA gain. Such a situation can happen when the input signal has very low energy and the Noise Threshold is also set very low. When the AGC noise threshold flag is set, the status of AGC saturation flag should be ignored.

overflow, the signal is clipped and distortion results. This typically happens when the AGC Target Level is kept very high and the energy in the input signal increases faster than the Attack Time.

level is compared to the programmed detection levels in the AGC to provide the correct functionality. This low pass filter is in the form of a first-order IIR filter. Three 8-bit registers are used to form the 24-bit digital coefficient as shown on the register map. In this way, a total of 9 registers are programmed to form the 3 IIR coefficients. The transfer function of the filter implemented for signal level detection is given by

Where:

Coefficient N0 can be programmed by writing into Page 8, Register 12, 13 and 14. Coefficient N1 can be programmed by writing into Page 8, Register 16, 17 and 18. Coefficient D1 can be programmed by writing into Page 8, Register 20, 21 and 22. N0, N1 and D1 are 24-bit 2’s complement numbers and their default values implement a low-pass filter with cut-off at 0.002735*ADC_FS .

See Table 2-6 for various AGC programming options. AGC can be used only if analog microphone input is routed to the ADC channel.

Table 2-6. AGC Parameter Settings

Function Control Register Control Register Bit

Left ADC Right ADC

AGC enable Page 0, Register 86 Page 0,Register 94 D(7) Target Level Page 0, Register 86 Page 0, Register 94 D(6:4) Gain Hysteresis Page 0, Register 86 Page 0, Register 94 D(1:0) Hysteresis Page 0, Register 87 Page 0, Register 95 D(7:6) Noise threshold Page 0, Register 87 Page 0, Register 95 D(5:1) Max PGA applicable Page 0, Register 88 Page 0, Register 96 D(6:0) Time constants (attack time) Page 0, Register 89 Page 0, Register 97 D(7:0) Time constants(decay time) Page 0, Register 90 Page 0, Register 98 D(7:0) Debounce time (Noise) Page 0, Register 91 Page 0, Register 99 D(4:0) Debounce time (Signal) Page 0, Register 92 Page 0, Register 100 D(3:0) Gain applied by AGC Page 0, Register 93 Page 0, Register 101 D(7:0) (Read Only) AGC Noise Threshold Flag Page 0, Register 45 (sticky flag), Page 0, Register 45 (sticky flag), D(6:5) (Read Only)

Page 0, Register 47 (non-sticky Page 0, Register 47 (non-sticky flag) flag)

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DecayTime

Target Level

Input

Signal

Output

Signal

AGC Gain

Attack

Time

ADC

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Table 2-6. AGC Parameter Settings (continued)

Function Control Register Control Register Bit

Left ADC Right ADC

AGC Saturation flag Page 0, Register 36 (sticky flag) Page 0, Register 36 (sticky flag) D(5), D(1) (Read Only) ADC Saturation flag Page 0, Register 42 (sticky flag), Page 0, Register 42 (sticky flag), D(3:2) (Read Only)

Page 0, Register 43 (non-sticky Page 0, Register 43 (non-sticky flag) flag)

Figure 2-6. AGC Characteristics

2.3.3 ADC Decimation Filtering and Signal Processing Overview

The PCM3070 ADC channel includes a built-in digital decimation filter to process the oversampled data from the sigma-delta modulator to generate digital data at Nyquist sampling rate with high dynamic range. The decimation filter can be chosen from three different types, depending on the required frequency response, group delay and sampling rate.

2.3.4 ADC Processing Blocks

The PCM3070 offers a range of processing blocks which implement various signal processing capabilities along with decimation filtering. These processing blocks give users the choice of how much and what type of signal processing they may use and which decimation filter is applied.

Table 2-7 gives an overview of the available processing blocks of the ADC channel and their properties.

The signal processing blocks available are:

• First-order IIR

• Scalable number of biquad filters

• Variable-tap FIR filter

• AGC

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ToAudio

Interface

1stOrder

IIR

AGC Gain

Compen-

sation

AGC

ToAnalog PGA

Filter A

From Delta-Sigma

Modulator

From Digital Vol. Ctrl

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The processing blocks are tuned for common cases and can achieve high anti-alias filtering or low-group delay in combination with various signal processing effects such as audio effects and frequency shaping. The available first order IIR, BiQuad and FIR filters have fully user-programmable coefficients. The Resource Class Column (RC) gives an approximate indication of power consumption.

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ADC

Table 2-7. ADC Processing Blocks

Processing Channel Decimation 1st Order Number FIR Required Resource

Blocks Filter IIR BiQuads AOSR Value Class

PRB_R1

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Stereo A Yes 0 No 128,64 6 PRB_R2 Stereo A Yes 5 No 128,64 8 PRB_R3 Stereo A Yes 0 25-Tap 128,64 8 PRB_R4 Right A Yes 0 No 128,64 3 PRB_R5 Right A Yes 5 No 128,64 4 PRB_R6 Right A Yes 0 25-Tap 128,64 4 PRB_R7 Stereo B Yes 0 No 64 3 PRB_R8 Stereo B Yes 3 No 64 4 PRB_R9 Stereo B Yes 0 20-Tap 64 4

PRB_R10 Right B Yes 0 No 64 2 PRB_R11 Right B Yes 3 No 64 2 PRB_R12 Right B Yes 0 20-Tap 64 2 PRB_R13 Stereo C Yes 0 No 32 3 PRB_R14 Stereo C Yes 5 No 32 4 PRB_R15 Stereo C Yes 0 25-Tap 32 4 PRB_R16 Right C Yes 0 No 32 2 PRB_R17 Right C Yes 5 No 32 2 PRB_R18 Right C Yes 0 25-Tap 32 2

Default

Available

2.3.5 Signal Processing Blocks – Details

2.3.5.1 1storder IIR, AGC, Filter A

Figure 2-7. Signal Chain for PRB_R1 and PRB_R4

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1stOrder

IIR

AGC Gain

Compen-

sation

AGC

Filter A

ToAudio Interface

ToAnalog PGA

From Delta-Sigma

Modulator

From Digital Vol. Ctrl

1stOrder

IIR

AGC Gain

Compen-

sation

AGC

Filter A

25-Tap FIR

From Delta-Sigma

Modulator

ToAnalog PGA

ToAudio Interface

From Digital Vol. Ctrl

ToAudio

Interface

1stOrder

IIR

AGC Gain

Compen-

sation

AGC

Filter B

ToAudio Interface

ToAnalog PGA

From Delta-Sigma

Modulator

From Digital Vol. Ctrl

1stOrder

IIR

AGC Gain

Compen-

sation

AGC

Filter B H

From Delta-Sigma

Modulator

ToAnalog PGA

ToAudio Interface

From Digital Vol. Ctrl

ADC

2.3.5.2 5 Biquads, 1storder IIR, AGC, Filter A

Figure 2-8. Signal Chain PRB_R2 and PRB_R5

2.3.5.3 25 Tap FIR, 1storder IIR, AGC, Filter A

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Figure 2-9. Signal Chain for PRB_R3 and PRB_R6

2.3.5.4 1storder IIR, AGC, Filter B

Figure 2-10. Signal Chain for PRB_R7 and PRB_R10

2.3.5.5 3 Biquads, 1storder IIR, AGC, Filter B

Figure 2-11. Signal Chain for PRB_R8 and PRB_R11

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1stOrder

IIR

AGC Gain

Compen-

sation

AGC

Filter B

20-Tap FIR

From Delta-Sigma

Modulator

To Analog PGA

ToAudio Interface

From Digital Vol. Ctrl

1stOrder

IIR

AGC Gain

Compen-

sation

AGC

Filter C

From Delta-Sigma

Modulator

From Digital Vol. Ctrl

ToAnalog PGA

ToAudio

Interface

1stOrder

IIR

AGC Gain

Compen-

sation

AGC

Filter C

From Delta-Sigma

Modulator

From Digital Vol. Ctrl

ToAnalog PGA

ToAudio

Interface

1stOrder

IIR

AGC Gain

Compen

sation

AGC

Filter C

25-Tap FIR

From Delta-Sigma

Modulator

From Digital Vol. Ctrl

To Analog PGA

To Audio Interface

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2.3.5.6 20 Tap FIR, 1storder IIR, AGC, Filter B

Figure 2-12. Signal Chain for PRB_R9 and PRB_R12

2.3.5.7 1storder IIR, AGC, Filter C

ADC

Figure 2-13. Signal Chain for PRB_R13 and PRB_R16

2.3.5.8 5 Biquads, 1storder IIR, AGC, Filter C

Figure 2-14. Signal Chain for PRB_R14 and PRB_R17

2.3.5.9 25 Tap FIR, 1storder IIR, AGC, Filter C

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Figure 2-15. Signal for PRB_R15 and PRB_R18

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ADC

2.3.5.10 User Programmable Filters

Depending on the selected processing block, different types and orders of digital filtering are available. A 1st-order IIR filter is always available, and is useful to efficiently filter out possible DC components of the signal. Up to 5 biquad section or alternatively up to 25-tap FIR filters are available for specific processing blocks. The coefficients of the available filters are arranged as sequentially indexed coefficients in two banks. If adaptive filtering is chosen, the coefficient banks can be switched on-the-fly. For more details on adaptive filtering see Section 2.3.6.5 below.

The coefficients of these filters are each 24-bits wide, in two's-complement and occupy 3 consecutive 8-bit registers in the register space. For default values please see Section 5.13.

2.3.5.10.1 1stOrder IIR Section

The transfer function for the first order IIR Filter is given by

The frequency response for the 1storder IIR Section with default coefficients is flat at a gain of 0dB. Details on ADC coefficient default values are given in Section 5.13.

Table 2-8. ADC 1st order IIR Filter Coefficients

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Filter FIlter ADC Coefficient Left ADC Coefficient Right Channel

1stOrder IIR N1 C5 (Pg 8,Reg 28,29,30) C37 (Pg 9,Reg 36,37,38)

Coefficient Channel

N0 C4 (Pg 8,Reg 24,25,26) C36 (Pg 9,Reg 32,33,34)

D1 C6 (Pg 8,Reg 32,33,34) C39 (Pg 9,Reg 40,41,42)

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2.3.5.10.2 Biquad Section

The transfer function of each of the Biquad Filters is given by

The frequency response for each of the biquad section with default coefficients is flat at a gain of 0dB. Details on ADC coefficient default values are given in Section 5.13.

ADC

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Table 2-9. ADC Biquad Filter Coefficients

Filter FIlter ADC Coefficient Left ADC Coefficient Right Channel

BIQUAD A N0 C7 (Pg 8, Reg 36,37,38) C39 (Pg 9, Reg 44,45,46)

BIQUAD B N0 C12 (Pg 8, Reg 56,57,58) C44 (Pg 9, Reg 64,65,66)

BIQUAD C N0 C17 (Pg 8, Reg 76,77,78) C49 (Pg 9, Reg 84,85,86)

BIQUAD D N0 C22 (Pg 8, Reg 96,97,98) C54 (Pg 9, Reg 104,105,106)

BIQUAD E N0 C27 (Pg 8, Reg 116,117,118) C59 (Pg 9, Reg 124,125,126)

Coefficient Channel

N1 C8 (Pg 8, Reg 40,41,42) C40 (Pg 9, Reg 48,49,50) N2 C9 (Pg 8, Reg 44,45,46) C41 (Pg 9, Reg 52,53,54) D1 C10 (Pg 8, Reg 48,49,50) C42 (Pg 9, Reg 56,57,58) D2 C11 (Pg 8, Reg 52,53,54) C43 (Pg 9, Reg 60,61,62)

N1 C13 (Pg 8, Reg 60,61,62) C45 (Pg 9, Reg 68,69,70) N2 C14 (Pg 8, Reg 64,65,66) C46 (Pg 9, Reg 72,73,74) D1 C15 (Pg 8, Reg 68,69,70) C47 (Pg 9, Reg 76,77,78) D2 C16 (Pg 8, Reg 72,73,74) C48 (Pg 9, Reg 80,81,82)

N1 C18 (Pg 8, Reg 80,81,82) C50 (Pg 9, Reg 88,89,90) N2 C19 (Pg 8, Reg 84,85,86) C51 (Pg 9, Reg 92,93,94) D1 C20 (Pg 8, Reg 88,89,90) C52 (Pg 9, Reg 96,97,98) D2 C21 (Pg 8, Reg 92,93,94) C53 (Pg 9, Reg 100,101,102)

N1 C23 (Pg 8, Reg 100,101,102) C55 (Pg 9, Reg 108,109,110) N2 C24 (Pg 8, Reg 104,105,106) C56 (Pg 9, Reg 112,113,114) D1 C25 (Pg 8, Reg 108,109,110) C57 (Pg 9, Reg 116,117,118) D2 C26 (Pg 8, Reg 112,113,114) C58 (Pg 9, Reg 120,121,122)

N1 C28 (Pg 8, Reg 120,121,122) C60 (Pg 10, Reg 8,9,10) N2 C29 (Pg 8, Reg 124,125,126) C61 (Pg 10, Reg 12,13,14) D1 C30 (Pg 9, Reg 8,9,10) C62 (Pg 10, Reg 16,17,18) D2 C31 (Pg 9, Reg 12,13,14) C63 (Pg 10, Reg 20,21,22)

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PRB_R18andPRB_R15PRB_R6,PRB_R3,for,24M

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ADC

2.3.5.10.3 FIR Section

Six of the available ADC processing blocks offer FIR filters for signal processing. PRB_R9 and PRB_R12 feature a 20-tap FIR filter while the processing blocks PRB_R3, PRB_R6, PRB_R15 and PRB_R18 feature a 25-tap FIR filter

The coefficients of the FIR filters are 24-bit 2’s complement format and correspond to the ADC coefficient space as listed below. There is no default transfer function for the FIR filter. When the FIR filter gets used all applicable coefficients must be programmed.

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Table 2-10. ADC FIR Filter Coefficients

Filter FIlter Coefficient Left ADC Filter Coefficient Right ADC Channel

Fir0 C7 (Pg 8, Reg 36,37,38) C39 (Pg 9, Reg 44,45,46) Fir1 C8 (Pg 8, Reg 40,41,42) C40 (Pg 9, Reg 48,49,50) Fir2 C9 (Pg 8, Reg 44,45,46) C41 (Pg 9, Reg 52,53,54) Fir3 C10 (Pg 8, Reg 48,49,50) C42 (Pg 9, Reg 56,57,58) Fir4 C11 (Pg 8, Reg 52,53,54) C43 (Pg 9, Reg 60,61,62) Fir5 C12 (Pg 8, Reg 56,57,58) C44 (Pg 9, Reg 64,65,66) Fir6 C13 (Pg 8, Reg 60,61,62) C45 (Pg 9, Reg 68,69,70) Fir7 C14 (Pg 8, Reg 64,65,66) C46 (Pg 9, Reg 72,73,74) Fir8 C15 (Pg 8, Reg 68,69,70) C47 (Pg 9, Reg 76,77,78) Fir9 C16 (Pg 8, Reg 72,73,74) C48 (Pg 9, Reg 80,81,82) Fir10 C17 (Pg 8, Reg 76,77,78) C49 (Pg 9, Reg 84,85,86) Fir11 C18 (Pg 8, Reg 80,81,82) C50 (Pg 9, Reg 88,89,90) Fir12 C19 (Pg 8, Reg 84,85,86) C51 (Pg 9, Reg 92,93,94) Fir13 C20 (Pg 8, Reg 88,89,90) C52 (Pg 9, Reg 96,97,98) Fir14 C21 (Pg 8, Reg 92,93,94) C53 (Pg 9, Reg 100,101,102) Fir15 C22 (Pg 8, Reg 96,97,98) C54 (Pg 9, Reg 104,105,106) Fir16 C23 (Pg 8, Reg 100,101,102) C55 (Pg 9, Reg 108,109,110) Fir17 C24 (Pg 8, Reg 104,105,106) C56 (Pg 9, Reg 112,113,114) Fir18 C25 (Pg 8, Reg 108,109,110) C57 (Pg 9, Reg 116,117,118) Fir19 C26 (Pg 8, Reg 112,113,114) C58 (Pg 9, Reg 120,121,122) Fir20 C27 (Pg 8, Reg 116,117,118) C59 (Pg 9, Reg 124,125,126) Fir21 C28 (Pg 8, Reg 120,121,122) C60 (Pg 10, Reg 8,9,10) Fir22 C29 (Pg 8, Reg 124,125,126) C61 (Pg 10, Reg 12,13,14) Fir23 C30 (Pg 9, Reg 8,9,10) C62 (Pg 10, Reg 16,17,18) Fir24 C31 (Pg 9, Reg 12,13,14) C63 (Pg 10, Reg 20,21,22)

Channel

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–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

FrequencyNormalizedtof

Magnitude – dB

ADCChannelResponseforDecimationFilter A (Redlinecorrespondsto –73dB)

G013

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2.3.5.11 Decimation Filter

The PCM3070 offers 3 different types of decimation filters. The integrated digital decimation filter removes high-frequency content and down samples the audio data from an initial sampling rate of AOSR*Fs to the final output sampling rate of Fs. The decimation filtering is achieved using a higher-order CIC filter followed by linear-phase FIR filters. The decimation filter cannot be chosen by itself, it is implicitly set through the chosen processing block.

The following subsections describe the properties of the available filters A, B and C.

2.3.5.11.1 Decimation Filter A

This filter is intended for use at sampling rates up to 48kHz. When configuring this filter, the oversampling ratio of the ADC can either be 128 or 64. For highest performance the oversampling ratio must be set to

128. Filter A can also be used for 96kHz at an AOSR of 64.

Parameter Condition Value (Typical) Units AOSR = 128

Filter Gain Pass Band 0…0.39 Fs 0.062 dB Filter Gain Stop Band 0.55…64Fs –73 dB Filter Group Delay 17/Fs Sec. Pass Band Ripple, 8 ksps 0…0.39 Fs 0.062 dB Pass Band Ripple, 44.1 ksps 0…0.39 Fs 0.05 dB Pass Band Ripple, 48 ksps 0…0.39 Fs 0.05 dB

AOSR = 64

Filter Gain Pass Band 0…0.39 Fs 0.062 dB Filter Gain Stop Band 0.55…32Fs –73 dB Filter Group Delay 17/Fs Sec. Pass Band Ripple, 8 ksps 0…0.39 Fs 0.062 dB Pass Band Ripple, 44.1 ksps 0…0.39 Fs 0.05 dB Pass Band Ripple, 48 ksps 0…0.39 Fs 0.05 dB Pass Band Ripple, 96 ksps 0…20kHz 0.1 dB

ADC

Table 2-11. ADC Decimation Filter A, Specification

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Figure 2-16. ADC Decimation Filter A, Frequency Response

–10

–20

–30

–40

–50

–60

–70

–80

–90

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

FrequencyNormalizedtof

Magnitude – dB

ADCChannelResponseforDecimationFilterB (Redlinecorrespondsto –44dB)

G014

ADC

2.3.5.11.2 Decimation Filter B

Filter B is intended to support sampling rates up to 96kHz at a oversampling ratio of 64.

Parameter Condition Value (Typical) Units AOSR = 64

Filter Gain Pass Band 0…0.39Fs ±0.077 dB Filter Gain Stop Band 0.60Fs…32Fs –46 dB Filter Group Delay 11/Fs Sec. Pass Band Ripple, 8 ksps 0…0.39Fs 0.076 dB Pass Band Ripple, 44.1 ksps 0…0.39Fs 0.06 dB Pass Band Ripple, 48 ksps 0…0.39Fs 0.06 dB Pass Band Ripple, 96 ksps 0…20kHz 0.11 dB

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Table 2-12. ADC Decimation Filter B, Specifications

Figure 2-17. ADC Decimation Filter B, Frequency Response

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ADCChannelResponseforDecimationFilterC (Redlinecorrespondsto –60dB)

–20

–40

–60

–100

–80

–120

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

FrequencyNormalizedtof

Magnitude – dB

G015

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2.3.5.11.3 Decimation Filter C

Filter type C along with AOSR of 32 is specially designed for 192ksps operation for the ADC. The pass band which extends up to 0.11*Fs ( corresponds to 21kHz), is suited for audio applications.

Parameter Condition Value (Typical) Units

Filter Gain from 0 to 0.11Fs 0…0.11Fs ±0.033 dB Filter Gain from 0.28Fs to 16Fs 0.28Fs…16Fs –60 dB Filter Group Delay 11/Fs Sec. Pass Band Ripple, 8 ksps 0…0.11Fs 0.033 dB Pass Band Ripple, 44.1 ksps 0…0.11Fs 0.033 dB Pass Band Ripple, 48 ksps 0…0.11Fs 0.032 dB Pass Band Ripple, 96 ksps 0…0.11Fs 0.032 dB Pass Band Ripple, 192 ksps 0…20kHz 0.086 dB

ADC

Table 2-13. ADC Decimation Filter C, Specifications

Figure 2-18. ADC Decimation Filter C, Frequency Response

2.3.5.12 ADC Data Interface

The decimation filter and signal processing block in the ADC channel passes 32-bit data words to the audio serial interface once every cycle of Fs,ADC. During each cycle of Fs,ADC, a pair of data words ( for left and right channel ) are passed. The audio serial interface rounds the data to the required word length of the interface before converting to serial data as per the different modes for audio serial interface.

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)tt(OUT_ADC_RIGHT)t(COMP_PHASE_ADC_RIGHT

( )

FS_ADC*AOSR

k*AOSR*)5:6(Delay)0:4(Delay

)tt(OUT_ADC_LEFT)t(COMP_PHASE_ADC_LEFT

FS_ADC*AOSR

)7(Delay

ADC

2.3.6 Special Functions

2.3.6.1 Channel-to-Channel Phase Adjustment

The PCM3070 has a built-in feature to fine-adjust the phase between the stereo ADC record signals. This delay can be controlled in fine amounts in the following fashion.

Delay(7:0) = Page 0/Register 85/D(7:0) Where

where

Where kfis a function of the decimation filter:

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(5)

(6)

and

Where

Decimation Filter Type k

A 0.25 B 0.5 C 1

(7)

(8)

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2.3.6.2 DC Measurement

The PCM3070 supports a highly flexible DC measurement feature using the high resolution oversampling and noise-shaping ADC. This mode can be used when the particular ADC channel is not used for the audio-record function. This mode can be enabled by programming Page 0, Register 102, D(7:6). The converted data is 24-bits, using 2.22 numbering format. The value of the converted data for the left-channel ADC can be read back from Page 0, Register 104-106 and for the right-channel ADC from Page 0, Register 107-109. Before reading back the converted data, Page 0, Register 103, D(6) must be programmed to latch the converted data into the read-back register. After the converted data is read back, Page 0, Register 103, D(6) must be reset to 0 immediately. In DC measurement mode, two measurement methods are supported.

Mode A

In DC-measurement mode A, a variable-length averaging filter is used. The length of the averaging filter D, can be programmed from 1 to 20 by programming Page 0, Register 102, D(4:0). To choose mode A, Page 0, Register 102, D(5) must be programmed to 0.

Mode B

To choose mode B Page 0, Register 102, D(5) must be programmed to 1. In DC-measurement mode B, a first-order IIR filter is used. The coefficients of this filter are determined by D, Page 0, Register 102, D(4:0). The nature of the filter is given in the table below

D:Page 0, Reg 102 , D(4:0) –3 dB BW (kHz) –0.5 dB BW (kHz)

ADC

Table 2-14. DC Measurement Bandwidth Settings

1 688.44 236.5 2 275.97 96.334 3 127.4 44.579 4 61.505 21.532 5 30.248 10.59 6 15.004 5.253 7 7.472 2.616 8 3.729 1.305

9 1.862 652 10 931 326 11 465 163 12 232.6 81.5 13 116.3 40.7 14 58.1 20.3 15 29.1 10.2 16 14.54 5.09 17 7.25 2.54 18 3.63 1.27 19 1.8 0.635 20 0.908 0.3165

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ADC

By programming Page 0, Reg 103, D(5) to ‘1’, the averaging filter is periodically reset after 2^R number of ADC_MOD_CLK, where R is programmed in Page 0, Reg 103, D(4:0). When Page 0, Reg 103, D(5) is set to 1 then the value of D should be less than the value of R. When Page 0, Reg 103, D(5) is programmed as 0 the averaging filter is never reset.

2.3.6.3 Fast Charging AC Capacitors

The value of the coupling capacitor must be so chosen that the high-pass filter formed by the coupling capacitor and the input impedance do not affect the signal content. At power-up, before proper recording can begin, this coupling capacitor must be charged up to the common-mode voltage. To enable quick charging, the PCM3070 has modes to speed up the charging of the coupling capacitor. These are controlled by controlling Page 1, Register 71, D(5:0).

2.3.6.4 Anti Thump

For audio recording, the analog input pins of the PCM3070, must be AC-coupled to isolate the DC-common mode voltage of the driving circuit from the common-mode voltage of the PCM3070.

When the analog inputs are not selected for any routing, the input pins are 3-stated and the voltage on the pins is undefined. When the unselected inputs are selected for any routing, the input pins must charge from the undefined voltage to the input common-mode voltage. This charging signal can cause audible artifacts. In order to avoid such artifacts the PCM3070 also incorporates anti-thump circuitry to allow connection of unused inputs to the common-mode level. This feature is disabled by default, and can be enabled by writing the appropriate value into Page 1, Register 58, D(7:2). The use of this feature in combination with the PTM_R1 setting in Page 0, Register 61 when the ADC channel is powered down causes the additional current consumption of 700μA from AVdd and 125μA from DVdd in the sleep mode.

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+ 100 hidden pages

Texas Instruments PCM3070 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual

PCM3070 Overview

1.1 Description

1.2 Typical Circuit Configuration

2.1 Terminal Descriptions

2.1.1 Digital Pins

2.1.2 Analog Pins

PCM3070 Application

2.1.3 Multifunction Pins

2.1.4 Register Settings for Multifunction Pins

2.2 Analog Audio I/O

2.2.1 Analog Bypass

2.2.2 ADC Bypass Using Mixer Amplifiers

2.2.3 Headphone Output

2.2.4 Stereo Single Ended Configuration

2.2.5 Mono Differential DAC to Mono Differential Headphone Output

2.2.6 Headphone Amplifier Class-D Mode

2.2.7 Line Outputs

2.3 ADC

2.3.1 ADC Signal Routing

2.3.2 ADC Gain Setting

2.3.2.1 Analog Programmable Gain Amplifier (PGA)

2.3.2.2 Digital Volume Control

2.3.2.3 Fine Digital Gain Adjustment

2.3.2.4 AGC

2.3.3 ADC Decimation Filtering and Signal Processing Overview

2.3.4 ADC Processing Blocks

2.3.5 Signal Processing Blocks – Details

2.3.5.1 1storder IIR, AGC, Filter A

2.3.5.2 5 Biquads, 1storder IIR, AGC, Filter A

2.3.5.3 25 Tap FIR, 1storder IIR, AGC, Filter A

2.3.5.4 1storder IIR, AGC, Filter B

2.3.5.5 3 Biquads, 1storder IIR, AGC, Filter B

2.3.5.6 20 Tap FIR, 1storder IIR, AGC, Filter B

2.3.5.7 1storder IIR, AGC, Filter C

2.3.5.8 5 Biquads, 1storder IIR, AGC, Filter C

2.3.5.9 25 Tap FIR, 1storder IIR, AGC, Filter C

2.3.5.10 User Programmable Filters

2.3.5.10.1 1stOrder IIR Section

2.3.5.10.2 Biquad Section

2.3.5.10.3 FIR Section

2.3.5.11 Decimation Filter

2.3.5.11.1 Decimation Filter A

2.3.5.11.2 Decimation Filter B

2.3.5.11.3 Decimation Filter C

2.3.5.12 ADC Data Interface

2.3.6 Special Functions

2.3.6.1 Channel-to-Channel Phase Adjustment

2.3.6.2 DC Measurement

2.3.6.3 Fast Charging AC Capacitors

2.3.6.4 Anti Thump