TEXAS INSTRUMENTS PCM3002, PCM3003 Technical data

Download

    

Lch In Rch In

Analog Front-End

Delta-Sigma

Modulator

Digital

Decimation

Filter

Serial Interface

and

Mode Control

Digital Out

Mode Control System Clock

B0006-01

Digital In

Digital

Interpolation

Filter

Lch Out

Rch Out

Low-Pass Filter

and

Output Buffer

Multilevel

Delta-Sigma

Modulator

* PCM3002 Only

SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004

16/20-BIT SINGLE-ENDED ANALOG INPUT/OUTPUT STEREO AUDIO CODECS

PCM3002 PCM3003

FEATURES

• Monolithic 20-Bit ∆ Σ ADC and DAC

• 16/20-Bit Input/Output Data

• Software Control: PCM3002

• Hardware Control: PCM3003

• Stereo ADC:

– Single-Ended Voltage Input – Antialiasing Filter – 64 × Oversampling – High Performance

• THD+N: –86 dB

• SNR: 90 dB

• Dynamic Range: 90 dB

• Stereo DAC:

– Single-Ended Voltage Output – Analog Low-Pass Filter – 64 × Oversampling – High Performance

• THD+N: –86 dB

• SNR: 94 dB

• Dynamic Range: 94 dB

• Special Features (PCM3002, PCM3003)

– Digital De-Emphasis: 32 kHz, 44.1 kHz,

48 kHz

– Power Down: ADC/DAC Independent

• Special Features (PCM3002)

– Digital Attenuation (256 Steps) – Soft Mute – Digital Loopback – Four Alternative Audio Data Formats

• Sampling Rate: 4 kHz to 48 kHz

• Single 3-V Power Supply

• Small Package: SSOP-24

APPLICATIONS

• DVC Applications

• DSC Applications

• Portable/Mobile Audio Applications

DESCRIPTION

The PCM3002 and PCM3003 are low-cost, single-chip stereo audio codecs (analog-to-digital and digital-to-analog converters) with single-ended analog voltage input and output.

The ADCs and DACs employ delta-sigma modulation with 64-times oversampling. The ADCs include a digital decimation filter, and the DACs include an 8-times oversampling digital interpolation filter. The DACs also include digital attenuation, de-emphasis, infinite zero detection, and soft mute to form a complete subsystem. The PCM3002 and PCM3003 operate with left-justified (ADC) and right-justified (DAC) formats, while the PCM3002 also supports other formats, including the I2S data format.

The PCM3002 and PCM3003 provide a power-down mode that operates on the ADCs and DACs independently.

The PCM3002 and PCM3003 are fabricated using a highly advanced CMOS process, and are available in a 24-pin SSOP package. The PCM3002 and PCM3003 are suitable for a wide variety of cost-sensitive consumer applications where good performance is required.

The PCM3002 programmable functions are controlled by software. The PCM3003 functions, which are controlled by hardware, include de-emphasis, power-down, and audio data format selections.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

System Two, Audio Precision are trademarks of Audio Precision, Inc. All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com

PCM3002 PCM3003

SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ELECTRICAL CHARACTERISTICS

All specifications at TA= 25 ° C, V

PARAMETER CONDITIONS

DIGITAL INPUT/OUTPUT Input Logic

(1) (2) (3)

(2)

(1) (3)

Output Logic

(4)

(5)

CLOCK FREQUENCY

ADC CHARACTERISTICS Resolution 20 Bits DC Accuracy

Dynamic Performance

(1) Pins 7, 8, 17 and 18: RST, ML, MD, and MC for the PCM3002; PDAD, PDDA, DEM1, and DEM0 for PCM3003 (Schmitt-trigger input

with 100-k Ω typical internal pulldown resistor) (2) Pins 9, 10, 11, 15: SYSCLK, LRCIN, BCKIN, DIN (Schmitt-trigger input) (3) Pin 16: 20BIT for PCM3003 (Schmitt-trigger input, 100-k Ω typical internal pulldown resistor) (4) Pin 12: DOUT (5) Pin 16: ZFLG for PCM3002 (open-drain output) (6) See Application Bulletin SBAA033 for information relating to operation at lower sampling frequencies. (7) High-pass filter for offset cancel (8) fIN= 1 kHz, using the System Two™ audio measurement system by Audio Precision™ in rms mode with 20-kHz LPF, 400-Hz HPF used

for performance calculation.

Input logic level VDC

Input logic current µ A

Output logic level I

Sampling frequency 4

System clock frequency 384 f

Gain mismatch, channel- ± 1 ± 3 % of FSR to-channel

Gain error ± 2 ± 5 % of FSR Gain drift ± 20 ppm of FSR/ ° C Bipolar zero error High-pass filter bypassed Bipolar zero drift High-pass filter bypassed

(8)

THD+N dB

Dynamic range A-weighted 86 90 dB Signal-to-noise ratio A-weighted 86 90 dB Channel separation 84 88 dB

= V

= 3 V, fS= 44.1 kHz, SYSCLK = 384 fS, and 16-bit data, unless otherwise noted

PCM3002E/3003E

MIN TYP MAX UNITS

0.7 V

0.3 V

± 1

100

= –1 mA V

OUT

= 1 mA 0.3 VDC

OUT

= 1 mA 0.3

OUT

256 f

S S

512 f

(7) (7)

– 0.3

(6)

44.1 48 kHz

1.024 11.2896 12.288

1.536 16.9344 18.432 MHz

2.048 22.5792 24.576

± 1.7 % of FSR

± 20 ppm of FSR/ ° C

VIN= –0.5 dB –86 –80

VIN= –60 dB –28

www.ti.com

SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004

ELECTRICAL CHARACTERISTICS (continued)

All specifications at TA= 25 ° C, V

PARAMETER CONDITIONS

Digital Filter Performance

Pass band 0.454 f Stop band 0.583 f Pass-band ripple ± 0.05 dB Stop-band attenuation –65 dB Delay time 17.4/f HPF frequency response –3 dB 0.019 f

Analog Input

Voltage range 0.6 V Center voltage 0.5 V Input impedance 30 k Ω Antialiasing filter frequency –3 dB 150 kHz

response

DAC CHARACTERISTICS Resolution 20 Bits DC Accuracy

Gain mismatch, channel- ± 1 ± 3 % of FSR to-channel

Gain error ± 1 ± 5 % of FSR Gain drift ± 20 ppm of FSR/ ° C Bipolar zero error ± 2.5 % of FSR Bipolar zero drift ± 20 ppm of FSR/ ° C

Dynamic Performance

Digital Filter Performance

Analog Output

(9) f

THD+N dB

Dynamic range EIAJ, A-weighted 88 94 dB Signal-to-noise ratio EIAJ, A-weighted 88 94 dB Channel separation 86 91 dB

Pass band 0.445 f Stop band 0.555 f Pass-band ripple ± 0.17 dB Stop-band attenuation –35 dB Delay time 11.1/f

Voltage range 0.6 V Center voltage 0.5 V Load impedance AC coupling 10 k Ω LPF frequency response f = 20 kHz –0.16 dB

= 1 kHz, using the System Two audio measurement system by Audio Precision in rms mode with 20-kHz LPF, 400-Hz HPF used

OUT

for performance calculation.

(9)

= V

= 3 V, fS= 44.1 kHz, SYSCLK = 384 fS, and 16-bit data, unless otherwise noted

PCM3002E/3003E

MIN TYP MAX UNITS

CC CC

= 0 dB (full scale) –86 –80

OUT

= –60 dB –32

OUT

CC CC

PCM3002 PCM3003

Hz Hz

mHz

Vp-p VDC

Hz Hz

Vp-p VDC

www.ti.com

PCM3002 PCM3003

SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004

ELECTRICAL CHARACTERISTICS (continued)

All specifications at TA= 25 ° C, V

PARAMETER CONDITIONS

POWER SUPPLY REQUIREMENTS

VCC, V

TEMPERATURE RANGE

stg

(10) Applies for voltages between 2.4 V and 2.7 V for 0 ° C to 70 ° C and 256 fS/512 fSoperation (384 fSnot available) (11) SYSCLK, BCKIN, and LRCIN are stopped.

Supply voltage

Supply current

Power dissipation

Operation –25 85 ° C Storage –55 125 ° C Thermal resistance 100 ° C/W

= V

= 3 V, fS= 44.1 kHz, SYSCLK = 384 fS, and 16-bit data, unless otherwise noted

PCM3002E/3003E

MIN TYP MAX UNITS

–25 ° C to 85 ° C 2.7 3 3.6 VDC

0 ° C to 70 ° C

Operation, V

Power down, V

Operation, V

Power down

(10)

= V

(11)

3 V

= 3 V 18 24 mA

= V

, V

= 3 V 50 µ A

= V

= 3 V 54 72 mW

= V

2.4 3 3.6 VDC

150 µ W

PACKAGE/ORDERING INFORMATION

PRODUCT QUANTITY

PCM3002E 24-pin SSOP DB PCM3002E

PCM3003E 24-pin SSOP DB PCM3003E

PACKAGE PACKAGE PACKAGE ORDERING TRANSPORT

TYPE CODE MARKING NUMBER MEDIA

PCM3002E Rails 58

PCM3002E/2K Tape and reel 2000

PCM3003E Rails 58

PCM3003E/2K Tape and reel 2000

ABSOLUTE MAXIMUM RATINGS

Supply voltage VDD, VCC1, VCC2 –0.3 V to 6.5 V Supply voltage differences ± 0.1 V GND voltage differences ± 0.1 V Digital input voltage –0.3 V to V Analog input voltage –0.3 V to VCC1, VCC2 + 0.3 V, < 6.5 V Power dissipation 300 mW Input current (any pins except supplies) ± 10 mA Operating temperature –25 ° C to 85 ° C Storage temperature –55 ° C to 125 ° C Lead temperature, soldering 260 ° C, 5 s Package temperature (IR reflow, peak) 235 ° C

+ 0.3 V, < 6.5 V

www.ti.com

1 2 3 4 5 6 7 8 9 10 11 12

24 23 22 21 20 19 18 17 16 15 14 13

VCC1 VCC1

VINR

REF

RST

SYSCLK

LRCIN BCKIN

DOUT

2 AGND1 AGND2 V

COM

OUT

L MC MD ZFLG DIN V

DGND

PCM3002

(TOP VIEW)

P0004-02

1 2 3 4 5 6 7 8 9 10 11 12

24 23 22 21 20 19 18 17 16 15 14 13

VCC1 VCC1

VINR

REF

L PDAD PDDA

SYSCLK

LRCIN

BCKIN

DOUT

2 AGND1 AGND2 V

COM

OUT

L DEM0 DEM1 20BIT DIN V

DGND

PCM3003

(TOP VIEW)

PCM3002 PCM3003

SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range

MIN NOM MAX UNIT

Analog supply voltage, VCC1, VCC2 2.7 3 3.6 V Digital supply voltage, V Analog input voltage, full scale (–0 dB) V Digital input logic family CMOS

Digital input clock frequency

Analog output load resistance 10 k Ω Analog output load capacitance 30 pF Digital output load capacitance 10 pF Operating free-air temperature, T

= 3 V 1.8 Vp-p

System clock 8.192 24.576 MHz Sampling clock 32 48 kHz

2.7 3 3.6 V

–25 85 ° C

NAME PIN I/O DESCRIPTION

AGND1 23 – ADC analog ground AGND2 22 – DAC analog ground

BCKIN 11 I Bit clock input DGND 13 – Digital ground

DIN 15 I Data input

DOUT 12 O Data output

LRCIN 10 I Sample rate clock input (fs)

MC 18 I Bit clock for mode control MD 17 I Serial data for mode control

ML 8 I Strobe pulse for mode control

(1) Schmitt-trigger input (2) With 100-k Ω typical internal pulldown resistor

RST 7 I Reset, active LOW

SYSCLK 9 I System clock input

1 1, 2 – ADC analog power supply

2 24 – DAC analog power supply

COM

PIN ASSIGNMENTS—PCM3002

21 – ADC/DAC common 14 – Digital power supply

(1)

(1) (2)

(1) (2) (1) (2) (1)

www.ti.com

PCM3002 PCM3003

SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004

NAME PIN I/O DESCRIPTION

VINL 6 I ADC analog input, Lch VINR 3 I ADC analog input, Rch

L 19 O DAC analog output, Lch

OUT

R 20 O DAC analog output, Rch

OUT

1 4 – ADC reference 1

REF

2 5 – ADC reference 2

REF

ZFLG 16 O Zero flag output, active LOW

(3) Open-drain output

NAME PIN I/O DESCRIPTION

AGND1 23 – ADC analog ground AGND2 22 – DAC analog ground

BCKIN 11 I Bit clock input

DEM0 18 I De-emphasis control 0 DEM1 17 I De-emphasis control 1

DGND 13 – Digital ground

DIN 15 I Data input

DOUT 12 O Data output

LRCIN 10 I Sample rate clock input (fs)

PDAD 7 I ADC power down, active LOW PDDA 8 I DAC power down, active LOW

SYSCLK 9 I System clock input

1 1, 2 – ADC analog power supply

2 24 – DAC analog power supply

COM

VINL 6 I ADC analog input, Lch VINR 3 I ADC analog input, Rch

L 19 O DAC analog output, Lch

OUT

R 20 O DAC analog output, Rch

OUT

1 4 – ADC reference 1

REF

2 5 – ADC reference 2

REF

20BIT 16 I 20-bit format select

(1) Schmitt-trigger input (2) With 100-k Ω typical internal pulldown resistor

21 – ADC/DAC common 14 – Digital power supply

PIN ASSIGNMENTS—PCM3002 (continued)

(3)

PIN ASSIGNMENTS—PCM3003

(1)

(1) (2) (1) (2)

(1)

(1) (2) (1) (2)

(1)

(1)(2)

www.ti.com

−25 0 25 50 75 100 TA − Free-Air Temperature − °C

Dynamic Range − dB

SNR

SNR − Signal-to-Noise Ratio − dB

G002

Dynamic Range

0.002

0.004

0.006

0.008

0.010

−25 0 25 50 75 100

TA − Free-Air Temperature − °C

THD+N − Total Harm. Dist. + Noise at −0.5 dB − %

−0.5 dB

−60 dB

G001

THD+N − Total Harm. Dist. + Noise at −60 dB − %

2.1 2.4 2.7 3.0 3.3 3.6 3.9 VCC − Supply Voltage − V

Dynamic Range − dB

SNR − Signal-to-Noise Ratio − dB

G004

Dynamic Range

SNR

0.002

0.004

0.006

0.008

0.010

2.1 2.4 2.7 3.0 3.3 3.6 3.9

VCC − Supply Voltage − V

THD+N − Total Harm. Dist. + Noise at −0.5 dB − %

THD+N − Total Harm. Dist. + Noise at −60 dB − %

G003

−60 dB

−0.5 dB

All specifications at TA= 25 ° C, V

ADC SECTION

TEMPERATURE TEMPERATURE

SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004

TYPICAL PERFORMANCE CURVES

= V

= 3 V, fS= 44.1 kHz, f

THD+N DYNAMIC RANGE and SNR

vs vs

SYSCLK

= 384 fS, and f

= 1 kHz, unless otherwise noted

SIGNAL

PCM3002 PCM3003

Figure 1. Figure 2.

THD+N DYNAMIC RANGE and SNR

vs vs

SUPPLY VOLTAGE SUPPLY VOLTAGE

Figure 3. Figure 4.

NOTE: All characteristics at supply voltages from 2.4 V to 2.7 V are measured at SYSCLK = 256 fS.

www.ti.com

Dynamic Range − dB

SNR − Signal-to-Noise Ratio − dB

G006

Dynamic Range

SNR

fS − Sampling Frequency − kHz

4832 44.1

0.002

0.004

0.006

0.008

0.010

fS − Sampling Frequency − kHz

THD+N − Total Harm. Dist. + Noise at −0.5 dB − %

G005

THD+N − Total Harm. Dist. + Noise at −60 dB − %

4832 44.1

−60 dB

−0.5 dB

−25 0 25 50 75 100 TA − Free-Air Temperature − °C

Dynamic Range − dB

SNR

SNR − Signal-to-Noise Ratio − dB

G008

Dynamic Range

0.002

0.004

0.006

0.008

0.010

−25 0 25 50 75 100

TA − Free-Air Temperature − °C

THD+N − Total Harm. Dist. + Noise at FS − %

−60 dB

G007

THD+N − Total Harm. Dist. + Noise at −60 dB − %

PCM3002 PCM3003

SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004

TYPICAL PERFORMANCE CURVES (continued)

All specifications at TA= 25 ° C, V

SAMPLING FREQUENCY SAMPLING FREQUENCY

= V

THD+N DYNAMIC RANGE and SNR

vs vs

= 3 V, fS= 44.1 kHz, f

SYSCLK

= 384 fS, and f

= 1 kHz, unless otherwise noted

SIGNAL

DAC SECTION

Figure 5. Figure 6.

THD+N DYNAMIC RANGE and SNR

vs vs

TEMPERATURE TEMPERATURE

Figure 7. Figure 8.

www.ti.com

2.1 2.4 2.7 3.0 3.3 3.6 3.9 VCC − Supply Voltage − V

Dynamic Range − dB

SNR − Signal-to-Noise Ratio − dB

G010

Dynamic Range

SNR

0.002

0.004

0.006

0.008

0.010

2.1 2.4 2.7 3.0 3.3 3.6 3.9

VCC − Supply Voltage − V

THD+N − Total Harm. Dist. + Noise at FS − %

THD+N − Total Harm. Dist. + Noise at −60 dB − %

G009

−60 dB

Dynamic Range − dB

SNR − Signal-to-Noise Ratio − dB

G012

Dynamic

Range

SNR

fS − Sampling Frequency − kHz

4832 44.1

256 fS, 512 f

384 f

0.002

0.004

0.006

0.008

0.010

fS − Sampling Frequency − kHz

THD+N − Total Harm. Dist. + Noise at FS − %

G011

THD+N − Total Harm. Dist. + Noise at −60 dB − %

4832 44.1

384 f

256 fS, 512 f

384 f

256 fS, 512 f

−60 dB

TYPICAL PERFORMANCE CURVES (continued)

All specifications at TA= 25 ° C, V

SUPPLY VOLTAGE SUPPLY VOLTAGE

SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004

= V

= 3 V, fS= 44.1 kHz, f

SYSCLK

= 384 fS, and f

= 1 kHz, unless otherwise noted

SIGNAL

THD+N DYNAMIC RANGE and SNR

vs vs

PCM3002 PCM3003

Figure 9. Figure 10.

NOTE: All characteristics at supply voltages from 2.4 V to 2.7 V are measured at SYSCLK = 256 fS.

THD+N DYNAMIC RANGE and SNR

vs vs

Figure 11. Figure 12.

SAMPLING FREQUENCY and SYSTEM CLOCK SAMPLING FREQUENCY and SYSTEM CLOCK

www.ti.com

f − Frequency − kHz

−140

−120

−100

−80

−60

−40

−20

0 5 10 15 20 25

Amplitude − dB

G013

f − Frequency − kHz

−140

−120

−100

−80

−60

−40

−20

0 5 10 15 20 25

Amplitude − dB

G015

Signal Level − dB

−96 −84 −72 −60 −48 −36 −24 −12 0

THD+N − Total Harmonic Distortion + Noise − %

G017

0.001

0.1

100

0.01

PCM3002 PCM3003

SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004

TYPICAL PERFORMANCE CURVES (continued)

All specifications at TA= 25 ° C, V

OUTPUT SPECTRUM

ADCs

OUTPUT SPECTRUM (–0.5 dB, N = 8192) OUTPUT SPECTRUM (–60 dB, N = 8192)

= V

= 3 V, fS= 44.1 kHz, f

SYSCLK

= 384 fS, and f

= 1 kHz, unless otherwise noted

SIGNAL

Figure 13. Figure 14.

THD+N

SIGNAL LEVEL

Figure 15.

www.ti.com

f − Frequency − kHz

−140

−120

−100

−80

−60

−40

−20

0 5 10 15 20 25

Amplitude − dB

G014

f − Frequency − kHz

−140

−120

−100

−80

−60

−40

−20

0 5 10 15 20 25

Amplitude − dB

G016

Signal Level − dB

−96 −84 −72 −60 −48 −36 −24 −12 0

THD+N − Total Harmonic Distortion + Noise − %

G018

0.001

0.1

100

0.01

TYPICAL PERFORMANCE CURVES (continued)

All specifications at TA= 25 ° C, V

DACs

OUTPUT SPECTRUM (0 dB, N = 8192) OUTPUT SPECTRUM (–60 dB, N = 8192)

PCM3002 PCM3003

SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004

= V

= 3 V, fS= 44.1 kHz, f

SYSCLK

= 384 fS, and f

= 1 kHz, unless otherwise noted

SIGNAL

Figure 16. Figure 17.

THD+N

SIGNAL LEVEL

Figure 18.

www.ti.com

VCC − Supply Voltage − V

2.1 2.4 2.7 3.0 3.3 3.6 3.9

+ I

− mA

ADC and DAC

ADC

DAC

Power Down and Off

2.5

2.0

1.5

1.0

+ I

: Power Down and Off − mA

G020

0.5

TA − Free-Air Temperature − °C

−50 −25 0 25 50 75 100

+ I

− mA

ADC and DAC

ADC

DAC

Power Down and Off

2.5

2.0

1.5

1.0

+ I

: Power Down and Off − mA

G019

0.5

+ I

− mA

ADC and DAC

fS − Sampling Frequency − kHz

4832 44.1

G021

512 f

256 f

PCM3002 PCM3003

SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004

All specifications at TA= 25 ° C, V

SUPPLY CURRENT

TYPICAL PERFORMANCE CURVES

= V

= 3 V, fS= 44.1 kHz, f

= 384 fS, DIN = BPZ, and V

SYSCLK

= BPZ, unless otherwise

noted

ICC+ I

vs vs

SUPPLY VOLTAGE TEMPERATURE

Figure 19. Figure 20.

All characteristics at supply voltages from 2.4 V to

2.7 V are measured at SYSCLK = 256 fS.

ICC+ I

SAMPLING FREQUENCY

Figure 21.

www.ti.com

DECIMATION FILTER

Normalized Frequency [× fS Hz]

−200

−150

−100

−50

0 8 16 24 32

Amplitude − dB

G022

Normalized Frequency [× fS Hz]

−100

−80

−60

−40

−20

0.0 0.2 0.4 0.6 0.8 1.0

Amplitude − dB

G023

Normalized Frequency [× fS Hz]

−1.0

−0.8

−0.6

−0.4

−0.2

0.0

0.2

0.0 0.1 0.2 0.3 0.4 0.5

Amplitude − dB

G024

Normalized Frequency [× fS Hz]

−10

−9

−8

−7

−6

−5

−4

−3

−2

−1

0.45 0.47 0.49 0.51 0.53 0.55

Amplitude − dB

G025

−4.13 dB at 0.5 f

TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (ADCs)

All specifications at TA= 25 ° C, V

OVERALL CHARACTERISTICS STOP-BAND ATTENUATION CHARACTERISTICS

PCM3002 PCM3003

SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004

= V

= 3 V, fS= 44.1 kHz, and f

= 384 fS, unless otherwise noted

SYSCLK

Figure 22. Figure 23.

PASS-BAND RIPPLE CHARACTERISTICS TRANSITION BAND CHARACTERISTICS

Figure 24. Figure 25.

www.ti.com

Normalized Frequency [× fS/1000 Hz]

−1.0

−0.8

−0.6

−0.4

−0.2

0.0

0.2

0 1 2 3 4

Amplitude − dB

G027

Normalized Frequency [× fS/1000 Hz]

−100

−90

−80

−70

−60

−50

−40

−30

−20

−10

0.0 0.1 0.2 0.3 0.4 0.5

Amplitude − dB

G026

−50

−40

−30

−20

−10

f − Frequency − Hz

Amplitude − dB

1 10 100 10M1k 10k

G028

100k 1M

−1.0

−0.8

−0.6

−0.4

−0.2

0.0

0.2

f − Frequency − Hz

Amplitude − dB

1 10 100 100k1k 10k

G029

PCM3002 PCM3003

SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004

TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (ADCs) (continued)

All specifications at TA= 25 ° C, V

HIGH-PASS FILTER

HIGH-PASS FILTER RESPONSE HIGH-PASS FILTER RESPONSE

= V

= 3 V, fS= 44.1 kHz, and f

SYSCLK

= 384 fS, unless otherwise noted

ANTIALIASING FILTER

Figure 26. Figure 27.

ANTIALIASING FILTER OVERALL ANTIALIASING FILTER PASS-BAND

FREQUENCY RESPONSE FREQUENCY RESPONSE

Figure 28. Figure 29.

www.ti.com

DIGITAL FILTER

−100

−80

−60

−40

−20

Level − dB

f − Frequency − Hz

75k25k 50k

G030

0 175k100k 125k 150k

−1.00

−0.80

−0.60

−0.40

−0.20

0.00

Level − dB

f − Frequency − Hz

G031

0 20k10k 15k

−12

−10

−8

−6

−4

−2

Level − dB

f − Frequency − Hz

G032

0 25k10k 15k 20k

−0.6

−0.4

−0.2

0.0

0.2

0.4

0.6

Error − dB

f − Frequency − Hz

3628

G033

0 145127256 10884

TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (DACs)

All specifications at TA= 25 ° C, V

PCM3002 PCM3003

SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004

= V

= 3 V, fS= 44.1 kHz, and f

= 384 fS, unless otherwise noted

SYSCLK

DE-EMPHASIS FILTER

OVERALL FREQUENCY CHARACTERISTICS PASS-BAND RIPPLE CHARACTERISTICS

(fS= 44.1 kHz) (fS= 44.1 kHz)

Figure 30. Figure 31.

DE-EMPHASIS FREQUENCY RESPONSE (32 kHz) DE-EMPHASIS ERROR (32 kHz)

Figure 32. Figure 33.

www.ti.com

−12

−10

−8

−6

−4

−2

Level − dB

f − Frequency − Hz

G034

0 25k10k 15k 20k

−0.6

−0.4

−0.2

0.0

0.2

0.4

0.6

Error − dB

f − Frequency − Hz

4999.8375

G035

0 19999.359999.675 14999.5125

−12

−10

−8

−6

−4

−2

Level − dB

f − Frequency − Hz

G036

0 25k10k 15k 20k

−0.6

−0.4

−0.2

0.0

0.2

0.4

0.6

Error − dB

f − Frequency − Hz

5442

G037

0 2176810884 16326

PCM3002 PCM3003

SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004

TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (DACs) (continued)

All specifications at TA= 25 ° C, V

DE-EMPHASIS FREQUENCY RESPONSE (44.1 kHz) DE-EMPHASIS ERROR (44.1 kHz)

= V

= 3 V, fS= 44.1 kHz, and f

SYSCLK

= 384 fS, unless otherwise noted

Figure 34. Figure 35.

DE-EMPHASIS FREQUENCY RESPONSE (48 kHz) DE-EMPHASIS ERROR (48 kHz)

Figure 36. Figure 37.

www.ti.com

−100

−80

−60

−40

−20

f − Frequency − Hz

Level − dB

1 10 100 10M1k 10k

G038

100k 1M

−0.15

−0.10

−0.05

0.00

0.05

0.10

0.15

f − Frequency − Hz

Level − dB

1 10 100 100k1k 10k

G039

TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (DACs) (continued)

All specifications at TA= 25 ° C, V

= V

= 3 V, fS= 44.1 kHz, and f

SYSCLK

ANALOG LOW-PASS FILTER

PCM3002 PCM3003

SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004

= 384 fS, unless otherwise noted

INTERNAL ANALOG FILTER FREQUENCY RESPONSE INTERNAL ANALOG FILTER FREQUENCY RESPONSE

(1 Hz–10 MHz) (1 Hz–100 kHz)

Figure 38. Figure 39.

www.ti.com

(1)

20BIT

(2)

Analog

Front-End

Circuit

LRCIN

VINL

Reference

REF

VINR

Delta-Sigma

Modulator

Delta-Sigma

Modulator

Decimation

and

High-Pass Filter

Power Supply

Reset and

Power Down

Serial Data

Interface

DOUT

(1)

/DEM0

(2)

COM

(+)

(−)

(+)

Mode

Control

Interface

Analog

Front-End

Circuit

Decimation

and

High-Pass Filter

ADC

BCKIN

DIN

Analog

Low-Pass

Filter

OUT

Multilevel

Delta-Sigma

Modulator

Interpolation

Filter

8× Oversampling

Analog

Low-Pass

Filter

OUT

Multilevel

Delta-Sigma

Modulator

Interpolation

Filter

8× Oversampling

DAC

(1)

/DEM1

(2)

PDDA

(2)

RST

(1)

/PDAD

(2)

Zero Detect

(1)

Clock

SYSCLK ZFLG

(1)

AGND2 VCC2 AGND1 VCC1 DGND V

B0004-03

PCM3002 PCM3003

SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004

BLOCK DIAGRAM

(1) MC, MD, ML, RST, and ZFLG are for PCM3002 only. (2) DEM0, DEM1, 20BIT, PDAD, and PDDA are for PCM3003 only.

www.ti.com

30 kΩ

VINR

COM

Delta-Sigma

Modulator

(+)

REF

1.0 µF

4.7 µF

−

(−)

−

S0011-03

REF

4.7 µF

PCM3002 PCM3003

SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004

Figure 40. Analog Front-End (Single-Channel)

PCM AUDIO INTERFACE

The four-wire digital audio interface for the PCM3002/3003 comprises LRCIN (pin 10), BCKIN (pin 11), DIN (pin 15), and DOUT (pin 12). The PCM3002 can be used with any of the four input/output data formats (formats 0–3), while the PCM3003 can only be used with selected input/output formats (formats 0–1). For the PCM3002, these formats are selected through program register 3 in the software mode. For the PCM3003, data formats are selected by the 20BIT input (pin 16). Figure 41 , Figure 42 , and Figure 43 illustrate audio data input/output formats and timing.

The PCM3002/3003 can accept 32, 48, or 64 bit clocks (BCKIN) in one clock of LRCIN. Only the 16-bit data format can be selected when 32-bit clocks/LRCIN are applied.

www.ti.com

DAC: 16-Bit, MSB-First, Right-Justified

FORMAT 0: PCM3002/3003

LRCIN Right-ChannelLeft-Channel

BCKIN

DIN

MSB

LSB

MSB

LSB

321 16151416 321 161514

BCKIN

LRCIN

Right-ChannelLeft-Channel

DOUT 1

14 15 16321

MSB LSB MSB LSB

14 15 16321

ADC: 16-Bit, MSB-First, Left-Justified

LRCIN Right-ChannelLeft-Channel

BCKIN

DIN

MSB

LSB

MSB

LSB

18 19 20321 18 19 2032120

DAC: 20-Bit, MSB-First, Right-Justified

FORMAT 1: PCM3002/3003

BCKIN

LRCIN

Right-ChannelLeft-Channel

DOUT 1

18 19 20321

MSB LSB MSB LSB

18 19 20321

ADC: 20-Bit, MSB-First, Left-Justified

T0016-04

PCM3002 PCM3003

SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004

Figure 41. Audio Data Input/Output Format

www.ti.com

DAC: 20-Bit, MSB-First, Left-Justified

FORMAT 2: PCM3002 Only

BCKIN

LRCIN

Right-ChannelLeft-Channel

DIN 1

18 19 20321

MSB LSB MSB LSB

18 19 20321

ADC: 20-Bit, MSB-First, Left-Justified

BCKIN

LRCIN

Right-ChannelLeft-Channel

DOUT 1

18 19 20321

MSB LSB MSB LSB

18 19 20321

LRCIN

Right-ChannelLeft-Channel

BCKIN

DIN

MSB LSB MSB LSB

18 19 20321 18 19 20321

DAC: 20-Bit, MSB-First, I2S

FORMAT 3: PCM3002 Only

LRCIN

Right-ChannelLeft-Channel

BCKIN

DOUT

MSB LSB MSB LSB

18 19 20321 18 19 20321

ADC: 20-Bit, MSB-First, I2S

T0016-05

PCM3002 PCM3003

SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004

Figure 42. Audio Data Input/Output Format (PCM3002)

www.ti.com

BCKIN

LRCIN

DIN

(BCH)

(BCL)

(LRP)

(LB)

(BCY)

0.5 V

(BL)

DOUT

(BDO)

(LDO)

0.5 V

(DIS)

(DIH)

0.5 V

T0021−01

PCM3002 PCM3003

SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004

BCKIN pulse cycle time t BCKIN pulse duration, HIGH t BCKIN pulse duration, LOW t BCKIN rising edge to LRCIN edge t LRCIN edge to BCKIN rising edge t LRCIN pulse duration t DIN setup time t DIN hold time t DOUT delay time to BCKIN falling edge t DOUT delay time to LRCIN edge t Rising time of all signals t Falling time of all signals t

(BCY) (BCH) (BCL)

(BL) (LB)

(LRP)

(DIS)

(DIH) (BDO) (LDO)

(RISE) (FALL)

300 ns (min) 120 ns (min) 120 ns (min)

40 ns (min) 40 ns (min) t

(min)

(BCY)

40 ns (min)

40 ns (min) 40 ns (max) 40 ns (max) 20 ns (max) 20 ns (max)

Figure 43. Audio Data Input/Output Timing

SYSTEM CLOCK

The system clock for the PCM3002/3003 must be either 256 fS, 384 fS, or 512 fS, where fSis the audio sampling frequency. The system clock should be provided at the SYSCLK input (pin 9).

The PCM3002/3003 also has a system-clock detection circuit that automatically senses if the system clock is operating at 256 fS, 384 fS, or 512 fS. When a 384-f automatically. The 256-f

Table 1 lists the relationship of typical sampling frequencies and system clock frequencies; Figure 44 illustrates the system clock timing.

clock is used to operate the digital filters and the delta-sigma modulators.

Table 1. System Clock Frequencies

SAMPLING RATE FREQUENCY (kHz) SYSTEM CLOCK FREQUENCY (MHz)

32 8.1920 12.2880 16.3840

44.1 11.2896 16.9344 22.5792 48 12.2880 18.4320 24.5760

256 f

or 512-f

system clock is used, the clock is divided to 256 f

384 f

512 f

www.ti.com

(SCKH)

SYSCLK

0.3 V

0.7 V

(SCKL)

1/256 fS, 1/384 fS,

or 1/512 f

T0005-05

1024 System Clock Periods

Reset Reset Removal

2.4 V

2.2 V

2.0 V

Internal Reset

System Clock

T0014-03

3 Clocks Minimum

Figure 44. System Clock Timing

PCM3002 PCM3003

SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004

System clock pulse duration, HIGH t System clock pulse duration, LOW t

(SCKH) (SCKL)

12 ns (min) 12 ns (min)

POWER-ON RESET

Both the PCM3002 and PCM3003 have internal power-on reset circuitry. Power-on reset occurs when the system clock (SYSCLK) is active and V three complete cycles prior to V

> 2.2 V to ensure proper reset operation. The initialization sequence requires

> 2.2 V. For the PCM3003, the SYSCLK must complete a minimum of

1024 SYSCLK cycles for completion, as shown in Figure 45 . Figure 46 shows the state of the DAC and ADC outputs during and after the reset sequence.

Figure 45. Internal Power-On Reset Timing

www.ti.com

T0019-02

Reset Ready/Operation

Internal Reset

or Power Down

DAC V

OUT

(DACDLY1)

(16384/fS)

Reset Removal or Power Down Off

Power Down

ADC DOUT

Zero Data Normal Data

(1)

COM

(0.5 VCC)

(ADCDLY1)

(18432/fS)

Zero Data

GND

(RST)

Reset Removal

1024 System Clock Periods

RST

PDAD and PDDA

Internal Reset

System Clock

(RST)

= 40 ns (min)

Reset

T0015-02

RST Pulse Duration

PCM3002 PCM3003

SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004

(1) The HPF transient response (exponentially attenuated signal from ± 0.2% dc of FSR with 200-ms time constant)

appears initially.

Figure 46. DAC Output and ADC Output for Reset and Power Down

EXTERNAL RESET

The PCM3002 includes a reset input, RST (pin 7), while the PCM3003 uses both PDAD (pin 7) and PDDA (pin 8) for external reset control. As shown in Figure 47 , the external reset signal must drive RST or PDAD and PDDA low for a minimum of 40 nanoseconds while SYSCLK is active in order to initiate the reset sequence. Initialization starts on the rising edge of RST or PDAD and PDDA, and requires 1024 SYSCLK cycles for completion. Figure 46 shows the state of the DAC and ADC outputs during and after the reset sequence.

SYNCHRONIZATION WITH THE DIGITAL AUDIO SYSTEM

The PCM3002/3003 operates with LRCIN synchronized to the system clock. The PCM3002/3003 does not require any specific phase relationship between LRCIN and the system clock, but there must be synchronization of LRCIN and the system clock. If the synchronization between the system clock and LRCIN changes more than 6 bit clocks (BCKIN) during one sample (LRCIN) period because of phase jitter on LRCIN, internal operation of the DAC stops within 1/f resynchronized to LRCIN followed by t and the digital output codes are set to bipolar zero until resynchronization occurs followed by t time. If LRCIN is synchronized within 5 or fewer bit clocks to the system clock, operation is normal. Figure 48 illustrates the effects on the output when synchronization is lost. Before the outputs are forced to bipolar zero (<1/f data and undefined states, the output has discontinuities, which cause output noise.

Figure 47. External Forced-Reset Timing

, and the analog output is forced to bipolar zero (0.5 V

seconds), the outputs are not defined and some noise may occur. During the transitions between normal

(DACDLY2)

delay time. Internal operation of the ADC also stops within 1/f

) until the system clock is

(ADCDLY2)

delay

www.ti.com

Within 1/f

(DACDLY2)

(32/fS)

Normal Data

COM

(0.5 VCC)

Undefined

Data

Normal Data

SynchronousAsynchronousSynchronous

Resynchronization

Synchronization Lost

DAC V

OUT

State of Synchronization

T0020-03

Normal Data

(1)

Zero DataNormal Data

ADC DOUT

(ADCDLY2)

(32/fS)

Undefined

Data

SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004

(1) The HPF transient response (exponentially attenuated signal from ± 0.2% dc of FSR with 200-ms time constant)

appears initially.

Figure 48. DAC Output and ADC Output for Loss of Synchronization

PCM3002 PCM3003

ZERO FLAG OUTPUT: PCM3002 ONLY

Pin 16 is an open-drain output, used as the infinite zero detection flag on the PCM3002 only. When input data is continuously zero for 65,536 BCKIN cycles, ZFLG is LOW; otherwise, ZFLG is in a high-impedance state.

OPERATIONAL CONTROL

The PCM3002 can be controlled in a software mode with a three-wire serial interface on MC (pin 18), MD (pin 17), and ML (pin 8). Table 2 indicates selectable functions, and Figure 49 and Figure 50 illustrate the control data input format and timing. The PCM3003 only allows for control of 16/20-bit data format, digital de-emphasis, and power-down control by hardware pins.

Audio data format ADC/DAC Four selectable formats Two selectable formats LRCIN polarity ADC/DAC O X Loopback control ADC/DAC O X Left-channel attenuation DAC O X Right-channel attenuation DAC O X Attenuation control DAC O X Infinite zero detection and mute DAC O X DAC output control DAC O X Soft mute control DAC O X De-emphasis (OFF, 32 kHz, 44.1 kHz, 48 kHz) DAC O O ADC power-down control ADC O O DAC power-down control DAC O O High-pass filter operation ADC O X

Table 2. Selectable Functions (O = User Selectable; X = Not Available)

FUNCTION ADC/DAC PCM3002 PCM3003

www.ti.com

B15

B9B10B11B12B13B14 B0

B1B2B3B4B5B6

T0023-01

(MCH)

LSB

(MCL)

(MHH)

(MCY)

(MDH)

(MDS)

(MLS)

(MLL)

(MLH)

T0024-02

0.5 V

PCM3002 PCM3003

SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004

Figure 49. Control Data Input Format

MC pulse cycle time t MC pulse duration, LOW t MC pulse duration, HIGH t MD setup time t MD hold time t ML low-level time t ML high-level time t ML setup time ML hold time

(3)

(2)

(MCY) (MCL) (MCH) (MDS) (MDH)

(MLL)

(MHH)

(MLS)

(MLH)

SYSCLK: 1/256 fSor 1/384 fSor 1/512 f

100 ns (min)

40 ns (min) 40 ns (min) 40 ns (min)

40 ns (min) 40 ns + 1 SYSCLK 40 ns + 1 SYSCLK

(1)

(min)

(1)

(min) 40 ns (min) 40 ns (min)

(1) SYSCLK: System clock cycle (2) MC rising edge of LSB to ML rising edge (3) ML rising edge to the next MC rising edge

Figure 50. Control Data Input Timing

www.ti.com

PCM3002 PCM3003

SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004

MAPPING OF PROGRAM REGISTERS

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

REGISTER 0 res res res res res A1 A0 LDL AL7 AL6 AL5 AL4 AL3 AL2 AL1 AL0 REGISTER 1 res res res res res A1 A0 LDR AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0 REGISTER 2 res res res res res A1 A0 PDAD BYPS PDDA ATC IZD OUT DEM1 DEM0 MUT REGISTER 3 res res res res res A1 A0 res res res LOP res FMT1 FMT0 LRP res

NOTE: res indicates a reserved bit that should be set to 0.

SOFTWARE CONTROL (PCM3002)

The PCM3002 special functions are controlled using four program registers which are each 16 bits long. There are four distinct registers, with bits 9 and 10 determining which register is in use. Table 3 describes the functions of the four registers.

Table 3. Functions of the Registers

10–9 A[1:0] Register address 00

8 LDL DAC attenuation data load control for

7–0 AL[7:0] DAC attenuation data for Lch

10–9 A[1:0] Register address 01

8 LDR DAC attenuation data load control for

7–0 AR[7:0] DAC attenuation data for Rch

10–9 A[1:0] Register address 10

8 PDAD ADC power-down control 7 BYPS ADC high-pass filter bypass control 6 PDDA DAC power-down control 5 ATC DAC attenuation data mode control 4 IZD DAC infinite zero detection and mute

3 OUT DAC output enable control

2–1 DEM[1:0] DAC de-emphasis control

0 MUT DAC Lch and Rch soft mute control

10–9 A[1:0] Register address 11

8–6 res Reserved, should be set to 0

5 LOP ADC/DAC digital loopback control 4 res Reserved, should be set to 0

3–2 FMT[1:0] ADC/DAC audio data format selection

1 LRP ADC/DAC polarity of LR-clock selection 0 res Reserved, should be set to 0

Lch

Rch

control

PROGRAM REGISTER 0

res: Bits 15–11: Reserved

These bits are reserved and should be set to 0.

www.ti.com

PCM3002 PCM3003

SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004

A[1:0] Bits 10, 9: Register address

These bits define the address for register 0:

A1 A0 REGISTER

0 0 Register 0

LDL Bit 8: DAC attenuation data load control for left channel

This bit is used to set analog outputs of the left and right channels simultaneously. The output level is controlled by AL[7:0] attenuation data when this bit is set to 1. When set to 0, the new attenuation data is ignored, and the output level remains at the previous attenuation level. The LDR bit in register 1 has the equivalent function as LDL. When either LDL or LDR is set to 1, the output levels of the left and right channels are controlled simultaneously.

AL (7:0) Bits 7–0: DAC attenuation data for left channel

AL7 and AL0 are the MSB and LSB, respectively. The attenuation level (ATT) is given by: ATT = 20 × log

AL[7:0] ATTENUATION LEVEL

00h – ∞ dB (mute) 01h –48.16 dB

: : FEh –0.07 dB FFh 0 dB (default)

(AL[7:0]/256) [dB], except AL[7:0] = FFh

PROGRAM REGISTER 1

res: Bits 15–11: Reserved

These bits are reserved and should be set to 0.

A[1:0] Bits 10, 9: Register address

These bits define the address for register 1:

A1 A0 REGISTER

0 1 Register 1

LDR Bit 8: DAC attenuation data load control for right channel

This bit is used to set analog outputs of the left and right channels simultaneously. The output level is controlled by AR[7:0] attenuation data when this bit is set to 1. When set to 0, the new attenuation data is ignored, and the output level remains at the previous attenuation level. The LDL bit in register 0 has the equivalent function as LDR. When either LDL or LDR is set to 1, the output levels of the left and right channels are controlled simultaneously.

AR[7:0] Bits 7–0: DAC attenuation data for right channel

AR7 and AR0 are the MSB and LSB, respectively. ATT = 20 × log

AR[7:0] ATTENUATION LEVEL

00h – ∞ dB (mute) 01h –48.16 dB

: : FEh –0.07 dB FFh 0 dB (default)

(AR[7:0]/256) [dB], except AR[7:0] = FFh

PROGRAM REGISTER 2

res: Bits 15–11: Reserved

These bits are reserved and should be set to 0.

www.ti.com

A[1:0] Bits 10, 9: Register address

These bits define the address for register 2:

A1 A0 REGISTER

1 0 Register 2

PDAD: Bit 8: ADC power-down control

This bit places the ADC section in the lowest power-consumption mode. The ADC operation is stopped by cutting the supply current to the ADC section, and DOUT is fixed to zero during ADC power-down mode enable. Figure 46 illustrates the ADC DOUT response for ADC power-down ON/OFF. This does not affect the DAC operation.

PDAD DAC POWER-DOWN STATUS

0 Power-down mode disabled (default) 1 Power-down mode enabled

BYPS: Bit 7: ADC high-pass filter bypass control

This bit enables or disables the high-pass filter for the ADC.

BYPS FILTER BYPASS STATUS

0 High-pass filter enabled (default) 1 High-pass filter disabled (bypassed)

PCM3002 PCM3003

SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004

PDDA: Bit 6: DAC power-down control

This bit places the DAC section in the lowest power-consumption mode. The DAC operation is stopped by cutting the supply current to the DAC section, and VOUT is fixed to GND during DAC power-down mode enable. Figure 46 illustrates the DAC VOUT response for DAC power-down ON/OFF. This does not affect the ADC operation.

PDDA ADC POWER-DOWN STATUS

0 Power-down mode disabled (default) 1 Power-down mode enabled

ATC: Bit 5: DAC attenuation data mode control

When set to 1, the register 0 attenuation data can be used for both DAC channels. In this case, the register 1 attenuation data is ignored.

ATC ATTENUATION CONTROL

0 Individual channel attenuation data control (default) 1 Common channel attenuation data control

IZD: Bit 4: DAC infinite zero detection and mute control

This bit enables the infinite zero detection circuit in the PCM3002. When enabled, this circuit disconnects the analog output amplifier from the delta-sigma DAC when the input is continuously zero for 65,536 consecutive cycles of BCKIN.

IZD INFINITE ZERO DETECT STATUS

0 Infinite zero detection and mute control disabled (default) 1 Infinite zero detection and mute control enabled

OUT: Bit 3: DAC output enable control

When set to 1, the outputs are forced to V PCM3002 hold the present data. Therefore, when set to 0, the outputs return to the previous programmed state.

OUT DAC OUTPUT STATUS

0 DAC outputs enabled (default normal operation) 1 DAC outputs disabled (forced to BPZ)

/2 (bipolar zero). In this case, all registers in the

www.ti.com

PCM3002 PCM3003

SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004

DEM[1:0]: Bits 2, 1: DAC de-emphasis control

These bits select the de-emphasis mode as shown below:

DEM1 DEM0 DE-EMPHASIS STATUS

0 0 De-emphasis 44. 1 kHz ON 0 1 De-emphasis OFF (default) 1 0 De-emphasis 48 kHz ON 1 1 De-emphasis 32 kHz ON

MUT: Bit 0: DAC soft mute control

When set to 1, both left- and right-channel DAC outputs are muted at the same time. This muting is done by attenuating the data in the digital filter, so there is no audible click noise when soft mute is turned on.

MUT MUTE STATUS

0 Mute disabled (default) 1 Mute enabled

PROGRAM REGISTER 3

res: Bits 15–11: Reserved

These bits are reserved and should be set to 0.

A[1:0] Bits 10, 9: Register address

These bits define the address for register 3:

A1 A0 REGISTER

1 1 Register 3

res: Bits 8–6: Reserved

These bits are reserved and should be set to 0.

LOP: Bit 5: ADC to DAC loopback control

When this bit is set to 1, the ADC audio data is sent directly to the DAC. The data format defaults to I2S; DOUT is still available in loopback mode.

LOP LOOPBACK STATUS

0 Loopback disabled (default) 1 Loopback enabled

res: Bit 4: Reserved

This bit is reserved and should be set to 0.

FMT[1:0] Bits 3–2: Audio data format select

These bits determine the input and output audio data formats.

FMT1 FMT0 DAC DATA FORMAT ADC DATA FORMAT NAME

0 0 16-bit, MSB-first, right-justified 16-bit, MSB-first, left-justified Format 0 (default) 0 1 20-bit, MSB-first, right-justified 20-bit, MSB-first, left-justified Format 1 1 0 20-bit, MSB-first, left-justified 20-bit, MSB-first, left-justified Format 2 1 1 20-bit, MSB-first, I2S 20-bit, MSB-first, I2S Format 3

LRP: Bit 1: ADC to DAC LRCIN polarity select

Polarity of LRCIN applies only to formats 0 through 2.

LRP LEFT/RIGHT POLARITY

0 Left channel is H, right channel is L (default). 1 Left channel is L, right channel is H.

www.ti.com

SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004

res: Bit 0: Reserved

This bit is reserved and should be set to 0.

PCM3003 DATA FORMAT CONTROL

The PCM3003 has hardware functional control using PDAD (pin 7) and PDDA (pin 8) for power-down control; DEM0 (pin 18) and DEM1 (pin 17) for de-emphasis; and 20BIT (pin 16) for 16/20-bit format selection.

Power-Down Control (Pin 7 and Pin 8)

Both the ADC and DAC power-down control pins place the ADC or DAC section in the lowest power-consumption mode. The ADC/DAC operation is stopped by cutting the supply current to the ADC/DAC section. DOUT is fixed to zero during ADC power-down mode enable and V power-down mode enable. Figure 46 illustrates the ADC and DAC output response for power-down ON/OFF.

PDAD PDDA POWER DOWN

Low Low Reset (ADC/DAC power down enabled)

Low High ADC power-down/DAC operates High Low ADC operates/DAC power down High High ADC and DAC normal operation

De-Emphasis Control (Pin 17 and Pin 18)

DEM0 (pin 18) and DEM1 (pin 17) are used as de-emphasis control pins.

DEM1 DEMO DE-EMPHASIS

Low Low De-emphasis enabled for 44.1 kHz

Low High De-emphasis disabled High Low De-emphasis enabled for 48 kHz High High De-emphasis enabled for 32 kHz

is fixed to GND during DAC

OUT

PCM3002 PCM3003

20BIT Audio Data Selection (Pin 16)

20BIT FORMAT

Low ADC: 16-bit MSB-first, left-justified

High ADC: 20-bit MSB-first, left-justified

DAC: 16-bit MSB-first, right-justified

DAC: 20-bit MSB-first, right-justified

www.ti.com

PCM3002 PCM3003

SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004

APPLICATION AND LAYOUT CONSIDERATIONS

POWER-SUPPLY BYPASSING

The digital and analog power supply lines to PCM3002/3003 should be bypassed to the corresponding ground pins with both 0.1- µ F ceramic and 10- µ F tantalum capacitors as close to the device pins as possible. Although the PCM3002/3003 has three power-supply lines to optimize dynamic performance, the use of one common power supply is generally recommended to avoid unexpected latch-up or pop noise due to power-supply sequencing problems. If separate power supplies are used, back-to-back diodes are recommended to avoid latch-up problems.

GROUNDING

In order to optimize the dynamic performance of the PCM3002/3003, the analog and digital grounds are not connected internally. The PCM3002/3003 performance is optimized with a single ground plane for all returns. It is recommended to tie all PCM3002/3003 ground pins to the analog ground plane using low-impedance connections. The PCM3002/3003 should reside entirely over this plane to avoid coupling high-frequency digital switching noise into the analog ground plane.

VOLTAGE INPUT

A tantalum or aluminum electrolytic capacitor, between 1 µ F and 10 µ F, is recommended as an ac-coupling capacitor at the inputs. Combined with the 30-k Ω characteristic input impedance, a 1- µ F coupling capacitor establishes a 5.3-Hz cutoff frequency for blocking dc. The input voltage range can be increased by adding a series resistor on the analog input line. This series resistor, when combined with the 30-k Ω input impedance, creates a voltage divider and enables larger input ranges.

INPUTS

REF

A 4.7- µ F to 10- µ F tantalum capacitor is recommended between V

1, V

REF

2, and AGND1 to ensure low source

REF

impedance for the ADC references. These capacitors should be located as close as possible to the reference pins to reduce dynamic errors on the ADC reference.

INPUT

COM

A 4.7- µ F to 10- µ F tantalum capacitor is recommended between V

and AGND1 to ensure low source

COM

impedance of the ADC and DAC common voltage. This capacitor should be located as close as possible to the V

pin to reduce dynamic errors on the dc common-mode voltage.

COM

SYSTEM CLOCK

The quality of the system clock can influence dynamic performance of both the ADC and DAC in the PCM3002/3003. The duty cycle and jitter at the system-clock input pin should be carefully managed. When power is supplied to the part, the system clock, bit clock (BCKIN), and word clock (LCRIN) also must be supplied simultaneously. Failure to supply the audio clocks results in a power-dissipation increase of up to three times normal dissipation and can degrade long-term reliability if the maximum power-dissipation limit is exceeded.

RESET CONTROL

If capacitors larger than 22 µ F are used on V PDAD = low and PDDA = low for the PCM3003) is required after the V

and V

REF

, external reset control ( RST = low for the PCM3002,

COM

, V

REF

transient response is settled.

COM

EXTERNAL MUTE CONTROL

For power-down ON/OFF control without click noise, which is generated by a DC level change on the DAC output, use of the external mute control is recommended. The control sequence, which is external mute ON, codec power-down ON, SYSCLK stop and resume if necessary, codec power-down OFF, and external mute OFF is recommended.

TYPICAL CONNECTION DIAGRAM

A typical connection diagram for the PCM3002/3003 is shown in Figure 51 .

www.ti.com

REF

20 19 18 17 16 15 14 13

5 6 7 8 9

VINL RST/PDAD ML/PDDA SYSCLK LRCIN BCKIN DOUT

OUT

DGND

OUT

L MC/DEM0 MD/DEM1

ZFLG/20BIT

DIN

Rch In

Audio

Interface

VCC1

24 23 22 21

1 2 3 4

VCC1 VINR V

REF

VCC2 AGND1 AGND2

COM

+ +

0.1 µF

and 10 µF

(1)

(6)

/DEM0

(7)

ZFLG

(6)

/20BIT

(7)

Control Interface

PCM3002/3003

1 µF

(3)

4.7 µF

(2)

4.7 µF

(2)

Lch In

1 µF

(3)

SYSCLK L/R CLK BIT CLK

DATA OUT

DATA IN

S0014-01

+3 V Analog V

0.1 µF

and 10 µF

(1)

4.7 µF

(2)

4.7 µF

(4)

Rch Out

(5)

Lch Out

(5)

(6)

/DEM1

(7)

0.1 µF

and 10 µF

(1)

(6)

/PDDA

(7)

RST

(6)

/PDAD

(7)

4.7 µF

(4)

10 kΩ

PCM3002 PCM3003

SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004

(1) 0.1- µ F ceramic and 10- µ F tantalum, typical, depending on power supply quality and pattern layout (2) 4.7- µ F, typical, gives settling time with 30-ms (4.7 µ F × 6.4 k Ω ) time constant in the power ON and power-down OFF

periods.

(3) 1- µ F, typical, gives 5.3-Hz cutoff frequency for the input HPF in normal operation and gives settling time with 30-ms

(1 µ F × 30 k Ω ) time constant in the power ON and power-down OFF periods.

(4) 4.7- µ F, typical, gives 3.4-Hz cutoff frequency for the output HPF in normal operation and gives settling time with

47-ms (4.7 µ F × 10 k Ω ) time constant in the power ON and power-down OFF periods. (5) Post low-pass filter with RIN> 10 k Ω , depending on system performance requirements (6) MC, MD, ML, ZFLG, RST, and 10-k Ω pullup resistor are for the PCM3002. (7) DEM0, DEM1, 20BIT, PDAD, PDDA are for the PCM3003.

Figure 51. Typical Connection Diagram for PCM3002/3003

www.ti.com

SW-CAP

Integrator

Analog In X(z) +

−

SW-CAP

Integrator

SW-CAP

Integrator

−

SW-CAP

Integrator

SW-CAP

Integrator

Digital Out Y(z)

Comparator

Qn(z)

H(z)

1-Bit DAC

STF(z) = H(z) / [1 + H(z)] NTF(z) = 1 / [1 + H(z)]

Y(z) = STF(z) * X(z) + NTF(z) * Qn(z) Signal Transfer Function Noise Transfer Function

B0005-01

PCM3002 PCM3003

SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004

THEORY OF OPERATION

ADC SECTION

The PCM3002/3003 ADC consists of two reference circuits, a stereo single-to-differential converter, a fully differential fifth-order delta-sigma modulator, a decimation filter (including digital high pass), and a serial interface circuit. The block diagram in this data sheet illustrates the architecture of the ADC section, Figure 40 shows the single-to-differential converter, and Figure 52 illustrates the architecture of the fifth-order delta-sigma modulator and transfer functions.

An internal reference circuit with three external capacitors provides all reference voltages required by the ADC, which defines the full-scale range for the converter. The internal single-to-differential voltage converter saves the space and extra parts needed for the external circuitry required by many delta-sigma converters. The internal full-differential signal processing architecture provides a wide dynamic range and excellent power supply rejection performance. The input signal is sampled at a 64 × oversampling rate, eliminating the need for a sample-and-hold circuit, and simplifying antialias filtering requirements. The fifth-order delta-sigma noise shaper consists of five integrators which use a switched-capacitor topology, a comparator, and a feedback loop consisting of a one-bit DAC. The delta-sigma modulator shapes the quantization noise, shifting it out of the audio band in the frequency domain. The high order of the modulator enables it to randomize the modulator outputs, reducing idle tone levels.

The 64-f filter, which also acts as a low-pass filter to remove the shaped quantization noise. The dc components are removed by a high-pass filter function contained within the decimation filter.

, one-bit data stream from the modulator is converted to 1-f

, 16/20-bit data words by the decimation

DAC SECTION

The delta-sigma DAC section of the PCM3002/3003 is based on a 5-level amplitude quantizer and a third-order noise shaper. This section converts the oversampled input data to a 5-level delta-sigma format. A block diagram of the 5-level delta-sigma modulator is shown in Figure 53 . This 5-level delta-sigma modulator has the advantage of improved stability and reduced clock-jitter sensitivity over the typical one-bit (2-level) delta-sigma modulator. The combined oversampling rate of the delta-sigma modulator and the internal 8 × interpolation filter is 64 fSfor a 256-f shown in Figure 54 .

system clock. The theoretical quantization noise performance of the 5-level delta-sigma modulator is

Figure 52. Simplified Fifth-Order Delta-Sigma Modulator

www.ti.com

−

−1

+ +

−

−1

8 f

21-Bit

Out

64 f

−1

B0008-01

5-Level Quantizer

f − Frequency − kHz

−150

−140

−130

−120

−110

−100

−90

−80

−70

−60

−50

−40

−30

−20

−10

0 5 10 15 20 25 30

Gain − dB

G040

THEORY OF OPERATION (continued)

PCM3002 PCM3003

SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004

Figure 53. Five-Level Delta-Sigma Modulator Block Diagram

Figure 54. Quantization Noise Spectrum

PACKAGE OPTION ADDENDUM

www.ti.com

12-Jan-2007

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package Drawing

Pins Package

Qty

Eco Plan

PCM3002E ACTIVE SSOP DB 24 58 Green (RoHS &

no Sb/Br)

PCM3002E/2K ACTIVE SSOP DB 24 2000 Green (RoHS &

no Sb/Br)

PCM3002E/2KG4 ACTIVE SSOP DB 24 2000 Green (RoHS &

no Sb/Br)

PCM3002EG ACTIVE SSOP DB 24 58 Pb-Free

PCM3002EG/2K ACTIVE SSOP DB 24 2000 Pb-Free

PCM3002EG/2KE6 ACTIVE SSOP DB 24 2000 Pb-Free

PCM3002EG4 ACTIVE SSOP DB 24 58 Green (RoHS &

no Sb/Br)

PCM3002EGE6 ACTIVE SSOP DB 24 58 Pb-Free

PCM3003E ACTIVE SSOP DB 24 58 Green (RoHS &

no Sb/Br)

PCM3003E/2K ACTIVE SSOP DB 24 2000 Green (RoHS &

no Sb/Br)

PCM3003E/2KG4 ACTIVE SSOP DB 24 2000 Green (RoHS &

no Sb/Br)

PCM3003EG4 ACTIVE SSOP DB 24 58 Green (RoHS &

no Sb/Br)

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

(RoHS)

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-1-260C-UNLIM

CU SNBI Level-2-260C-1 YEAR

CU NIPDAU Level-1-260C-UNLIM

CU SNBI Level-2-260C-1 YEAR

CU NIPDAU Level-1-260C-UNLIM

(3)

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

12-Jan-2007

Addendum-Page 2

MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,65

2,00 MAX

0,38 0,22

0,05 MIN

0,15

5,60 5,00

Seating Plane

8,20 7,40

0,10

0,25 0,09

0°–ā8°

Gage Plane

0,25

0,95 0,55

PINS **

DIM

A MAX

A MIN

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150

6,50

5,905,90

2016

7,50

6,90

8,50

10,50

9,907,90

10,50

9,90

12,90

12,30

4040065 /E 12/01

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety-critical applications.

TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.

TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements.

Following are URLs where you can obtain information on other Texas Instruments products and application solutions:

Products Applications

Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Clocks and Timers www.ti.com/clocks Digital Control www.ti.com/digitalcontrol Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security RFID www.ti-rfid.com Telephony www.ti.com/telephony RF/IF and ZigBee® Solutions www.ti.com/lprf Video & Imaging www.ti.com/video

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

Wireless www.ti.com/wireless

TEXAS INSTRUMENTS PCM3002, PCM3003 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

DESCRIPTION

ELECTRICAL CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS

RECOMMENDED OPERATING CONDITIONS

ADC SECTION

TYPICAL PERFORMANCE CURVES

DAC SECTION

OUTPUT SPECTRUM

ADCs

DACs

SUPPLY CURRENT

TYPICAL PERFORMANCE CURVES

DECIMATION FILTER

TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (ADCs)

HIGH-PASS FILTER

ANTIALIASING FILTER

DIGITAL FILTER

TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (DACs)

DE-EMPHASIS FILTER

ANALOG LOW-PASS FILTER

PCM AUDIO INTERFACE

SYSTEM CLOCK

POWER-ON RESET

EXTERNAL RESET

SYNCHRONIZATION WITH THE DIGITAL AUDIO SYSTEM

ZERO FLAG OUTPUT: PCM3002 ONLY

OPERATIONAL CONTROL

MAPPING OF PROGRAM REGISTERS

SOFTWARE CONTROL (PCM3002)

PROGRAM REGISTER 0

PROGRAM REGISTER 1

PROGRAM REGISTER 2

PROGRAM REGISTER 3

PCM3003 DATA FORMAT CONTROL

Power-Down Control (Pin 7 and Pin 8)

De-Emphasis Control (Pin 17 and Pin 18)

20BIT Audio Data Selection (Pin 16)

APPLICATION AND LAYOUT CONSIDERATIONS

POWER-SUPPLY BYPASSING

GROUNDING

VOLTAGE INPUT

SYSTEM CLOCK

RESET CONTROL

EXTERNAL MUTE CONTROL

TYPICAL CONNECTION DIAGRAM

THEORY OF OPERATION

ADC SECTION

DAC SECTION