Texas Instruments PCI445X User Manual
Implementation
Guide
August 2000 PCI Bus Solutions
SCPU007
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
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Copyright 2000, Texas Instruments Incorporated
About This Manual
Notational Conventions
Preface
Read This First
This manual is intended to assist the designer who is attempting to implement
a solution using the PCI4450 or PCI4451. Much, but not all, of the information
contained herein can also be found elsewhere. However, the smaller size of
this manual, as well as its organization by topics of primary interest to the
hardware designer, make it a much more usable source regarding those
problems most likely to be encountered in the design process.
How to Use This Manual
This document contains the following chapters:
Chapter 1,
examples beyond that contained in the data manuals, which will be useful for
implementing solutions using the PCI4450 or PCI4451.
Appendix A,
of those register bits that can only be cleared by a global reset, and of those
register bits used in conjunction with power management events.
Appendix B,
and conditions which can wake up a device that has been placed in partially
functional state for power conservation.
Appendix C,
input and/or output on each terminal of the device.
Notational Conventions
This document uses the following conventions.
Program listings, program examples, and interactive displays are shown
PCI445X Device
Global Reset Only Bits, PME Context Bits
PME and RI Behavior
PCI445X Buffer T ypes
in a special typeface similar to a typewriter’s. Examples use a bold
version of the special typeface for emphasis; interactive displays use a
bold version of the special typeface to distinguish commands that you
, provides the designer with information and
contains tabular listings
, provides truth tables that explain events
, lists the type of signal buffering used for
iii
Contents
enter from items that the system displays (such as prompts, command
output, error messages, etc.).
Here is a sample program listing:
0011 0005 0001 .field 1, 2
0012 0005 0003 .field 3, 4
0013 0005 0006 .field 6, 3
0014 0006 .even
Here is an example of a system prompt and a command that you might
enter:
C: csr –a /user/ti/simuboard/utilities
In syntax descriptions, the instruction, command, or directive is in a bold
typeface font and parameters are in an
italic typeface
. Portions of a syntax
that are in bold should be entered as shown; portions of a syntax that are
in
italics
describe the type of information that should be entered. Here is
an example of a directive syntax:
.asect “
section name
”,
address
.asect is the directive. This directive has two parameters, indicated by
section name
and
address
. When you use .asect, the first parameter must
be an actual section name, enclosed in double quotes; the second
parameter must be an address.
Square brackets ( [ and ] ) identify an optional parameter. If you use an
optional parameter, you specify the information within the brackets; you
don’t enter the brackets themselves. Here’s an example of an instruction
that has an optional parameter:
LALK
The LALK instruction has two parameters. The first parameter,
constant
16–bit constant [, shift]
, is required. The second parameter,
shift
, is optional. As this
16-bit
syntax shows, if you use the optional second parameter, you must
precede it with a comma.
Square brackets are also used as part of the pathname specification for
VMS pathnames; in this case, the brackets are actually part of the pathname (they are not optional).
Braces ( { and } ) indicate a list. The symbol | (read as
or
) separates items
within the list. Here’s an example of a list:
{ * | *+ | *– }
This provides three choices: *, *+, or *–.
Unless the list is enclosed in square brackets, you must choose one item
from the list.
Some directives can have a varying number of parameters. For example,
the .byte directive can have up to 100 parameters. The syntax for this
directive is:
.byte
iv
value1 [, ... , valuen]
This syntax shows that .byte must have at least one value parameter, but
you have the option of supplying additional value parameters, separated
by commas.
Related Documentation From Texas Instruments
Trademarks
FCC Warning
PCI4450 GFN/GJG PC Card and OHCI Controller Data Sheet
PCI4451 GFN/GJG PC Card and OHCI Controller Data Manual
OHCI.Lynx Configuration Information Application Report
PHY Layout Recommendations Application Report
TSB41LV03A Data Sheet
http://www.ti.com/sc/1394
http://www.ti.com/sc/docs/apps/analog/1394_physical_layer_controllers.html
This equipment is intended for use in a laboratory test environment only. It
generates, uses, and can radiate radio frequency energy and has not been
tested for compliance with the limits of computing devices pursuant to subpart
J of part 15 of FCC rules, which are designed to provide reasonable protection
against radio frequency interference. Operation of this equipment in other
environments may cause interference with radio communications, in which
case the user at his own expense will be required to take whatever measures
may be required to correct this interference.
, SLLS364
, SLLA020A
, SCPS046
, SCPS054
, SLLA077
Trademarks
MicroStar BGA is a trademark of Texas Instruments.
TI is a trademark of Texas Instruments.
Windows is a registered trademark of Microsoft Corporation. (Windows 95, Windows)
v
vi
Contents
Contents
1 PCI445X Device 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 System Features Selection 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.1 Package Types 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.2 G_RST and PRST 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.3 PME and RI Signaling 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.4 ZV Support 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.5 EEPROM for Subsystem V endor and Subsystem ID Registers 1-3. . . . . . . . . . . .
1.1.6 PCI and ISA Style Interrupt 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.7 Socket Power Switches 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.8 Distributed DMA (DDMA) 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.9 Optional PCI Signals 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.10 Socket Activity LEDs 1-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.11 MFUNC7–MFUNC0 Terminal Assignments 1-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.12 Miscellaneous Functions Description 1-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 System Implementation 1-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2.1 Clamping Rails 1-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2.2 PCI Bus Interface 1-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2.3 PC Card Interface 1-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
1.2.4 2-Wire (I
1.3 Sample PCI445X EEPROM Data File 1-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.1 P2C Interface for TPS22x6 Power Switch 1-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.2 Zoomed Video (ZV) Interface 1-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.3 Interrupt Signaling Interface 1-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.4 Miscellaneous Signals 1-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.5 Requirement of Pullup/Pulldown Registers 1-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 BIOS Considerations 1-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4.1 Initialization 1-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4.2 System Sleeping State Consideration 1-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4.3 Docking System Consideration 1-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 Important Information 1-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5.1 G_RST Clamping Rail 1-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5.2 PME/RI_OUT Bit Definition 1-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5.3 Serialized IRQ Data Stream 1-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5.4 Socket Power Control 1-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5.5 External CLOCK Frequency for P
C) Interface for EEPROM 1-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
C Interface 1-22. . . . . . . . . . . . . . . . . . . . . . . . . .
vii
Contents
A Global Reset Only Bits, PME Context Bits A-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.1 Global Reset Only Bits/PME Context Bits A-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B PME and RI Behavior B-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B.1 PME and RI Behavior B-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C PCI445X Buffer Types C-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C.1 PCI445X Buffer Types C-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
viii
Contents
Figures
1–1 Typical System Architecture 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–2 Serialized Interrupt Signal 1-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–3 EEPROM 2-Wire Interface 1-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–4 TPS22X6 Power Switch Interface 1-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–5 Example of a ZV Interface 1-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–6 Distributed DMA Signal Connection 1-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–7 G_RST and V
Relationship 1-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CCP
ix
Contents
Tables
1–1 Registers and Bits Loadable Through Serial EEPROM 1-11. . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–2 PC Card Interface Pullup Register List 1-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–3 PCI Bus Interface Pullup Register List 1-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–4 Miscellaneous Terminals Pullup Register List 1-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–5 Required Pullup/Pulldown Resistors 1-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–1 Global Reset Only Cleared Bits A-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–2 PME Context Bits A-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B–1 CardBus CTSCHG and Wake-Up Signals Truth Table B-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B–2 16-Bit Card RI/STSCHG and Wake-Up Signals Truth Table B-2. . . . . . . . . . . . . . . . . . . . . . . . .
C–1 PCI445X Terminal Function Assignment and Buffer Types C-2. . . . . . . . . . . . . . . . . . . . . . . . . .
C–2 Buffer Type Abbreviations C-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
x
Chapter 1
PCI445X Device
This implementation guide assists platform hardware developers designing
with the PCI445X dual socket PC card and 1394 open host controller interface
(OHCI) link layer controller (LLC). The PCI445X designation refers to any
device in the PCI445X family, for example, the PCI4450 or PCI4451 device.
The document includes an overview of the PCI445X function and features,
terminal assignments and pinout illustrations, PCI445X I/O electrical
characteristics, identification of required passive components and
recommendations for system implementation, and PHY/Link interface signal
isolation considerations.
Advantages of the PCI445X device:
G_RST (Section 1.1.2)
Internal ring oscillator (Section 1.3.1)
Zoomed video auto-detect function (Sections 1.1.4, 1.3.2)
Integrated IEEE1394 OHCI link layer controller
Topic Page
1.1 System Features Selection 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 System Implementation 1-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Sample PCI445X EEPROM Data File 1-12. . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 BIOS Consideration 1-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 Important Information 1-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-1
Figure 1–1 illustrates a platform using the PCI445X device along with the
TSB41L V03 3-port PHY , which provides the necessary interface to implement
a 3-port IEEE1394 node.
Figure 1–1.Typical System Architecture
CPU Memory
South
Bridge
Sound
Controller
North
Bridge
PCI Bus
Graphics
Controller
Audio
Codec
PC Card
Interrupt / PME / RI
19
PCI445X
ZV
4
14
TSB41LV03A
PHY
2
Power
Switch
EEPROM
Socket
Power
1-2
1.1 System Features Selection
This section explains selectable system features. Feature selection is required
for GPIO and MFUNC terminal assignments and PCI445X register
initialization. Detailed system implementation methods are described in the
following sections. All functions cannot necessarily be used at the same time,
because of the limitations of programmable multifunction terminals (i.e.,
MFUNC7–MFUNC0).
1.1.1 Package Types
The Texas Instruments PCI445X device is offered in two package types:
256-terminal ball grid array (BGA) and 257-terminal MicroStar BGA.
MicroStar BGA is a type of chip scale packaging (CSP).
1.1.2 G_RST and PRST
The PCI445X device has two reset inputs, G_RST and PRST. G_RST resets
all registers and state-machines; PRST
to maintain context in a low power state (see T able A–1 and Table A–2). If the
system does not support a wake-up event from D3-state (hot or cold), then
these terminals can be tied together.
System Features Selection
resets registers that are not required
1.1.3 PME and RI Signaling
For supporting a wake-up event, a power management event (PME) and/or
an RI signal should be signaled to the system. PME
RI_OUT/PME terminal. RI_OUT is available on RI_OUT/PME or MFUNC7.
PME and RI_OUT signals are usually connected to the south bridge or
embedded controller (EC). Detailed PME and RI signal behavior is explained
later.
is available only on the
1.1.4 ZV Support
The PCI445X device has internal zoomed video (ZV) buffers. It can support
three ZV sources, from two PC cards and one external source. Refer to the
detailed implementation guide in Section 1.3.2. The PCI445X device has the
ZV autodetect function for supporting a third external zoomed video source.
ZVSTAT and ZVPCLK are required to support the third source. (The ZV
autodetect function needs ZVPCLK for input, and ZVSTAT for enabling.)
ZVSTAT can be assigned on the MFUNC0, MFUNC1, or MFUNC4 terminal.
1.1.5 EEPROM for Subsystem Vendor and Subsystem ID Registers
Subsystem vendor ID and subsystem ID registers (PCI offsets 40h and 42h)
can be loaded from EEPROM through a two-wire serial interface. These
registers can be configured by BIOS if the PCI445X device is implemented on
the motherboard, by setting the SUBSYSRW bit (system control register , PCI
offset 80h, bit 5). EEPROM may be required for docking systems and is
required for add-in cards. The EEPROM interface terminals SDA and SCL are
PCI445X Device
1-3
System Features Selection
automatically assigned on the dedicated SDA and SCL terminals. A pullup
resistor (typically 10 kΩ) must be added on SDA and SCL when using an
EEPROM. The value of the pullup resistor can vary for different EEPROMs.
Refer to the EEPROM data sheet or contact the manufacturer for the
recommended pullup resistor value.
1.1.6 PCI and ISA Style Interrupt
The PCI445X device provides three modes of interrupt signaling:
Parallel PCI interrupts only
Parallel PCI interrupts and serialized ISA interrupts
Serialized PCI interrupts and serialized ISA interrupts
Three PCI interrupts (INTA
either the parallel mode using the MFUNC terminals or in the serial mode. The
number of PCI interrupts may be reduced by setting the INTRTIE bit (system
control register, PCI offset 80h, bit 29), which allows both the CardBus
functions (function 0 and function 1) to report and use INTA
TIEALL bit (system control register, PCI offset 80h, bit 28) which allows all 3
functions (both CardBus + OHCI) to report and use INTA.
1.1.7 Socket Power Switches
The PCI445X device supports TPS2206 and TPS2216 power switches. Refer
to the detailed explanation on each data sheet. The interface between the
power switch and the PCI445X device is serialized, so an external or internal
clock source is required. By default an external power switch clock is assumed
but this can be changed to use the oscillator internal to the PCI445X device
by setting P
1.1.8 Distributed DMA (DDMA)
Most of the systems do not use this function. This function needs PCGNT and
PCREQ signals. PCGNT can be assigned to the MFUNC2 or MFUNC3
terminal. PCREQ can be assigned to the MFUNC0, MFUNC4, or MFUNC7
terminal. (See Section 1.3.4.5, Distributed DMA.)
, INTB, and INTC) may be used and signaled in
or by setting the
2
CCLK bit (system control register, PCI offset 80h, bit 27).
1.1.9 Optional PCI Signals
1.1.9.1 CLKRUN
CLKRUN is the primary method for power reduction on the PCI bus. Most of
the notebook PCs implement CLKRUN. The PCI445X device has a dedicated
CLKRUN terminal. If it is not used, then a pulldown resistor is required to
prevent oscillations on this input.
1.1.9.2 LOCK
This signal can be assigned on the MFUNC1, MFUNC3 or MFUNC7 terminal.
1-4
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