TEXAS INSTRUMENTS PCI2050A Technical data
查询PCI2050A供应商
D
Two 32-Bit, 66-MHz PCI Buses
D
Configurable for PCI Power Management
Interface Specification
D
Provides CompactPCI Hot-Swap
Functionality
D
3.3-V Core Logic With Universal PCI
Interfaces Compatible With 3.3-V and 5-V
PCI Signaling Environments
D
Provides Internal Two-Tier Arbitration for
up to Nine Secondary Bus Masters and
Supports an External Secondary Bus
Arbiter
D
Burst Data Transfers With Pipeline
Architecture to Maximize Data Throughput
in Both Directions
D
Independent Read and Write Buffers for
Each Direction
description
PCI-to-PCI BRIDGE
SCPS067 – MA Y 2001
D
Up to Three Delayed Transactions in Both
Directions
D
Provides 10 Secondary PCI Clock Outputs
D
Predictable Latency per PCI Local Bus
Specification
D
Propagates Bus Locking
D
Supports Write Combining for Enhanced
Data Throughput
D
Supports Frame-to-Frame Delay of Only
Four PCI Clocks From One Bus to Another
D
Secondary Bus is Driven Low During Reset
D
Provides VGA/Palette Memory and I/O, and
Subtractive Decoding Options
D
Advanced Submicron, Low-Power CMOS
Technology
D
Packaged in 208-Terminal QFP
PCI2050A
This data sheet for PCI2050A lists only enhancements to PCI2050 and must be used in conjunction with
PCI2050, PCI-to-PCI bridge, data manual (Literature number SCPS053A)
The T exas Instruments PCI2050A PCI-to-PCI bridge provides a high performance connection path between two
peripheral component interconnect (PCI) buses operating at a maximum bus frequency of 66-MHz.
Transactions occur between masters on one and targets on another PCI bus, and the PCI2050A allows bridged
transactions to occur concurrently on both buses. The bridge supports burst mode transfers to maximize data
throughput, and the two bus traffic paths through the bridge act independently.
The PCI2050A bridge is compliant with the PCI local bus specification, and can be used to overcome the
electrical loading limits of 10 devices per PCI bus and one PCI device per extension slot by creating hierarchical
buses. The PCI2050A provides two-tier internal arbitration for up to nine secondary bus masters and may be
implemented with an external bus arbiter.
The CompactPCI hot-swap extended PCI capability makes the PCI2050A an ideal solution for multifunction
compact PCI cards and adapting single function cards to hot-swap compliance.
The PCI2050A bridge is compliant with PCI-to-PCI bridge specification 1.1. The PCI2050A provides compliance
for PCI Power Management 1.0 and 1.1. The PCI2050A has been designed to lead the industry in power
consumption and data throughput. An advanced CMOS process achieves low system power consumption while
operating at PCI clock rates up to 66-MHz.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
CompactPCI is a trademark of PICMG-PCI Industrial Computer Manufacturers Group, Inc.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 2001, Texas Instruments Incorporated
1
PCI2050A
PCI-to-PCI BRIDGE
SCPS067 – MAY 2001
PDV LOW-PROFILE QUAD FLAT PACKAGE
TOP VIEW
V
CC
GND
S_AD11
GND
S_AD12
S_AD13
V
CC
S_AD14
S_AD15
GND
S_C/BE1
S_PAR
S_SERR
V
CC
S_PERR
S_LOCK
S_STOP
GND
S_DEVSEL
S_TRDY
S_IRDY
V
CC
S_FRAME
S_C/BE2
GND
S_AD16
S_AD17
V
CC
S_AD18
S_AD19
GND
S_AD20
S_AD21
V
CC
S_AD22
S_AD23
GND
S_C/BE3
S_AD24
V
CC
S_AD25
S_AD26
GND
S_AD27
S_AD28
V
CC
S_AD29
S_AD30
GND
S_AD31
S_REQ0
V
CC
CONFIG66
MSK_IN
HSENUM
126
125
127
CCP
P_V
124
GND
123
P_AD1
P_AD0
122
121
CC
V
120
P_AD2
P_AD3
118
119
GND
117
P_AD4
P_AD5
116
115
CC
V
114
P_AD6
P_AD7
112
113
CCP
GND
148
S_AD7
S_AD6
146
147
V
145
CC
S_AD4
S_AD5
144
143
CC
V
S_M66ENA
S_AD10
S_AD9
S_C/BE0
154
153
152
151
S_AD8
150
149
MS0
155
214365871091211141316151817201922212423262528273029323134333635383740394241444346454847504952
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200
201
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208
GND
156
GND
142
S_AD2
S_AD3
140
141
CC
V
139
S_AD0
S_AD1
138
137
GND
136
S_V
135
TMS
TCK
TRST
132
134
133
PCI2050A
CC
V
131
TDO
130
TDI
129
HSLED
128
GND
P_C/BE0
111
110
CC
V
P_AD8
108
109
P_AD9
MS1
107
51 106
CC
V
105
104
103
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99
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53
GND
V
CC
P_M66ENA
P_AD10
GND
P_AD11
P_AD12
V
CC
P_AD13
P_AD14
GND
P_AD15
P_C/BE1
V
CC
P_PAR
P_SERR
P_PERR
P_LOCK
GND
P_STOP
P_DEVSEL
P_TRDY
P_IRDY
V
CC
P_FRAME
P_C/BE2
GND
P_AD16
P_AD17
V
CC
P_AD18
P_AD19
GND
P_AD20
P_AD21
V
CC
P_AD22
P_AD23
GND
P_IDSEL
P_C/BE3
P_AD24
V
CC
P_AD25
P_AD26
GND
P_AD27
P_AD28
V
CC
P_AD29
GND
V
CC
CC
V
S_REQ2
S_REQ3
S_REQ4
S_REQ6
S_REQ5
S_REQ1
2
S_GNT0
S_REQ7
S_REQ8
GND
S_GNT1
S_GNT2
S_GNT3
S_GNT4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
S_GNT5
S_GNT6
S_GNT7
GND
S_CLK
S_GNT8
V
GPIO2
S_RST
S_CFN
GP103/HSSWITCH
CC
GPIO0
GPIO1
S_CLKOUT0
GND
S_CLKOUT1
S_CLKOUT2
S_CLKOUT3
CC
V
S_CLKOUT4
GND
S_CLKOUT6
S_CLKOUT5
S_CLKOUT7
CC
V
S_CLKOUT8
S_CLKOUT9
P_RST
BPCCE
P_CLK
P_GNT
P_REQ
GND
P_AD31
CC
V
P_AD30
GND
primary PCI system terminals
I/O
DESCRIPTION
I/O
DESCRIPTION
TERMINAL
NAME NO.
P_CLK 45 I
P_RST
43 I
Primary PCI bus clock. P_CLK provides timing for all transactions on the primary PCI bus. All primary PCI signals
are sampled at rising edge of P_CLK.
PCI reset. When the primary PCI bus reset is asserted, P_RST causes the bridge to put all output buffers in a
high-impedance state and reset all internal registers. When asserted, the device is completely nonfunctional.
During P_RST
, the secondary interface is driven low. After P_RST is deasserted, the bridge is in its default state.
primary PCI address and data terminals
TERMINAL
NAME NO.
P_AD31
P_AD30
P_AD29
P_AD28
P_AD27
P_AD26
P_AD25
P_AD24
P_AD23
P_AD22
P_AD21
P_AD20
P_AD19
P_AD18
P_AD17
P_AD16
P_AD15
P_AD14
P_AD13
P_AD12
P_AD11
P_AD10
P_AD9
P_AD8
P_AD7
P_AD6
P_AD5
P_AD4
P_AD3
P_AD2
P_AD1
P_AD0
P_C/BE3
P_C/BE2
P_C/BE1
P_C/BE0
49
50
55
57
58
60
61
63
67
68
70
71
73
74
76
77
93
95
96
98
99
101
107
109
112
113
115
116
118
119
121
122
64
79
92
110
Primary address/data bus. These signals make up the multiplexed PCI address and data bus on the primary
interface. During the address phase of a primary bus PCI cycle, P_AD31–P_AD0 contain a 32-bit address
I/O
or other destination information. During the data phase, P_AD31–P_AD0 contain data.
Primary bus commands and byte enables. These signals are multiplexed on the same PCI terminals. During
the address phase of a primary bus PCI cycle, P_C/BE3
phase, this 4-bit bus is used as byte enables. The byte enables determine which byte paths of the full 32-bit
I/O
data bus carry meaningful data. P_C/BE0 applies to byte 0 (P_AD7–P_AD0), P_C/BE1 applies to byte 1
(P_AD15–P_AD8), P_C/BE2
(P_AD31–P_AD24).
PCI2050A
PCI-to-PCI BRIDGE
SCPS067 – MAY 2001
Terminal Functions
–P_C/BE0 define the bus command. During the data
applies to byte 2 (P_AD23–P_AD16), and P_C/BE3 applies to byte 3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
PCI2050A
I/O
DESCRIPTION
PCI-to-PCI BRIDGE
SCPS067 – MAY 2001
Terminal Functions (Continued)
primary PCI interface control terminals
TERMINAL
NAME NO.
Primary device select. The bridge asserts P_DEVSEL to claim a PCI cycle as the target device. As a PCI
P_DEVSEL 84 I/O
P_FRAME
P_GNT
P_IDSEL 65 I
P_IRDY 82 I/O
P_LOCK 87 I/O Primary PCI bus lock. P_LOCK is used to lock the primary bus and gain exclusive access as a bus master .
P_PAR 90 I/O
P_PERR
P_REQ 47 O Primary PCI bus request. Asserted by the bridge to request access to the primary PCI bus as a master.
P_SERR 89 O
P_STOP 85 I/O
P_TRDY 83 I/O
80 I/O
46 I
88 I/O
master on the primary bus, the bridge monitors P_DEVSEL
before time-out occurs, then the bridge terminates the cycle with a master abort.
Primary cycle frame. P_FRAME is driven by the master of a primary bus cycle. P_FRAME is asserted to
indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted. When
P_FRAME is deasserted, the primary bus transaction is in the final data phase.
Primary bus grant to bridge. P_GNT is driven by the primary PCI bus arbiter to grant the bridge access to the
primary PCI bus after the current data transaction has completed. P_GNT
bus request, depending on the primary bus arbitration algorithm.
Primary initialization device select. P_IDSEL selects the bridge during configuration space accesses.
P_IDSEL can be connected to one of the upper 24 PCI address lines on the primary PCI bus.
Note: There is no IDSEL signal interfacing the secondary PCI bus; thus, the entire configuration space of the
bridge can only be accessed from the primary bus.
Primary initiator ready. P_IRDY indicates ability of the primary bus master to complete the current data phase
of the transaction. A data phase is completed on a rising edge of P_CLK where both P_IRDY
are asserted. Until P_IRDY and P_TRDY are both sampled asserted, wait states are inserted.
Primary parity. In all primary bus read and write cycles, the bridge calculates even parity across the P_AD
and P_C/BE
one-P_CLK delay . As a target during PCI read cycles, the calculated parity is compared to the parity indicator
of the master; a miscompare can result in a parity error assertion (P_PERR).
Primary parity error indicator. P_PERR is driven by a primary bus PCI device to indicate that calculated parity
does not match P_PAR when P_PERR
Primary system error. Output pulsed from the bridge when enabled through the command register (PCI offset
04h). indicating a system error has occurred. The bridge needs not be the target of the primary PCI cycle to
assert this signal. When bit 6 is enabled in the bridge control register (PCI offset 3Eh), this signal also pulses,
indicating that a system error has occurred on one of the subordinate buses downstream from the bridge.
Primary cycle stop signal. This signal is driven by a PCI target to request that the master stop the current
primary bus transaction. This signal is used for target disconnects and is commonly asserted by target devices
which do not support burst data transfers.
Primary target ready. P_TRDY indicates the ability of the primary bus target to complete the current data
phase of the transaction. A data phase is completed upon a rising edge of P_CLK where both P_IRDY
P_TRDY
buses. As a bus master during PCI write cycles, the bridge outputs this parity indicator with a
is enabled through bit 6 of the command register (PCI offset 04h).
are asserted. Until both P_IRDY and P_TRDY are asserted, wait states are inserted.
until a target responds. If no target responds
may or may not follow a primary
and P_TRDY
and
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
secondary PCI system terminals
I/O
DESCRIPTION
TERMINAL
NAME NO.
S_CLKOUT9
S_CLKOUT8
S_CLKOUT7
S_CLKOUT6
S_CLKOUT5
S_CLKOUT4
S_CLKOUT3
S_CLKOUT2
S_CLKOUT1
S_CLKOUT0
S_CLK
S_CFN 23 I
S_RST 22 O
42
41
39
38
36
35
33
32
30
29
21 I Secondary PCI bus clock input. This input synchronizes the PCI2050 to the secondary bus clocks.
Secondary PCI bus clocks. Provide timing for all transactions on the secondary PCI bus. Each secondary
O
bus device samples all secondary PCI signals at the rising edge of its corresponding S_CLKOUT input.
Secondary external arbiter enable. When this signal is high, the secondary external arbiter is enabled. When
the external arbiter is enabled, the PCI2050 S_REQ0
to the bridge and S_GNT0
secondary bus.
Secondary PCI reset. S_RST is a logical OR of P_RST and the state of the secondary bus reset bit (bit 6)
of the bridge control register (PCI offset 3Eh). S_RST
secondary interface CLK signal.
PCI2050A
PCI-to-PCI BRIDGE
SCPS067 – MAY 2001
Terminal Functions (Continued)
terminal is reconfigured as a secondary bus grant input
is reconfigured as a secondary bus master request to the external arbiter on the
is asynchronous with respect to the state of the
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
PCI2050A
I/O
DESCRIPTION
PCI-to-PCI BRIDGE
SCPS067 – MAY 2001
Terminal Functions (Continued)
secondary PCI address and data terminals
TERMINAL
NAME NO.
S_AD31
S_AD30
S_AD29
S_AD28
S_AD27
S_AD26
S_AD25
S_AD24
S_AD23
S_AD22
S_AD21
S_AD20
S_AD19
S_AD18
S_AD17
S_AD16
S_AD15
S_AD14
S_AD13
S_AD12
S_AD11
S_AD10
S_AD9
S_AD8
S_AD7
S_AD6
S_AD5
S_AD4
S_AD3
S_AD2
S_AD1
S_AD0
S_C/BE3
S_C/BE2
S_C/BE1
S_C/BE0
S_DEVSEL 175 I/O
S_FRAME 179 I/O
S_GNT8
S_GNT7
S_GNT6
S_GNT5
S_GNT4
S_GNT3
S_GNT2
S_GNT1
S_GNT0
206
204
203
201
200
198
197
195
192
191
189
188
186
185
183
182
165
164
162
161
159
154
152
150
147
146
144
143
141
140
138
137
194
180
167
149
19
18
17
16
15
14
13
11
10
Secondary address/data bus. These signals make up the multiplexed PCI address and data bus on the
secondary interface. During the address phase of a secondary bus PCI cycle, S_AD31–S_AD0 contain a
I/O
32-bit address or other destination information. During the data phase, S_AD31–S_AD0 contain data.
Secondary bus commands and byte enables. These signals are multiplexed on the same PCI terminals.
During the address phase of a secondary bus PCI cycle, S_C/BE3
During the data phase, this 4-bit bus is used as byte enables. The byte enables determine which byte paths
I/O
of the full 32-bit data bus carry meaningful data. S_C/BE0 applies to byte 0 (S_AD7–S_AD0), S_C/BE1
applies to byte 1 (S_AD15–S_AD8), S_C/BE2 applies to byte 2 (S_AD23–S_AD16), and S_C/BE3 applies
to byte 3 (S_AD31–S_AD24).
Secondary device select. The bridge asserts S_DEVSEL to claim a PCI cycle as the target device. As a PCI
master on the secondary bus, the bridge monitors S_DEVSEL
before time-out occurs, then the bridge terminates the cycle with a master abort.
Secondary cycle frame. S_FRAME is driven by the master of a secondary bus cycle. S_FRAME is asserted
to indicate that a bus transaction is beginning and data transfers continue while S_FRAME
S_FRAME
Secondary bus grant to the bridge. The bridge provides internal arbitration and these signals are used to grant
potential secondary PCI bus masters access to the bus. Ten potential masters (including the bridge) can be
located on the secondary PCI bus.
O
When the internal arbiter is disabled, S_GNT0
for the bridge.
is deasserted, the secondary bus transaction is in the final data phase.
–S_C/BE0 define the bus command.
until a target responds. If no target responds
is asserted. When
is reconfigured as an external secondary bus request signal
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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