Texas Instruments OMAP5910, OMAP5912 Reference Manual

OMAP5910/5912 Multimedia Processor

DSP Subsystem

Reference Guide

Literature Number: SPRU890A

May 2005

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Products Applications

Amplifiers amplifier.ti.com Audio www.ti.com/audio

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DSP dsp.ti.com Broadband www.ti.com/broadband

Interface interface.ti.com Digital Control www.ti.com/digitalcontrol

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Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork

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Copyright © 2005, Texas Instruments Incorporated

About This Manual

This document describes the OMAP5910/5912 multimedia processor DSP
subsystem.

Notational Conventions

This document uses the following conventions.

- Hexadecimal numbers are shown with the suffix h. For example, the fol-

lowing number is 40 hexadecimal (decimal 64): 40h.

Related Documentation From Texas Instruments

Documentation that describes the OMAP5910/5912 devices, related
peripherals, and other technical collateral, is available in the OMAP5910
Product Folder on TI’s website: www.ti.com/omap5910, and in the OMAP5912
Product Folder on TI’s website: www.ti.com/omap5912.

Preface

Read This First

Trademarks

OMAP and the OMAP symbol are trademarks of Texas Instruments.

3DSP SubsystemSPRU890A

4 DSP Subsystem SPRU890A

Contents

Contents

1 Digital Signal Processor Subsystem Overview 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1 Architecture Overview 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 Features 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 Differences Between the OMAP5910 and OMAP5912 DSP Subsystems 19. . . . . . . . . . . .

1.4 Functional Block Diagrams 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 C55x DSP Core Overview 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 DSP Core Features 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 Introduction to the DSP Core 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3 Introduction to the Hardware Accelerators 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 DSP Subsystem Memory 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1 Internal Memory Space 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2 DSP External Memory Space 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3 I/O Memory Space 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4 Memory Maps 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 Instruction Cache 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1 Introduction 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1.1 Features 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1.2 Functional Block Diagram 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1.3 Supported Cache Configurations 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2 Instruction Cache Architecture 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.1 Introduction to the I-Cache 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.2 Instruction Cache Blocks 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.3 Instruction Cache Operation 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.4 DSP Core Bits for Controlling the I-Cache 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.5 Initialization 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.6 Reset Considerations 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.7 Clock Control 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.8 Power Management 42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.9 Emulation Considerations 42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.10 Timing Considerations 42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3 Configuring the I-Cache With the 2-Way Cache and No RAM Set Blocks 44. . . . . . . . . . . .

4.3.1 Architectural/Operational Description 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3.2 Software Configuration 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3.3 System Traffic Considerations 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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4.4 Configuring the I-Cache With the 2-Way Cache and One RAM Set 45. . . . . . . . . . . . . . . . .

4.4.1 Architectural/Operational Description 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.4.2 Software Configuration 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.4.3 System Traffic Considerations 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.5 Configuring the I-Cache With the 2-Way Cache and Two RAM Sets 46. . . . . . . . . . . . . . . .

4.5.1 Architectural/Operational Description 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.5.2 Software Configuration 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.5.3 System Traffic Considerations 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.6 Instruction Cache Registers 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.6.1 Overview 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.6.2 I-Cache Global Control Register (GCR) 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.6.3 I-Cache Line Flush Registers (FLR0, FLR1) 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.6.4 I-Cache N-Way Control Register (NWCR) 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.6.5 I-Cache RAM Set Control Registers (RCR1 and RCR2) 53. . . . . . . . . . . . . . . . . . .

4.6.6 I-Cache RAM Set Tag Registers (RTR1 and RTR2) 55. . . . . . . . . . . . . . . . . . . . . . .

4.6.7 I-Cache Status Register (ISR) 57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5 DSP External Memory Interface 58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.1 Overview 58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2 Peripheral Architecture 58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2.1 Clock Control 58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2.2 Memory Map 58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2.3 DSP External Memory Accesses 58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2.4 EMIF Requests 60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2.5 Write Posting: Buffering Write to DSP External Memory 61. . . . . . . . . . . . . . . . . . .

5.2.6 Reset Considerations 62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2.7 Power Management 62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3 EMIF Registers 63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3.1 Overview 63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3.2 EMIF Global Control Register (GCR) 63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3.3 EMIF Global Reset Register (GRR) 64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6 DSP Memory Management Unit 65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.1 Overview 65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.1.1 Purpose of the MMU 65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.1.2 Features 66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.1.3 Functional Block Diagram 67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.1.4 Supported Usage of the DSP MMU 67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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6.2 MMU Architecture 68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2.1 Summary of Address Translation Process 68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2.2 Translation Look-Aside Buffer (TLB) 69. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2.3 Table Walking Logic 79. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2.4 Memory Address Translation 82. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2.5 First-Level Translation Table 83. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2.6 Second-Level Translation Tables 87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2.7 MMU Error Handling 93. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2.8 Reset Considerations 94. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2.9 Clock Control 95. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2.10 Initialization 95. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2.11 Interrupt Support 95. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2.12 Power Management 96. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.3 Using the MPU to Manage the TLB 96. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.3.1 Architectural/Operational Description 96. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.3.2 Software Configuration 97. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.3.3 System Traffic Considerations 98. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.4 Using Table Walking Logic to Manage the TLB 98. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.4.1 Architectural/Operational Description 98. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.4.2 Software Configuration 99. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.4.3 System Traffic Considerations 100. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.5 DSP MMU Registers 101. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.5.1 Overview 101. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.5.2 MMU Pre-Fetch Register (PREFETCH_REG) 102. . . . . . . . . . . . . . . . . . . . . . . . . . .

DSP Side 103. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MPU Side 103. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.5.3 MMU Pre-Fetch Status Register (WALKING_ST_REG) 103. . . . . . . . . . . . . . . . . . .

6.5.4 MMU Control Register (CNTL_REG) 104. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.5.5 MMU Fault Address Registers (FAULT_AD_H_REG, FAULT_AD_L_REG) 105. .

6.5.6 MMU Fault Status Register (FAULT_ST_REG) 107. . . . . . . . . . . . . . . . . . . . . . . . . .

6.5.7 MMU Interrupt Acknowledge Register (IT_ACK_REG) 108. . . . . . . . . . . . . . . . . . . .

6.5.8 MMU Translation Table Registers (TTB_H_REG, TTB_L_REG) 109. . . . . . . . . . .

6.5.9 MMU Lock/Protect Entry Register (LOCK_REG) 110. . . . . . . . . . . . . . . . . . . . . . . . .

6.5.10 MMU Read/Write TLB Entry Register (LD_TLB_REG) 111. . . . . . . . . . . . . . . . . . . .

6.5.11 MMU CAM Entry Registers (CAM_H_REG, CAM_L_REG) 112. . . . . . . . . . . . . . . .

6.5.12 MMU RAM Entry Registers (RAM_H_REG, RAM_L_REG) 114. . . . . . . . . . . . . . . .

6.5.13 MMU TLB Global Flush Register (GFLUSH_REG) 115. . . . . . . . . . . . . . . . . . . . . . .

6.5.14 MMU TLB Entry Flush Register (FLUSH_ENTRY_REG) 116. . . . . . . . . . . . . . . . . .

6.5.15 MMU Read CAM Entry Registers

(READ_CAM_H_REG, READ_CAM_L_REG) 117. . . . . . . . . . . . . . . . . . . . . . . . . . .

6.5.16 MMU Read RAM Entry Registers

(READ_RAM_H_REG, READ_RAM_L_REG) 119. . . . . . . . . . . . . . . . . . . . . . . . . . .

6.5.17 MMU Idle Control Register (DSPMMU_IDLE_CTRL) 120. . . . . . . . . . . . . . . . . . . . .

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7 DSP DMA 121. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.1 Overview 121. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.1.1 Purpose of the DSP DMA 121. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.1.2 Features 121. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.1.3 Block Diagram of the DMA Controller 122. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2 DSP DMA Controller Architecture 124. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2.1 Clock Control 124. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2.2 Memory Map 124. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2.3 Channels and Port Accesses 125. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2.4 Channel Auto-Initialization Capability 127. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2.5 MPUI Access Configurations 131. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2.6 Service Chain 132. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2.7 Units of Data: Byte, Element, Frame, and Block 137. . . . . . . . . . . . . . . . . . . . . . . . .

7.2.8 Start Address in a Channel 137. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2.9 Updating Addresses in a Channel 139. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2.10 Data Packing Capability 139. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2.11 Data Burst Capability 141. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2.12 Synchronizing Channel Activity 142. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2.13 DSP GDMA Handler (OMAP5912 Only) 146. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Functional Multiplexing DSP DMA Register A

(FUNC_MUX_DSP_DMA_A) 149. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Functional Multiplexing DSP DMA Register B

(FUNC_MUX_DSP_DMA_B) 151. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Functional Multiplexing DSP DMA Register C

(FUNC_MUX_DSP_DMA_C) 152. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Functional Multiplexing DSP DMA Register D

(FUNC_MUX_DSP_DMA_D) 154. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2.14 Reset Considerations 154. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2.15 Interrupt Support 155. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2.16 Power Management 158. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2.17 Emulation Considerations 158. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2.18 Latency in DMA Transfers 159. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.3 DSP DMA Controller Registers 160. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.3.1 Overview 160. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.3.2 DMA Global Control Register (DMAGCR) 161. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.3.3 DMA Global Software Compatibility Register (DMAGSCR) 162. . . . . . . . . . . . . . . .

7.3.4 DMA Global Timeout Control Register (DMAGTCR) 163. . . . . . . . . . . . . . . . . . . . . .

7.3.5 DMA Channel Control Register (DMACCR) 164. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.3.6 DMA Interrupt Control Register (DMACICR) and Status

Register (DMACSR) 170. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.3.7 DMA Source and Destination Parameters Register (DMACSDP) 174. . . . . . . . . . .

7.3.8 DMA Source Start Address Registers (DMACSSAU and DMACSSAL) 179. . . . .

7.3.9 DMA Destination Start Address Registers (DMACDSAU

and DMACDSAL) 180. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8 DSP Subsystem SPRU890A

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7.3.10 DMA Element Number Register (DMACEN) and Frame

Number Register (DMACFN) 181. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.3.11 DMA Element Index Registers (DMACSEI, DMACDEI) and Frame

Index Registers (DMACSFI, DMACDFI) 182. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.3.12 DMA Source Address Counter (DMACSAC) and Destination

Address Counter (DMACDAC) 186. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8 TI Peripheral Bus Bridges 187. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.1 Introduction 187. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.2 DSP Private Peripherals 187. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.3 DSP Public Peripherals 188. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.4 DSP/MPU Shared Peripherals 188. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.5 Peripheral Access Rate 188. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.6 Peripheral Access Timeout 191. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.7 TIPB Register 191. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.7.1 Overview 191. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.7.2 TIPB Control Mode Register (CMR) 191. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DSP Side 192. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MPU Side 192. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9 MPU Interface Port 194. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.1 Introduction 194. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.2 MPUI and MPUI Port Overview 194. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.2.1 MPUI Port Modes 195. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.2.2 HOM/SAM Change Outside of Reset 196. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10 DSP Subsystem Endianess 197. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.1 Endianess Within OMAP 197. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.2 Endianess Conversion 198. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.3 Endianess Conversion Modules 199. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.3.1 Endianess Conversion by the DSP MMU 200. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.3.2 Endianess Conversion by the MPUI 201. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11 DSP Subsystem Interrupts 204. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.1 Overview 204. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.2 First Level Interrupts 207. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.2.1 OMAP5910 First Level Interrupt Mapping and Interrupt Registers 207. . . . . . . . . .

11.2.2 OMAP5912 First Level Interrupt Mapping and Interrupt Registers 210. . . . . . . . . .

11.3 Second Level Interrupts 213. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9DSP SubsystemSPRU890A

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12 DSP Subsystem Reset, Clocking, Idle Control, and Boot 216. . . . . . . . . . . . . . . . . . . . . . . . . . .

12.1 Reset Control 216. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.1.1 Hardware (Cold) Resets 216. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.1.2 Software (Warm) Resets 216. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.2 Clock Source 217. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.3 Idle Control 218. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.3.1 Idle Control at the DSP Subsystem Level 219. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.3.2 Idle Control at the DSP Module Level 219. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Condition 1: CPU Domain Active 222. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Condition 2: CPU Domain Idle 222. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Placing the DSP DMA in Idle 224. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Placing the Entire DSP Module Domain in Idle 224. . . . . . . . . . . . . . . . . . . . . . . . . .

12.4 DSP Bootloader 228. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.4.1 Introduction 228. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.4.2 Bootloader Operation 229. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DSP Side 230. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MPU Side 230. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.4.3 Boot Modes 230. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.4.4 Bootloader Sequence 233. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Revision History 234. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10 DSP Subsystem SPRU890A

Figures

Figures

1 OMAP5910 DSP Subsystem and Modules 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 OMAP5912 DSP Subsystem and Modules 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 DSP Core Diagram 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 Internal Memory Connections in the DSP Subsystem 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5 Conceptual Block Diagram of the I-Cache in the DSP Subsystem 31. . . . . . . . . . . . . . . . . . . .

6 2-Way Cache 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7 RAM Sets 1 and 2 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8 Fetch Address Fields for the 2-Way Cache Register 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9 Fetch Address Fields for a RAM Set 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10 Flow Chart of the Line Load Process 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11 CAFRZ, CAEN, and CACLR Bits in ST3_55 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12 I-Cache Global Control Register (GCR) 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13 I-Cache Line Flush Registers (FLR0, FLR1) 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14 I-Cache N-Way Control Register (NWCR) 53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15 I-Cache RAM Set Control Registers (RCR1 and RCR2) 54. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

16 I-Cache RAM Set Tag Registers (RTR1 and RTR2) 56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

17 I-Cache Status Register (ISR) 57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

18 DSP Subsystem External Memory Connections 59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

19 EMIF Global Control Register (GCR) 63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

20 EMIF Global Reset Register (GRR) 64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

21 Memory Defragmentation 65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

22 Task Protection 66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

23 DSP Subsystem Memory Interface 67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

24 MMU Address Translation 68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

25 MMU Translation Process 69. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

26 TLB Entry Structure 70. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

27 Determining Virtual Address Tags for TLB CAM Entries 71. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

28 Determining Physical Address Tags for TLB RAM Entries 73. . . . . . . . . . . . . . . . . . . . . . . . . . .

29 Physical Address Generation Using TLB Entry with Size = 00b (Section) 74. . . . . . . . . . . . . .

30 Physical Address Generation Using TLB Entry with Size = 01b (Large Page) 75. . . . . . . . . .

31 Physical Address Generation Using TLB Entry with Size = 10b (Small Page) 75. . . . . . . . . . .

32 Physical Address Generation Using TLB Entry with Size = 11b (Tiny Page) 76. . . . . . . . . . . .

33 TLB Entry Lock Mechanism 77. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

34 Physical Address Calculation 80. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

35 Sample Translation Table Hierarchy 82. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

36 DSP Subsystem Virtual Address Space Divided Into Sections 84. . . . . . . . . . . . . . . . . . . . . . . .

11DSP SubsystemSPRU890A

Figures

37 First-Level Descriptor Address Calculation 85. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

38 First-Level Descriptor Format Based on Two Least-Significant Bits 86. . . . . . . . . . . . . . . . . . .

39 Translation for a Virtual Memory Section 87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

40 Second-Level Descriptor Format Based on Two Least-Significant Bits 88. . . . . . . . . . . . . . . .

41 Translation for a Large Page 89. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

42 Translation for a Small Page 90. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

43 Translation for a Tiny Page 90. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

44 Calculating the Descriptor Address in a Coarse Page Table 91. . . . . . . . . . . . . . . . . . . . . . . . . .

45 Calculating the Descriptor Address in a Fine Page Table 92. . . . . . . . . . . . . . . . . . . . . . . . . . . .

46 DSP Subsystem External Memory Interface 97. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

47 DSP Subsystem External Memory Interface 99. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

48 MMU Pre-Fetch Register (PREFETCH_REG) 103. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

49 MMU Pre-Fetch Status Register (WALKING_ST_REG) 103. . . . . . . . . . . . . . . . . . . . . . . . . . . .

50 MMU Control Register (CNTL_REG) 104. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

51 MMU Fault Address Registers (FAULT_AD_H_REG, FAULT_AD_L_REG) 106. . . . . . . . . . .

52 MMU Fault Status Register (FAULT_ST_REG) 107. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

53 MMU Interrupt Acknowledge Register (IT_ACK_REG) 108. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

54 MMU Translation Table Registers (TTB_H_REG, TTB_L_REG) 109. . . . . . . . . . . . . . . . . . . . .

55 MMU Lock/Protect Entry Register (LOCK_REG) 110. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

56 MMU Read/Write TLB Entry Register (LD_TLB_REG) 111. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

57 MMU CAM Entry Registers (CAM_H_REG, CAM_L_REG) 112. . . . . . . . . . . . . . . . . . . . . . . . .

58 MMU RAM Entry Registers (RAM_H_REG, RAM_L_REG) 114. . . . . . . . . . . . . . . . . . . . . . . . .

59 MMU TLB Global Flush Register (GFLUSH_REG) 115. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

60 MMU TLB Entry Flush Register (FLUSH_ENTRY_REG) 116. . . . . . . . . . . . . . . . . . . . . . . . . . .

61 MMU CAM Entry Read Registers (READ_CAM_H_REG, READ_CAM_L_REG) 117. . . . . . .

62 MMU Read RAM Entry Registers (READ_RAM_H_REG, READ_RAM_L_REG) 119. . . . . . .

63 MMU Idle Control Register (DSPMMU_IDLE_CTRL) 120. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

64 Conceptual Block Diagram of the DMA Controller Connections 123. . . . . . . . . . . . . . . . . . . . . .

65 High-Level Data Memory Map for DSP Subsystem 124. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

66 High-Level I/O Memory Map for DSP Subsystem 125. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

67 The Two Parts of a DMA Controller Transfer 125. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

68 Registers for Controlling the Context of a Channel 126. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

69 DMA Channel Control Register (DMACCR) 127. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

70 Auto-Initialization Sequence With Unchanging Context (REPEAT = 1) 130. . . . . . . . . . . . . . . .

71 Auto-initialization Sequence With Changing Context (REPEAT = 0) 131. . . . . . . . . . . . . . . . . .

72 MPUI Access Configurations 132. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

73 One Possible Configuration for the Service Chains 133. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

74 Service Chain Applied to Three DMA Ports 136. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

75 DSP GDMA Handler 147. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

76 Functional Multiplexing DSP DMA Register A (FUNC_MUX_DSP_DMA_A) 150. . . . . . . . . . .

77 Functional Multiplexing DSP DMA Register B (FUNC_MUX_DSP_DMA_B) 151. . . . . . . . . . .

78 Functional Multiplexing DSP DMA Register C (FUNC_MUX_DSP_DMA_C) 153. . . . . . . . . .

79 Functional Multiplexing DSP DMA Register D (FUNC_MUX_DSP_DMA_D) 154. . . . . . . . . .

80 Triggering a Channel Interrupt Request 156. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12 DSP Subsystem SPRU890A

Figures

81 DMA Global Control Register (DMAGCR) 161. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

82 DMA Global Software Compatibility Register (DMAGSCR) 162. . . . . . . . . . . . . . . . . . . . . . . . .

83 DMA Global Timeout Control Register (DMAGTCR) 163. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

84 DMA Channel Control Register (DMACCR) 165. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

85 DMA Interrupt Control Register (DMACICR) and Status Register (DMACSR) 171. . . . . . . . .

86 DMA Source and Destination Parameters Register (DMACSDP) 175. . . . . . . . . . . . . . . . . . . .

87 DMA Source Start Address Registers (DMACSSAU and DMACSSAL) 179. . . . . . . . . . . . . . .

88 DMA Destination Start Address Registers (DMACDSAU and DMACDSAL) 181. . . . . . . . . . .

89 DMA Element Number Register (DMACEN) and Frame Number

Register (DMACFN) 182. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

90 DMA Source Element Index Registers (DMACSEI, DMACDEI) and Frame

Index Registers (DMACSFI, DMACDFI) 185. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

91 DMA Source Address Counter (DMACSAC) and Destination Address

Counter (DMACDAC) 186. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

92 TIPB Control Mode Register (CMR) 192. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

93 MPUI Mode Change Bits in ST3_55 196. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

94 DSP MMU Endianess Control Register (DSP_ENDIAN_CONV) 201. . . . . . . . . . . . . . . . . . . . .

95 MPUI Control Register (CTRL_REG) 203. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

96 OMAP5910 DSP Subsystem Interrupts 205. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

97 OMAP5912 DSP Subsystem Interrupts 206. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

98 IFR0 and IER0 Bit Locations (OMAP5910) 209. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

99 IFR1 and IER1 Bit Locations (OMAP5910) 210. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

100 IFR0 and IER0 Bit Locations (OMAP5912) 212. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

101 IFR1 and IER1 Bit Locations (OMAP5912) 212. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

102 OMAP Clock Generation 217. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

103 DSP Clock Domain 217. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

104 Generation of DSP Subsystem Master Clock and DSP MMU Clock 218. . . . . . . . . . . . . . . . . .

105 Idle Configuration Process 221. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

106 Idle Control Register (ICR) 225. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

107 Idle Status Register (ISTR) 226. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

108 DSP Boot Configuration Register (DSP_BOOT_CONFIG) 230. . . . . . . . . . . . . . . . . . . . . . . . . .

13DSP SubsystemSPRU890A

Tables

Tables

1 OMAP5910/5912 DSP Subsystem Global Memory Map 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Fetch Address Field Descriptions for the 2-Way Cache Register Field Descriptions 36. . . . .

3 Fetch Address Field Descriptions for a RAM Set 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 Instruction Presence Check and I-Cache Response 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5 Summary of the I-Cache Registers 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6 I-Cache Global Control Register (GCR) Bits Field Descriptions 50. . . . . . . . . . . . . . . . . . . . . . .

7 I-Cache Line Flush Register 0 (FLR0) Field Descriptions 52. . . . . . . . . . . . . . . . . . . . . . . . . . . .

8 I-Cache Line Flush Register 1 (FLR1) Field Descriptions 52. . . . . . . . . . . . . . . . . . . . . . . . . . . .

9 I-Cache N-way Control Register (NWCR) Field Descriptions 53. . . . . . . . . . . . . . . . . . . . . . . . .

10 I-Cache RAM Set 1 Control Register (RCR1) and RAM Set 2 Control Register

11 I-Cache RAM Set 1 Tag Register (RTR1) Field Descriptions 56. . . . . . . . . . . . . . . . . . . . . . . . .

12 I-Cache RAM Set 2 Tag Register (RTR2) Field Descriptions 56. . . . . . . . . . . . . . . . . . . . . . . . .

13 I-Cache Status Register (ISR) Field Descriptions 57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14 EMIF Requests and Their Priorities 60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15 EMIF Requests Associated with Dual and Long Data Accesses 61. . . . . . . . . . . . . . . . . . . . . .

16 Summary of the EMIF Registers 63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

17 EMIF Global Control Register (GCR) Field Descriptions 64. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

18 EMIF Global Reset Register (GRR) Field Descriptions 64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

19 First−Level Descriptor Contents 86. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

20 First−Level Descriptor Contents 89. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

21 Summary of DSP MMU Registers 101. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

22 MMU Pre-Fetch Register (PREFETCH_REG) Field Descriptions 103. . . . . . . . . . . . . . . . . . . .

23 MMU Pre-Fetch Status Register (WALKING_ST_REG) Field Descriptions 104. . . . . . . . . . . .

24 Control Register (CNTL_REG) Field Descriptions 105. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

25 MMU MSB Fault Address Register (FAULT_AD_H_REG) Field Descriptions 106. . . . . . . . . .

26 MMU LSB Fault Address Register (FAULT_AD_L_REG) Field Descriptions 106. . . . . . . . . . .

27 MMU Fault Status Register (FAULT_ST_REG) Field Descriptions 107. . . . . . . . . . . . . . . . . . .

28 MMU Interrupt Acknowledge Register (IT_ACK_REG) Field Descriptions 109. . . . . . . . . . . . .

29 MMU MSB Translation Table Register (TTB_H_REG) Field Descriptions 110. . . . . . . . . . . . .

30 MMU LSB Translation Table Register (TTB_L_REG) Field Descriptions 110. . . . . . . . . . . . . .

31 MMU Lock/Protect Entry Register (LOCK_REG) Field Descriptions 111. . . . . . . . . . . . . . . . . .

32 MMU Read/Write TLB Entry Register (LD_TLB_REG) Field Descriptions 112. . . . . . . . . . . . .

33 MMU MSB CAM Entry Register (CAM_H_REG) Field Descriptions 113. . . . . . . . . . . . . . . . . .

34 MMU LSB CAM Entry Register (CAM_L_REG) Field Descriptions 113. . . . . . . . . . . . . . . . . . .

35 MMU MSB RAM Entry Register (RAM_H_REG) Field Descriptions 114. . . . . . . . . . . . . . . . . .

(RCR2) Field Descriptions 55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14 DSP Subsystem SPRU890A

Tables

36 MMU LSB RAM Entry Register (RAM_L_REG) Field Descriptions 114. . . . . . . . . . . . . . . . . . .

37 MMU TLB Global Flush Register (GFLUSH_REG) Field Descriptions 115. . . . . . . . . . . . . . . .

38 MMU TLB Entry Flush Register (FLUSH_ENTRY_REG) Field Descriptions 116. . . . . . . . . . .

39 MMU MSB CAM Entry Read Register (READ_CAM_H_REG) Field Descriptions 117. . . . . .

40 MMU LSB CAM Entry Read Register (READ_CAM_L_REG) Field Descriptions 118. . . . . . .

41 MMU MSB RAM Entry Read Register (READ_RAM_H_REG) Field Descriptions 119. . . . . .

42 MMU LSB RAM Entry Read Register (READ_RAM_L_REG) Field Descriptions 120. . . . . . .

43 MMU Idle Control Register (DSPMMU_IDLE_CTRL) Field Descriptions 120. . . . . . . . . . . . . .

44 DMA Channel Control Register (DMACCR) Field Descriptions 128. . . . . . . . . . . . . . . . . . . . . .

45 Activity Shown in 74 135. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

46 Registers Used to Define the Start Addresses for a DMA Transfer 137. . . . . . . . . . . . . . . . . . .

47 DMA Controller Ports 139. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

48 DMA Controller Data Packing 140. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

49 Read/Write Synchronization 143. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

50 DSP DMA Controller Synchronization Events for OMAP5910 145. . . . . . . . . . . . . . . . . . . . . . .

51 DSP DMA Controller Synchronization Events for OMAP5912 146. . . . . . . . . . . . . . . . . . . . . . .

52 DSP GDMA Handler Input Request Lines 147. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

53 Registers of the OMAP5912 DSP GDMA Handler 149. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

54 Functional Multiplexing DSP DMA Register A (FUNC_MUX_DSP_DMA_A)

Field Descriptions 150. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

55 Functional Multiplexing DSP DMA Register B (FUNC_MUX_DSP_DMA_B)

Field Descriptions 152. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

56 Functional Multiplexing DSP DMA Register C (FUNC_MUX_DSP_DMA_C)

Field Descriptions 153. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

57 Functional Multiplexing DSP DMA Register D (FUNC_MUX_DSP_DMA_D)

Field Descriptions 154. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

58 DMA Controller Operational Events and Their Associated Bits and Interrupts 155. . . . . . . . .

59 Registers of the DMA Controller 160. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

60 DMA Global Control Register (DMAGCR) Field Descriptions 161. . . . . . . . . . . . . . . . . . . . . . . .

61 DMA Global Software Compatibility Register (DMAGSCR) Field Descriptions 163. . . . . . . . .

62 DMA Global Timeout Control Register (DMAGTCR) Field Descriptions 164. . . . . . . . . . . . . . .

63 DMA Channel Control Register (DMACCR) Field Descriptions 165. . . . . . . . . . . . . . . . . . . . . .

64 DMA Interrupt Control Register (DMACICR) Fields Descriptions 171. . . . . . . . . . . . . . . . . . . . .

65 DMA Status Register (DMACSR) Field Descriptions 173. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

66 DMA Source and Destination Parameters Register (DMACSDP) Field Descriptions 175. . . .

67 DMA Source Start Address Register − Upper Part (DMACSSAU) Field Descriptions 180. . .
68 DMA Source Start Address Register − Lower Part (DMACSSAL) Field Descriptions 180. . .
69 DMA Destination Start Address Register − Upper Part (DMACDSAU)

Field Descriptions 181. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

70 DMA Destination Start Address Register − Lower Part (DMACDSAL)

Field Descriptions 181. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

71 DMA Element Number Register (DMACEN) Field Descriptions 182. . . . . . . . . . . . . . . . . . . . . .

72 Frame Number Register (DMACFN) Field Descriptions 182. . . . . . . . . . . . . . . . . . . . . . . . . . . .

73 DMA Source Element Index Register (DMACSEI/DMACEI) Field Descriptions 185. . . . . . . .

74 DMA Source Frame Index Register (DMACSFI / DMACFI) Field Descriptions 185. . . . . . . . .

15DSP SubsystemSPRU890A

Tables

75 DMA Destination Element Index Register (DMACDEI) Field Descriptions 186. . . . . . . . . . . . .

76 DMA Destination Frame Index Register (DMACDFI) Field Descriptions 186. . . . . . . . . . . . . .

77 DMA Source Address Counter (DMACSAC) Field Descriptions 186. . . . . . . . . . . . . . . . . . . . . .

78 DMA Destination Address Counter (DMACDAC) Field Descriptions 186. . . . . . . . . . . . . . . . . .

79 TIPB Access Rates 189. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

80 Peripherals Affected by Access Factor Bits (OMAP5912) 190. . . . . . . . . . . . . . . . . . . . . . . . . . .

81 Peripherals Affected by Access Factor Bits (OMAP5910) 190. . . . . . . . . . . . . . . . . . . . . . . . . . .

82 Register of the TIPB Bridge 191. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

83 TIPB Control Mode Register (CMR) Field Descriptions 192. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

84 HOM_R and HOM_P Bits in DSP Core Register ST3_55 197. . . . . . . . . . . . . . . . . . . . . . . . . . .

85 Little-Endian versus Big-Endian Data Format 197. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

86 Big-Endian Access of Little-Endian Data 199. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

87 Effect of DSP MMU Endianess Conversion Settings 200. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

88 DSP MMU Endianess Control Register (DSP_ENDIAN_CONV) Field Descriptions 201. . . .

89 Effect of MPUI Endianess Conversion Settings 202. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

90 MPUI Control Register (CTRL_REG) Field Descriptions 203. . . . . . . . . . . . . . . . . . . . . . . . . . . .

91 OMAP5910 Level 1 Interrupt Mapping 208. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

92 OMAP5912 Level 1 Interrupt Mapping 210. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

93 OMAP5910 Level 2 Interrupt Mapping 213. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

94 OMAP5912 Level 2.0 Interrupt Mapping 214. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

95 OMAP5912 Level 2.1 Interrupt Mapping 214. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

96 Idle Domains in the DSP 219. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

97 Changing Idle Configurations 222. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

98 DSP Core Response After Reactivation 223. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

99 Registers for DSP Module Idle Control 225. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

100 Idle Control Register (ICR) Field Descriptions 226. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

101 Idle Status Register (ISTR) Field Descriptions 227. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

102 DSP PDROM Contents 229. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

103 Bootloader Initialization 229. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

104 DSP Boot Configuration Register (DSP_BOOT_CONFIG) Field Descriptions 230. . . . . . . . .

105 Registers for DSP Module Idle Control 231. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

106 Document Revision History 234. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

16 DSP Subsystem SPRU890A

1 Digital Signal Processor Subsystem Overview

1.1 Architecture Overview

The Digital Signal Processor (DSP) Subsystem is a collection of modules
which include the TMS320C55x CPU processor along with its hardware
accelerators, tightly coupled memory, instruction cache, and dedicated DMA,
the interfaces it uses to communicate with rest of the OMAP device, as well
as a number of peripherals.

The TMS320C55x core processor (also referred to as the DSP core) and the
peripherals included in the DSP subsystem communicate with:

- The MPU core via the microprocessor unit interface (MPUI)

- Various standard memories via the external memory interface (EMIF)

- Various system peripherals via two TI peripheral bus (TIPB) bridges

Figure 1 and Figure 2 in section 1.4 show block diagrams for the OMAP5910
and OMAP5912 DSP subsystems.

DSP Subsystem

1.2 Features

The DSP subsystem is composed of several portions: the DSP module, the
peripherals that surround that module, and several interfaces used to
communicate with the rest of the OMAP modules. Each portion has the
following components:

- DSP module:

J TMS320C55x (C55x) DSP core

J Tightly coupled hardware accelerators: discrete cosine

transform/inverse discrete cosine transform (DCT/IDCT), motion
estimation, and half-pixel interpolation

J Tightly coupled memories and their interfaces: dual-access RAM

(DARAM), single-access RAM (SARAM), programmable dynamic
ROM, and an instruction cache (I-Cache)

J Six-channel DMA controller that can copy memory contents from one

address to another without DSP core intervention

17DSP SubsystemSPRU890A

Digital Signal Processor Subsystem Overview

DSP subsystem interfaces:

-

J External memory interface (EMIF) that connects the DSP core to

external and loosely coupled memories

J MPUI port that permits access to DSP resources by the MPU and

system DMA

J TIPB that provides two external bus interfaces for private and public

peripherals

- DSP subsystem peripherals:

J Private peripherals are on the DSP private peripheral bus, and can

only be accessed by the DSP core. DSP private peripherals include:

H Three 32-bit timers

H Watchdog timer

H Interrupt handlers

J Public peripherals are on the DSP public peripheral bus. These

peripherals are directly accessible by the DSP core and DSP DMA.
The MPU core can also access these peripherals through the MPUI
port. DSP public peripherals include:

H Two multichannel buffered serial ports (McBSPs)

H Two multichannel serial interfaces (MCSIs)

J The DSP core and DMA controller also have access to system

peripherals (also referred to as shared peripherals). Shared
peripherals are connected to both the MPU public peripheral bus and
the DSP public peripheral bus. Shared peripherals include:

H Mailbox module to permit interrupt-based signaling between the

DSP and MPU cores

H Three universal asynchronous receiver/transmitter (UART)

modules

H General-purpose input/output (GPIO) module

J The OMAP5912 also adds these shared peripherals:

H Eight general purpose timers

H Serial port interface (SPI)

H I2C master/slave interface

H Extra McBSP

H Multimedia card/secure digital interface (MMC/SDIO)

H 32-KHz synchronization counter

This document describes all of the DSP module components listed above. The
DSP subsystem peripherals are described in separate documents.

DSP Subsystem18 SPRU890A

Digital Signal Processor Subsystem Overview

1.3 Differences Between the OMAP5910 and OMAP5912 DSP

Subsystems

The OMAP5910 and OMAP5912 DSP subsystems are very similar. The
difference between the subsystems lies in the mix of the MPU/DSP shared
peripherals.

1.4 Functional Block Diagrams

Figure 1 and Figure 2 show functional block diagrams of the OMAP5910 and
OMAP5912 DSP subsystems.

Figure 1. OMAP5910 DSP Subsystem and Modules

DSP Subsystem and Interfaces

DSP private

peripherals

Timers

Watchdog

timer

Interrupt
handlers

Interrupt
interface

DSP private

peripheral bus

DSP public

peripheral bus

DSP public
peripherals

ROM,

SRAM,

Flash,

SBFlash

SDRAM

Endianess

conversion

DSP

MMU

controller

On-chip

SRAM

Traffic

EMIF

I-Cache

DARAM

SARAM

DSP Module

Internal

memory

buses

Memory

I/F

Configuration

DMA

(EMIF)
(DARAM)
(SARAM)

(MPUI)

(TIPB)

MPUI port

HWA

TMS320C55x

DSP core

Shared

TIPB

bridge

Private

TIPB

bridge

Pseudo

dynamic

sharing

MPU/DSP shared

peripherals

Mailbox

GPIO I/F

UART1,2,3

Static UART

sharing switch

16

16

Endianess conversion

MPU
subsystem

System

DMA

MPUI

MPU

MPU public
peripheral
bus

MPU public
TIPB bridge

McBSP1

McBSP3

MCSI2

MCSI1

19DSP SubsystemSPRU890A

Digital Signal Processor Subsystem Overview

Figure 2. OMAP5912 DSP Subsystem and Modules

DSP Subsystem and Interfaces

DSP Module

Internal

memory

buses

Memory

I/F

Configuration

DMA

(EMIF)
(DARAM)
(SARAM)

(MPUI)

(TIPB)

MPUI port

HWA

TMS320C55x

DSP core

Shared

TIPB

bridge

Pseudo

dynamic

sharing

ROM,

SRAM,

Flash,

SBFlash

SDRAM

Endianess
conversion

DSP

MMU

Traffic

controller

On-chip

SRAM

EMIF

I-Cache

DARAM

SARAM

Private

TIPB

bridge

DSP private

peripherals

Timers

Watchdog

timer

Interrupt
handlers

Interrupt

interface

DSP private

peripheral bus

DSP public

peripheral bus

MPU/DSP shared

peripherals

Mailbox

MPU/DSP static

shared

8xGPTIMERS

SPI

UART1,2,3

I2C

MMCSDIO2

McBSP2

MPU/DSP

Dynamic shared

GPIO1,2,3,4

32-KHz synchro timer

16

16

DSP public
peripherals

Endianess conversion

MPU
subsystem

System

DMA

MPUI

MPU

MPU public
peripheral
bus

MPU public
TIPB bridge

McBSP1

McBSP3

MCSI2

MCSI1

DSP Subsystem20 SPRU890A

2 C55x DSP Core Overview

The DSP subsystem is based on the TMS320C55x DSP generation processor
core. This section is intended to give a mere overview of the C55x DSP core.
For detailed information, see the TMS320C55x DSP CPU Reference Guide
(SPRU371).

2.1 DSP Core Features

Features of the high-performance, low-power DSP core include:

- Advanced multiple-bus architecture with one internal program memory

bus and five internal data buses (three dedicated to reads and two
dedicated to writes)

- Unified program/data memory architecture

- Dual 17-bit x 17-bit multipliers coupled to 40-bit dedicated adders for

non-pipelined single-cycle multiply accumulate (MAC) operations

- Two address generators with eight auxiliary registers and two auxiliary

register arithmetic units

C55x DSP Core Overview

- 8M x 16 bits (16M bytes) of total addressable memory space

- Single-instruction repeat or block repeat operations for program code

- Conditional execution

- Seven-stage pipeline for high instruction throughput

- Instruction buffer unit that loads, parses, queues, and decodes

instructions to decouple the program fetch function from the pipeline

- Program flow unit that coordinates program actions among multiple

parallel DSP core functional units

- Address data flow unit that provides data address generation and includes

a 16-bit arithmetic unit capable of performing arithmetical, logical, shift,
and saturation operations

- Data computation unit containing the primary computation units of the

DSP core, including a 40-bit arithmetic logic unit, two MAC units, and a
shifter

- Software-programmable idle domains that provide configurable

low-power modes

- Automatic power management

21DSP SubsystemSPRU890A

C55x DSP Core Overview

2.2 Introduction to the DSP Core

The DSP core supports an internal bus structure composed of one program
bus, three data read buses, two data write buses, and additional buses
dedicated to peripheral and DMA controller activity. These buses provide the
ability to perform up to three data reads and two data writes in a single cycle.

The DSP core provides two multiply-accumulate (MAC) units, each capable
of 17-bit x 17-bit multiplication in a single cycle. A central 40-bit arithmetic/logic
unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under
instruction set control, providing the ability to optimize parallel activity and
power consumption. These resources are managed in the address unit (AU)
and data unit (DU) of the DSP core.

The DSP core supports a variable byte width instruction set for improved code
density. The instruction unit (IU) performs 32-bit program fetches from internal
or DSP external memory and queues instructions for the program unit (PU).
The program unit decodes the instructions, directs tasks to AU and DU
resources, and manages the fully protected pipeline. Predictive branching
capability avoids pipeline flushes on execution of conditional instructions.

Figure 3 shows a conceptual block diagram of the DSP core. Detailed
information on each of the buses and units represented in this figure are given
in the TMS320C55x DSP CPU Reference Guide (SPRU371).

DSP Subsystem22 SPRU890A

Figure 3. DSP Core Diagram

C55x DSP Core Overview

Data-read data buses BB, CB, DB (each 16 bits)

Data-read address buses BAB, CAB, DAB (each 23 bits)

Program-read data bus PB (32 bits)

Program-read address bus PAB (24 bits)

External data

buses

External

program buses

Memory

interface unit

Other useful documents include:

- TMS320C55x DSP Mnemonic Instruction Set Reference Guide

- TMS320C55x Programmer’s Guide (SPRU376): Describes ways to

CPU

Instruction

buffer unit

(I unit)

Data-write data buses EB, FB (each 16 bits)

Data-write address buses EAB, FAB (each 23 bits)

Program
flow unit

(P unit)

Address-data

flow unit

(A unit)

Data

computation

unit

(D unit)

(SPRU374): Describes the mnemonic instructions individually. It also
includes a summary of the instruction set, a list of the instruction opcodes,
and a cross-reference to the algebraic instruction set.

optimize C and assembly code for the TMS320C55x DSPs and explains
how to write code that uses the special features and instructions of the
DSP.

- TMS320C55x Optimizing C Compiler User’s Guide (SPRU281):

Describes the TMS320C55x C Compiler. This C compiler accepts ANSI
standard C source code and produces assembly language source code
for TMS320C55x devices.

23DSP SubsystemSPRU890A

C55x DSP Core Overview

TMS320C55x Assembly Language Tools User’s Guide (SPRU280):

-

Describes the assembly language tools (assembler, linker, and other tools
used to develop assembly language code), assembler directives, macros,
common object file format, and symbolic debugging directives for
TMS320C55x devices.

2.3 Introduction to the Hardware Accelerators

Three powerful C55x hardware accelerator modules assist the DSP core in
implementing algorithms that are commonly used in video compression
applications such as MPEG4 encoders/decoders. These accelerators allow
implementation of such algorithms using fewer DSP instruction cycles and
dissipating less power than if the DSP core were operating alone. The
hardware accelerators are utilized via functions from the TMS320C55x
Image/Video Processing Library available from Texas Instruments.

The Image/Video Processing Library implements many useful functions
utilizing the hardware accelerators, including:

- Forward and Inverse Discrete Cosine Transform (DCT) (used for video

compression/decompression)

- Motion Estimation (used for compression standards such as MPEG video

encoding and H.26x encoding)

- Pixel Interpolation (enabling high-performance fractal pixel motion

estimation)

- Quantization/Dequantization (useful for JPEG, MPEG, H.26x

encoding/decoding)

- Flexible 1D/2D Wavelet Processing (useful for JPEG2000, MPEG4, and

other compression standards)

- Boundary and Perimeter Computation (useful for Machine Vision

applications)

- Image Threshold and Histogram Computations (useful for various Image

Analysis applications)

More information on the C55x Image/Video Processing Library can be found
in the TMS320C55x Image/Video Processing Library Programmer’s

Reference (SPRU037).

DSP Subsystem24 SPRU890A

C55x DSP Core Overview

There are three hardware accelerators included along with the C55x DSP
core:

- DCT/IDCT Accelerator: This hardware accelerator implements Forward

and Inverse DCT algorithms. These DCT/IDCT algorithms can enable a
wide range of video compression standards including JPEG
Encode/Decode, MPEG Video Encode/Decode, and H.26x
Encode/Decode.

- Motion Estimation Accelerator: This hardware accelerator implements a

high-performance motion estimation algorithm, enabling MPEG Video
encoder or H.26x encoder applications. Motion estimation is typically one
of the most computation-intensive operations in video-encoding systems.

- Pixel Interpolation Accelerator: This hardware accelerator enables

high-performance pixel-interpolation algorithms, which allow for powerful
fractal pixel motion estimation when used in conjunction with the Motion
Estimation Accelerator. Such algorithms provide significant improvement
to video-encoding applications.

Detailed information on the C55x Hardware Accelerators can be found in the

TMS320C55x Hardware Extensions for Image/Video Applications
Programmer’s Reference (SPRU098).

25DSP SubsystemSPRU890A

DSP Subsystem Memory

3 DSP Subsystem Memory

The DSP subsystem requires access to three different types of memory:
program memory, data memory, and I/O memory. The DSP subsystem
architecture uses a unified program and data memory space composed of
memory internal and external to the DSP subsystem. Internal memory is made
up of tightly coupled memory blocks, whereas DSP external memory is
mapped to OMAP system memory. The DSP subsystem architecture provides
access to a maximum of 8M words (16M bytes) of program/data memory
space.

The DSP subsystem I/O memory space is separate from the data/program
memory space. The I/O space includes the configuration and data registers
for all peripherals accessible by the DSP subsystem.

3.1 Internal Memory Space

The DSP subsystem memory consists of four types of tightly coupled
memories which provide the DSP core with maximum efficiency.

- Dual-access RAM (DARAM)

The DARAM memory consists of 8 blocks of 8K bytes each. The DARAM
(64K bytes) can support up to two memory accesses into each RAM block
in one DSP core clock cycle. Accesses can be made from any internal
data, program, or DMA bus.

- Single-access RAM (SARAM)

The SARAM memory consists of 12 blocks of 8K bytes each. The SARAM
(96K bytes) can support one memory access into each RAM block in one
DSP core clock cycle. This access can be a 32-bit value. Accesses can be
made from any internal data, program, or DMA bus.

- Programmable dynamic ROM (PDROM)

The PDROM memory consists of 1 block of 32K bytes. The programmable
dynamic ROM (32K bytes) can support one memory read in one DSP core
clock cycle. This access can be a 32-bit value. Accesses can be made
from any internal data read or program bus.

The PDROM contains a program called a bootloader, which is executed by
the DSP core when it is taken out of reset. Depending on the boot mode
selected, the DSP core will either branch to an internal or DSP external
memory address, or go into idle. Note that the memory at the destination
address must be initialized with valid code before the bootloader is
executed. Selecting boot mode 000b will disable the PDROM. The MPU
core specifies the boot mode through the DSP_BOOT_CONFIG register.
For more information on the DSP subsystem bootloader and the
DSP_BOOT_CONFIG register, see section 12.4.

DSP Subsystem26 SPRU890A

Configurable I-Cache structure

-

The DSP instruction cache (I-Cache) module is a special-purpose, tightly
coupled, RAM-based program memory. The module is designed to
significantly improve DSP core performance by buffering the instructions
most recently fetched from DSP external memory. The entire external
program memory space is cacheable. Section 4 describes the I-Cache in
more detail.

Figure 4 shows the connections between the internal memory blocks and the
buses of the DSP core.

Figure 4. Internal Memory Connections in the DSP Subsystem

12 blocks of 8K bytes

8 blocks of 8K bytes

1 block of 32K bytes

DSP Subsystem Memory

P buses

B buses

C buses

D buses

E buses

F bus

PDROM

SARAM

DARAM

To

external

memory

I/F

A

D

The DSP core uses the six sets of buses to simultaneously fetch up to 32 bits
of program code and to read up to 48 bits of data from memory (or to write up
to 32 bits of data to memory). To achieve maximum performance from the
architecture, pay close attention to placement of code and data structures
within the on-chip memory resources. For more details, see the TMS320C55x
Programmer’s Guide (SPRU376).

27DSP SubsystemSPRU890A

DSP Subsystem Memory

3.2 DSP External Memory Space

The DSP core and DMA controller use the external memory interface (EMIF)
to access the DSP external memory. External memory for the DSP subsystem
ranges from byte address 0x02 8000 to 0xFF 8000 if the internal PDROM is
enabled, or to 0xFF FFFF if the PDROM is not enabled. See Figure 18 for more
details.

Note:

The term DSP external memory refers to memory outside of the DSP
subsystem internal memory space. This includes program addresses in the
range of 0x02 8000 to 0xFF 8000 if the internal PDROM is enabled, or to
0xFF FFFF if the PDROM is not enabled.

All DSP external memory access requests are passed through the DSP
memory management unit (MMU). If this unit is enabled and configured by the
MPU core, it translates the DSP external memory access request address,
also called a virtual address, into a system memory address, also called a
physical address, that is then passed to the traffic controller. The traffic
controller completes the memory access through one of the three system
memory interfaces: internal memory (IMIF), slow external memory (EMIFS),
or fast external memory (EMIFF).

If the MMU is not enabled, then the access request is passed directly to the
system traffic controller. In this case, the DSP virtual address is mapped to the
first 16M bytes of chip select space 0 (CS0) of the system memory.

3.3 I/O Memory Space

The DSP subsystem I/O space is a separate address space from the
data/program memory space. Configuration and data registers for all
peripherals reside in the DSP subsystem I/O space, which consists of
64K-word addresses. Each peripheral maps into a 1K-word section of I/O
memory.

OMAP devices include sets of peripherals grouped into three main categories:
shared, public, or private.

- DSP/MPU shared peripherals are connected to both the MPU public

peripheral bus and the DSP public peripheral bus. Connections are routed
through a TI peripheral bus switch, which must be configured to allow MPU
domain or DSP domain access. Some shared peripherals have
permanent connections to both public peripheral buses, although read
and write accesses to each peripheral register may differ.

DSP Subsystem28 SPRU890A

DSP Subsystem Memory

DSP public peripherals are connected to the DSP public peripheral bus

-

and are directly accessible by the DSP core and DSP DMA. These
peripherals may also be accessed by the MPU core and system DMA
controller via the MPUI.

- DSP private peripherals are on the DSP private peripheral bus, and thus,

can only be accessed by the DSP core.

To read or write to these registers, you must access the DSP subsystem I/O
space either through C language constructs or, in the case of
assembly-language code, by using a special instruction qualifier called the
memory-mapped register access qualifier. For more details about this
qualifier, see TMS320C55x DSP Mnemonic Instruction Set Reference Guide
(SPRU374).

Note:

Byte access to I/O space is not supported.

The TI peripheral bus bridges manage accesses to the I/O memory space via
two peripheral buses: a private TI peripheral bus and a public TI peripheral
bus. Section 8 describes the TI peripheral bus bridges and their buses.

3.4 Memory Maps

Table 1 shows the high-level program/data memory map for the DSP
subsystem. DSP core data accesses utilize 16-bit word addresses, while DSP
core program fetches utilize byte addressing. DSP DMA data fetches always
use byte addresses.

Table 1. OMAP5910/5912 DSP Subsystem Global Memory Map

Byte Address Range Word Address Range Internal Memory DSP External

Memory

0x00 0000-0x00 FFFF 0x00 0000-0x00 7FFF DARAM 64K bytes

0x01 0000-0x02 7FFF 0x00 8000-0x01 3FFF SARAM 96K bytes

0x02 8000-0xFF 7FFF 0x01 4000-0x7F BFFF Managed by DSP

MMU

0xFF 8000-0xFF FFFF

†

This space could be DSP external memory or internal shared system memory, depending on the DSP MMU configuration.

0x7F C000-0x7F FFFF PDROM

(MPNMC = 0)

Managed by DSP
MMU (MPNMC = 1)

The I/O memory map varies from device to device, due to the different peripheral
mixes. For a detailed I/O memory map, see the device-specific data manual.

†

29DSP SubsystemSPRU890A

Instruction Cache

4 Instruction Cache

4.1 Introduction

On the OMAP5912/10 applications processors, instructions for the C55x DSP
core can reside in internal memory or in DSP external memory. When
instructions reside in DSP external memory, the instruction cache (I-Cache)
can improve the overall system performance by buffering the most recent
instructions accessed by the DSP core.

Note:

The term DSP external memory refers to memory outside of the DSP
subsystem internal memory space. This includes program addresses in the
range of 0x02 8000 to 0xFF 8000 if the internal PDROM is enabled, or to
0xFF FFFF if the PDROM is not enabled.

4.1.1 Features

For storing instructions, the I-Cache contains:

- One 2-way cache. The 2-way cache uses 2-way set associative mapping

and holds up to 16K bytes: 512 sets, two lines per set, four 32-bit words
per line. In the 2-way cache, each line is identified by a unique tag.

- Two RAM sets (1 and 2). These two banks of RAM are available to hold

blocks of code. Each RAM set holds up to 4K bytes: 256 lines, four 32-bit
words per line. Each RAM set uses a single tag to identify a continuous
range of memory addresses that is represented in the RAM set. Before
enabling the I-Cache, configure the I-Cache to use zero, one, or both RAM
sets.

The DSP core status register, ST3_55, contains three cache control bits for
enabling, freezing, and flushing the I-Cache (see section 4.2.4). To configure
the I-Cache and check its status, the DSP core accesses a set of registers in
the I-Cache (see section 4.6).

4.1.2 Functional Block Diagram

Figure 5 shows how the I-Cache fits into the DSP subsystem.

DSP Subsystem30 SPRU890A