Texas Instruments MSP430P325IFN, MSP430P325IPG, MSP-EVK430B320, MSP430P325IPM, MSP-STK430B320 Datasheet
MSP430P325
MIXED SIGNAL MICROCONTROLLER
SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000
D
Low Supply Voltage Range, 2.7 V – 5.5 V
D
Low Operation Current, 3 mA at 1 MHz,
3 V
D
Ultralow Power Consumption (Standby
Mode Down to 0.1 mA)
D
Five Power-Saving Modes
D
Wakeup From Standby Mode in 6 ms
D
16-Bit RISC Architecture, 300 ns Instruction
Cycle Time
D
Single Common 32 kHz Crystal, Internal
System Clock up to 3.3 MHz
D
Integrated LCD Driver for up to 84
Segments
description
The T exas Instruments MSP430 is an ultralow-power mixed-signal microcontroller family consisting of several
devices which feature different sets of modules targeted to various applications. The microcontroller is designed
to be battery operated for an extended application lifetime. With 16-bit RISC architecture, 16-bit integrated
registers on the CPU, and a constant generator, the MSP430 achieves maximum code ef ficiency . The digitallycontrolled oscillator, together with the frequency-locked-loop (FLL), provides a wakeup from a low-power mode
to active mode in less than 6 ms.
D
D
D
D
D
D
PG Package
(TOP VIEW)
Integrated 12+2 Bit A/D Converter
Family Members Include:
– MSP430P325, 16KB OTP, 512 Byte RAM
EPROM Version Available for Prototyping:
PMS430E325
Serial Onboard Programming
Programmable Code Protection by Security
Fuse
Avaliable in 64 Pin Quad Flatpack (QFP),
68 Pin Plastic J-Leaded Chip Carrier
(PLCC), 68 Pin J-Leaded Ceramic Chip
Carrier (JLCC) Package (EPROM Version)
SSAVSS
A1A0XBUF
DV
64 636261605958575655545352
CC
CC
CC
A2
A3
A4
A5
Xin
CIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
202122 23 242526 272829303132
P0.3
P0.4
P0.2/TXD
AV
DV
SV
Rext
Xout/TCLK
TP0.0
TP0.1
TP0.2
TP0.3
TP0.4
TP0.5
P0.0
P0.1/RXD
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
P0.5
RST/NMI
P0.6
P0.7
TCK
R33
TMS
TDI/VPP
R23
R13
TDO/TDI
COM3
COM2
S0
S1
R03
COM1
51
COM0
50
S20/O20/CMPI
49
S19/O19
48
S18/O18
47
S17/O17
46
S16/O16
45
S15/O15
44
S14/O14
43
S13/O13
42
S12/O12
41
S1 1/O11
40
S10/O10
39
S9/O9
38
S8/O8
37
S7/O7
36
S6/O6
35
S5/O5
34
S4/O4
33
S3/O3
S2/O2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 2000, Texas Instruments Incorporated
1
MSP430P325
40°C to 85°C
MSP430P325IPG
MSP430P325IPM
MSP430P325IFN
25°C
PMS430E325FZ
MIXED SIGNAL MICROCONTROLLER
SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000
description (continued)
Typical applications include sensor systems that capture analog signals, convert them to digital values, and then
process the data and display them or transmit them to a host system. The MSP430x32x offers an integrated
12+2 bit A/D converter with six multiplexed inputs.
AVAILABLE OPTIONS
PACKAGED DEVICES
T
A
°
–
°
°
functional block diagram
PLASTIC
64-PIN QFP
(PG)
PLASTIC
64-PIN QFP
(PM)
— — —
PLASTIC
68-PIN PLCC
(FN)
CERAMIC
68-PIN JLCC
(FZ)
—
TDI/VPP
TDO/TDI
TMS
TCK
Bus
Conv
RST/NMI
Power-on-
Reset
MAB, 4 Bit
MCB
MDB, 8 Bit
Timer/Port
Applications:
A/D Conv.
Timer, O/P
6
8 b Timer/
Counter
Serial Protocol
Support
Basic
Timer1
f
CMPI
LCD
TXD
RXD
8 I/O’s, All With
1, 2, 3, 4 MUX
XIN Xout/TCLK XBUF P0.0 P0.7
Oscillator
FLL
System Clock
CPU
Incl. 16 Reg.
Test
JTAG
ACLK
MCLK
MAB, 16 Bit
MDB, 16 Bit
8/16 kB ROM
16 kB OTP
’C’: ROM
’P’: OTP
ADC
12 + 2 Bit
6 Channels
Current S.
6
256/512 B
RAM
Watchdog
Timer
15/16 Bit
I/O Port
Interr. Cap.
3 Int. Vectors
LCD
84 Segments
Com0–3
S0–19/O2–19
S20/O20CMPI
2
A0–5
SVCC
Rext
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TP0.0–5
CIN
R33 R13
R23
R03
I/O
DESCRIPTION
MIXED SIGNAL MICROCONTROLLER
SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000
Terminal Functions
TERMINAL
NAME NO.
AV
CC
AV
SS
A0 61 I Analog-to-digital converter input port 0 or digital input port 0
A1 62 I Analog-to-digital converter input port 1 or digital input port 1
A2–A5 5–8 I Analog-to-digital converter inputs ports 2–5 or digital inputs ports 2–5
CIN 11 I Input used as enable of counter TPCNT1 – Timer/Port
COM0–3 51–54 O Common outputs, used for LCD backplanes – LCD
DV
CC
DV
SS
P0.0 18 I/O General-purpose digital I/O
P0.1/RXD 19 I/O General-purpose digital I/O, receive digital input port, 8-Bit Timer/Counter
P0.2/TXD 20 I/O General-purpose digital I/O, transmit data output port, 8-Bit Timer/Counter
P0.3–P0.7 21–25 I/O Five general-purpose digital I/Os, bit 3 to bit 7
Rext 4 I Programming resistor input of internal current source
RST/NMI 59 I Reset input or non-maskable interrupt input
R03 29 I Input of fourth positive analog LCD level (V4) – LCD
R13 28 I Input of third positive analog LCD level (V3) – LCD
R23 27 I Input of second positive analog LCD level (V2) – LCD
R33 26 O Output of first positive analog LCD level (V1) – LCD
SV
CC
S0 30 O Segment line S0 – LCD
S1 31 O Segment line S1 – LCD
S2–S5/O2–O5 32–35 O Segment lines S2 to S5 or digital output ports O2–O5, group 1 – LCD
S20/O20/CMPI 50 I/O Segment line S20 can be used as comparator input port CMPI – Timer/Port
S6–S9/O6–O9 36–39 O Segment lines S6 to S9 or digital output ports O6–O9, group 2 – LCD
S10–S13/O10–O13 40–43 O Segment lines S10 to S13 or digital output ports O10–O13, group 3 – LCD
S14–S17/O14–O17 44–47 O Segment lines S14 to S17 or digital output ports O14 to O17, group 4 – LCD
S18-S19/O18-O19 48, 49 O Segment lines S18 and S19 or digital output port O18 and O19, group 5 – LCD
TCK 58 I Test clock, clock input terminal for device programming and test
TDO/TDI 55 I/O Test data output, data output terminal or data input during programming
TDI/VPP 56 I Test data input, data input terminal or input of programming voltage
TMS 57 I Test mode select, input terminal for device programming and test
TP0.0 12 O General-purpose 3-state digital output port, bit 0 – Timer/Port
TP0.1 13 O General-purpose 3-state digital output port, bit 1 – Timer/Port
TP0.2 14 O General-purpose 3-state digital output port, bit 2 – Timer/Port
TP0.3 15 O General-purpose 3-state digital output port, bit 3 – Timer/Port
TP0.4 16 O General-purpose 3-state digital output port, bit 4 – Timer/Port
TP0.5 17 I/O General-purpose digital input/output port, bit 5 – Timer/Port
XBUF 60 O Clock signal output of system clock MCLK or crystal clock ACLK
Xin 9 I Input terminal of crystal oscillator
Xout/TCLK 10 I/O Output terminal of crystal oscillator or test clock input
1 Positive analog supply voltage
63 Analog ground reference
2 Positive digital supply voltage
64 Digital ground reference
3 Switched AVCC to analog-to-digital converter
MSP430P325
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3
MSP430P325
MIXED SIGNAL MICROCONTROLLER
SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000
short-form description
processing unit
The processing unit is based on a consistent and orthogonally-designed CPU and instruction set. This design
structure results in a RISC-like architecture, highly transparent to the application development, and it is
distinguished by ease of programming. All operations other than program-flow instructions are consequently
performed as register operations in conjunction with seven addressing modes for source and four modes for
destination operand.
Program Counter
CPU
Sixteen registers are located inside the CPU,
providing reduced instruction execution time. This
reduces a register-register operation execution
time to one cycle of the processor frequency.
Four of the registers are reserved for special
use as a program counter, a stack pointer , a status
register, and a constant generator . The remaining
registers are available as general-purpose
registers.
Stack Pointer
Status Register
Constant Generator
General-Purpose Register
General-Purpose Register
PC/R0
SP/R1
SR/CG1/R2
CG2/R3
R4
R5
Peripherals are connected to the CPU using a
data address and control bus and can be handled
easily with all instructions for memory
General-Purpose Register R14
manipulation.
General-Purpose Register
instruction set
The instruction set for this register-register architecture provides a powerful and easy-to-use assembler
language. The instruction set consists of 51 instructions with three formats and seven addressing modes.
T able 1 provides a summation and example of the three types of instruction formats; the addressing modes are
listed in Table 2.
Table 1. Instruction Word Formats
Dual operands, source-destination e.g. ADD R4, R5 R4 + R5 → R5
Single operands, destination only e.g. CALL R8 PC → (TOS), R8 → PC
Relative jump, un-/conditional e.g. JNE Jump-on equal bit = 0
Each instruction that operates on word and byte data is identified by the suffix B.
Examples: Instructions for word operation Instructions for byte operation
MOV EDE, TONI MOV.B EDE, TONI
ADD #235h, &MEM ADD.B #35h, &MEM
PUSH R5 PUSH.B R5
SWPB R5 —
R15
4
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MSP430P325
MIXED SIGNAL MICROCONTROLLER
SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000
Table 2. Address Mode Descriptions
ADDRESS MODE s d SYNTAX EXAMPLE OPERATION
Register √ √ MOV Rs, Rd MOV R10, R11 R10 → R11
Indexed √ √ MOV X(Rn), Y(Rm) MOV 2(R5), 5(R6) M(2 + R5) → M(6 + R6)
Symbolic (PC relative) √ √ MOV EDE, TONI M(EDE) → M(TONI)
Absolute √ √ MOV &MEM, &TCDAT M(MEM) → M(TCDAT)
Indirect √ MOV @Rn, Y(Rm) MOV @R10, Tab(R6) M(R10) → M(Tab + R6)
Indirect autoincrement √ MOV @Rn+, RM MOV @R10+, R11 M(R10) → R11, R10 + 2 → R10
Immediate √ MOV #X, TONI MOV #45, TONI #45 → M(TONI)
NOTE: s = source d = destination
Computed branches (BR) and subroutine calls (CALL) instructions use the same addressing modes as the other
instructions. These addressing modes provide
calls. The full use of this programming capability permits a program structure different from conventional 8- and
16-bit controllers. For example, numerous routines can easily be designed to deal with pointers and stacks
instead of using flag type programs for flow control.
operation modes and interrupts
indirect
addressing, ideally suited for computed branches and
The MSP430 operating modes support various advanced requirements for ultralow power and ultralow energy
consumption. This is achieved by the intelligent management of the operations during the different module
operation modes and CPU states. The requirements are fully supported during interrupt event handling. An
interrupt event awakens the system from each of the various operating modes and returns with the RETI
instruction to the mode that was selected before the interrupt event. The clocks used are ACLK and MCLK.
ACLK is the crystal frequency and MCLK is a multiple of ACLK and is used as the system clock.
The software can configure five operating modes:
D
Active mode (AM). The CPU is enabled with different combinations of active peripheral modules.
D
Low power mode 0 (LPM0). The CPU is disabled, peripheral operation continues, ACLK and MCLK signals
are active, and loop control for MCLK is active.
D
Low power mode 1 (LPM1). The CPU is disabled, peripheral operation continues, ACLK and MCLK signals
are active, and loop control for MCLK is inactive.
D
Low power mode 2 (LPM2). The CPU is disabled, peripheral operation continues, ACLK signal is active,
and MCLK and loop control for MCLK are inactive.
D
Low power mode 3 (LPM3). The CPU is disabled, peripheral operation continues, ACLK signal is active,
MCLK and loop control for MCLK are inactive, and the dc generator for the digital controlled oscillator (DCO)
(³MCLK generator) is switched off.
D
Low power mode 4 (LPM4). The CPU is disabled, peripheral operation continues, ACLK signal is inactive
(crystal oscillator stopped), MCLK and loop control for MCLK are inactive, and the dc generator for the DCO
is switched off.
The special function registers (SFR) include module-enable bits that stop or enable the operation of the specific
peripheral module. All registers of the peripherals may be accessed if the operational function is stopped or
enabled. However, some peripheral current-saving functions are accessed through the state of local register
bits. An example is the enable/disable of the analog voltage generator in the LCD peripheral, which is turned
on or off using one register bit.
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5
MSP430P325
MIXED SIGNAL MICROCONTROLLER
SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000
operation modes and interrupts (continued)
The most general bits that influence current consumption and support fast turnon from low-power operating
modes are located in the status register (SR). Four of these bits control the CPU and the system clock generator:
SCG1, SCG0, OscOff, and CPUOff.
15 9 8 7 0
Reserved For Future
Enhancements
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the ROM with an address range of
0FFFFh-0FFE0h. The vector contains the 16-bit address of the appropriate interrupt handler instruction
sequence.
INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY
Power-up, external reset, watchdog
NMI, oscillator fault
Dedicated I/O P0.0 P0.0IFG Maskable 0FFFAh 13
Dedicated I/O P0.1 or 8-Bit Timer/Counter
RXD
Watchdog Timer WDTIFG Maskable 0FFF4h 10
ADC ADCIFG Maskable 0FFEAh 5
Timer/Port
Basic Timer1 BTIFG Maskable 0FFE2h 1
I/O port 0, P0.2–7
NOTES: 1. Multiple source flags
2. Timer/Port interrupt flags are located in the T/P registers
3. Non-maskable: neither the individual nor the general interrupt enable bit will disable an interrupt event.
4. (Non)-maskable: the individual interrupt enable bit can disable on interrupt event, but the general interrupt enable bit cannot.
V SCG1 SCG0 OscOff CPUOff GIE N Z C
rw-0
WDTIFG
NMIIFG (see Notes 1 and 3)
OFIFG (see Notes 1 and 4)
RC1FG, RC2FG, EN1FG
P0.27IFG (see Note 1)
(see Note1)
P0.1IFG Maskable 0FFF8h 12
(see Note 2)
Reset 0FFFEh 15, highest
Non-maskable,
(Non)-maskable
Maskable 0FFE8h 4
Maskable 0FFE0h 0, lowest
0FFFCh 14
0FFF6h 11
0FFF2h 9
0FFF0h 8
0FFEEh 7
0FFECh 6
0FFE6h 3
0FFE4h 2
6
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MSP430P325
MIXED SIGNAL MICROCONTROLLER
SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000
operation modes and interrupts (continued)
special function registers
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
that are not allocated to a functional purpose are not physically present in the device. Simple SW access is
provided with this arrangement.
interrupt enable 1 and 2
Address
0h
7654 0
321
P0IE.1 OFIE WDTIE
rw-0 rw-0 rw-0 rw-0
WDTIE: Watchdog Timer enable signal
OFIE: Oscillator fault enable signal
P0IE.0: Dedicated I/O P0.0
P0IE.1: P0.1 or 8-Bit Timer/Counter, RXD
Address
01h BTIE TPIE
7654 0
rw-0
321
rw-0
ADIE: A/D converter enable signal
TPIE: Timer/Port enable signal
BTIE: Basic Timer1 enable signal
interrupt flag register 1 and 2
Address
02h NMIIFG P0IFG.0
7654 0
rw-0 rw-1 rw-0
321
P0IFG.1 OFIFG WDTIFG
rw-0 rw-0
WDTIFG: Set on overflow or security key violation
or
Reset on VCC power on or reset condition at RST/NMI-pin
OFIFG: Flag set on oscillator fault
P0.0IFG: Dedicated I/O P0.0
P0.1IFG: P0.1 or 8-Bit Timer/Counter, RXD
NMIIFG: Signal at RST
/NMI-pin
P0IE.0
ADIE
rw-0
Address
03h BTIFG ADIFG
7654 0
rw
321
rw-0
BTIFG Basic Timer1 flag
ADFIG Analog-to-digital converter flag
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7
MSP430P325
MIXED SIGNAL MICROCONTROLLER
SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000
operation modes and interrupts (continued)
module enable register 1 and 2
Address
04h
Address
05h
Legend rw:
7654 0321
7654 0321
rw-0:
memory organization
Bit can be read and written.
Bit can be read and written. It is reset by PUC.
SFR bit not present in device.
MSP430P325
PMS430E325
FFFFh
FFE0h
FFDFh
C000h
Int. Vector
16 kB OTP
or
EPROM
03FFh
0200h
01FFh
0100h
00FFh
0010h
000Fh
0000h
512B RAM
16b Per.
8b Per.
SFR
8
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MSP430P325
MIXED SIGNAL MICROCONTROLLER
SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000
peripherals
Peripherals connect to the CPU through data, address, and control busses and can be handled easily with all
instructions for memory manipulation.
peripheral file map
PERIPHERALS WITH WORD ACCESS
Watchdog Watchdog Timer control WDTCTL 0120h
ADC Data register
Reserved
Control register
Input enable register
Input register
PERIPHERALS WITH BYTE ACCESS
EPROM EPROM control EPCTL 054h
Crystal buffer Crystal buffer control CBCTL 053h
System clock SCG frequency control
SCG frequency integrator
SCG frequency integrator
Timer/Port T imer/Port enable
Timer/Port data
Timer/Port counter2
Timer/Port counter1
Timer/Port control
8-Bit Timer/Counter 8-Bit Timer/Counter data
8-Bit Timer/Counter preload
8-Bit Timer/Counter control
Basic Timer1 Basic Timer counter2
Basic Timer counter1
Basic Timer control
LCD LCD memory 15
:
LCD memory 1
LCD control & mode
Port P0 Port P0 interrupt enable
Port P0 interrupt edge select
Port P0 interrupt flag
Port P0 direction
Port P0 output
Port P0 input
Special function SFR interrupt flag2
SFR interrupt flag1
SFR interrupt enable2
SFR interrupt enable1
ADAT
ACTL
AEN
AIN
SCFQCTL
SCFI1
SCFI0
TPE
TPD
TPCNT2
TPCNT1
TPCTL
TCDAT
TCPLD
TCCTL
BTCNT2
BTCNT1
BTCTL
LCDM15
:
LCDM1
LCDCTL
P0IE
P0IES
P0IFG
P0DIR
P0OUT
P0IN
IFG2
IFG1
IE2
IE1
0118h
0116h
0114h
o112h
0110h
052h
051h
050h
04Fh
04Eh
04Dh
04Ch
04Bh
044h
043h
042h
047h
046h
040h
03Fh
:
031h
030h
015h
014h
013h
012h
011h
010h
003h
002h
001h
000h
oscillator and system clock
Two clocks are used in the system, the system (master) clock (MCLK) and the auxiliary clock (ACLK). The MCLK
is a multiple of the ACLK. The ACLK runs with the crystal oscillator frequency . The special design of the oscillator
supports the feature of low current consumption and the use of a 32 768 Hz crystal. The crystal is connected
across two terminals without any other external components being required.
The oscillator starts after applying VCC, due to a reset of the control bit (OscOff) in the status register (SR). It
can be stopped by setting the OscOff bit to a 1. The enabled clock signals ACLK, ACLK/2, ACLK/4, or MCLK
are accessible for use by external devices at output terminal XBUF.
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9
MSP430P325
MIXED SIGNAL MICROCONTROLLER
SLAS164A – FEBRUARY 1998 – REVISED MARCH 2000
oscillator and system clock (continued)
The controller system clock has to operate with different requirements according to the application and system
conditions. Requirements include:
D
High frequency in order to react quickly to system hardware requests or events
D
Low frequency in order to minimize current consumption, EMI, etc.
D
Stable frequency for timer applications e.g. real-time clock (RTC)
D
Enable start-stop operation with a minimum of delay
These requirements cannot all be met with fast frequency high-Q crystals or with RC-type low-Q oscillators. The
compromise selected for the MSP430 uses a low-crystal frequency , which is multiplied to achieve the desired
nominal operating range:
f
(system)
The crystal frequency multiplication is achieved with a frequency locked loop (FLL) technique. The factor N is
set to 31 after a power-up clear condition. The FLL technique, in combination with a digital controlled oscillator
(DCO) provides immediate start-up capability together with long term crystal stability . The frequency variation
of the DCO with the FLL inactive is typically 330 ppm, which means that with a cycle time of 1 µs the maximum
possible variation is 0.33 ns. For more precise timing, the FLL can be used forcing longer cycle times, if the
previous cycle time was shorter than the selected one. This switching of cycle times makes it possible to meet
the chosen system frequency over a long period of time.
The start-up operation of the system clock depends on the previous machine state. During a power-up clear
(PUC), the DCO is reset to its lowest possible frequency. The control logic starts operation immediately after
recognition of PUC. Connect operation of the FLL control logic requires the presence of a stable crystal
oscillator.
digital I/O
One 8-Bit I/O port (Port0) is implemented. Six control registers give maximum flexibility of digital input/output
to the application:
D
All individual I/O bits are programmable independently.
D
Any combination of input, output, and interrupt conditions is possible.
D
Interrupt processing of external events is fully implemented for all eight bits of port P0.
D
Provides read/write access to all registers with all instructions
The six registers are:
= (N+1) × f
crystal)
(
D
Input register Contains information at the pins
D
Output register Contains output information
D
Direction register Controls direction
D
Interrupt flags Indicates if interrupt(s) are pending
D
Interrupt edge select Contains input signal change necessary for interrupt
D
Interrupt enable Contains interrupt enable pins
All six registers contain eight bits except for the interrupt flag register and the interrupt enable register. The two
LSBs of the interrupt flag and interrupt enable registers are located in the special functions register (SFR). Three
interrupt vectors are implemented, one for Port0.0, one for Port0.1, and one commonly used for any interrupt
event on Port0.2 to Port0.7. The Port0.1 and Port0.2 pin function is shared with the 8-Bit Timer/Counter.
10
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