Texas Instruments MSP50C614 User Manual

MSP50C614

Mixed-Signal Processor

User’s Guide

SPSU014

January 2000

Printed on Recycled Paper

IMPORTANT NOTICE

T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Copyright  2000, Texas Instruments Incorporated

About This Manual

This user’s guide gives information for the MSP50C61 mixed-signal proces­sor. This information includes a functional overview, a detailed architectural
description, device peripheral functional description, assembly language
instruction listing, code development tools, applications, customer informa­tion, and electrical characteristics (in data sheet). This document also contains
information for the MSP50C604 and MSP50C605, which are in the Product
Preview stage of development.

How to Use This Manual

This document contains the following chapters:

-

Preface

Read This First

Chapter 1 –Introduction to the MSP50C614

-

-

-

-

-

-

-

-

-

Notational Conventions

This document uses the following conventions.

-

Chapter 2 –MSP50C614 Architecture
Chapter 3 –Peripheral Functions
Chapter 4 –Assembly Language Instructions
Chapter 5 –Code Development Tools
Chapter 6 –Applications
Chapter 7 –Customer Information
Appendix A –MSP50C605 Preliminary Data
Appendix B –MSP50C604 Preliminary Data
Appendix C –MSP50C605 Data Sheet

Program listings, program examples, and interactive displays are shown
in a special typeface similar to a typewriter’s. Examples use a bold

Read This First

iii

Notational Conventions

version of the special typeface for emphasis; interactive displays use a
bold version of the special typeface to distinguish commands that you

enter from items that the system displays (such as prompts, command
output, error messages, etc.).

Here is a sample program listing:

0011 0005 0001 .field 1, 2
0012 0005 0003 .field 3, 4
0013 0005 0006 .field 6, 3
0014 0006 .even

Here is an example of a system prompt and a command that you might
enter:

C: csr –a /user/ti/simuboard/utilities

-

In syntax descriptions, the instruction, command, or directive is in a bold
typeface font and parameters are in an

italic typeface

. Portions of a syntax

that are in bold should be entered as shown; portions of a syntax that are

italics

in

describe the type of information that should be entered. Here is

an example of a directive syntax:

.asect ”

section name

”,

address

.asect is the directive. This directive has two parameters, indicated by

tion name

and

address

. When you use .asect, the first parameter must be
an actual section name, enclosed in double quotes; the second parameter
must be an address.

-

Square brackets ( [ and ] ) identify an optional parameter. If you use an
optional parameter, you specify the information within the brackets; you
don’t enter the brackets themselves. Here’s an example of an instruction
that has an optional parameter:

LALK

The LALK instruction has two parameters. The first parameter,

stant

16–bit constant [, shift]

, is required. The second parameter,

16-bit con-

shift

, is optional. As this syntax
shows, if you use the optional second parameter, you must precede it with
a comma.

Square brackets are also used as part of the pathname specification for
VMS pathnames; in this case, the brackets are actually part of the path­name (they are not optional).

-

Braces ( { and } ) indicate a list. The symbol | (read as or) separates items
within the list. Here’s an example of a list:

{ * | *+ | *– }

sec-

This provides three choices: *, *+, or *–.

iv

Information About Cautions and Warnings

Unless the list is enclosed in square brackets, you must choose one item
from the list.

-

Some directives can have a varying number of parameters. For example,
the .byte directive can have up to 100 parameters. The syntax for this di­rective is:

.byte

value1 [, ... , valuen]

This syntax shows that .byte must have at least one value parameter, but
you have the option of supplying additional value parameters, separated
by commas.

Information About Cautions and Warnings

This book may contain cautions and warnings.

This is an example of a caution statement.
A caution statement describes a situation that could potentially

damage your software or equipment.

This is an example of a warning statement.
A warning statement describes a situation that could potentially

cause harm to you.

The information in a caution or a warning is provided for your protection.
Please read each caution and warning carefully.

Trademarks

Intel, i486, and Pentium are trademarks of Intel Corporation.
Microsoft, Windows, Windows 95, and Windows 98 are registered trademarks of Microsoft Corporation.

Read This First

v

vi

Contents

Contents

1 Introduction to the MSP50C614 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1 Features of the C614 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 Applications 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 Development Device: MSP50P614 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4 Functional Description 1-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.5 C605 and C604 (Preliminary Information) 1-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.6 Terminal Assignments and Signal Descriptions 1-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 MSP50C614 Architecture 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 Architecture Overview 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 Computation Unit 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.1 Multiplier 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.2 Arithmetic Logic Unit 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3 Data Memory Address Unit 2-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.1 RAM Configuration 2-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.2 Data Memory Addressing Modes 2-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4 Program Counter Unit 2-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5 Bit Logic Unit 2-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6 Memory Organization: RAM and ROM 2-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6.1 Memory Map 2-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6.2 Peripheral Communications (Ports) 2-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6.3 Interrupt Vectors 2-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6.4 ROM Code Security 2-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6.5 Macro Call Vectors 2-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7 Interrupt Logic 2-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.8 Timer Registers 2-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.9 Clock Control 2-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.9.1 Oscillator Options 2-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.9.2 PLL Performance 2-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.9.3 Clock Speed Control Register 2-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.9.4 RTO Oscillator Trim Adjustment 2-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.10 Execution Timing 2-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11 Reduced Power Modes 2-34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 Peripheral Functions 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1 I/O 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

vii

Contents

3.1.1 General-Purpose I/O Ports 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.2 Dedicated Input Port F 3-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.3 Dedicated Output Port G 3-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.4 Branch on D Port 3-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.5 Internal and External Interrupts 3-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2 Digital-to-Analog Converter (DAC) 3-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.1 Pulse-Density Modulation Rate 3-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.2 DAC Control and Data Registers 3-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.3 PDM Clock Divider 3-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3 Comparator 3-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4 Interrupt/General Control Register 3-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5 Hardware Initialization States 3-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 Assembly Language Instructions 4-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1 Introduction 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2 System Registers 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.1 Multiplier Register (MR) 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.2 Shift Value Register (SV) 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.3 Data Pointer Register (DP) 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.4 Program Counter (PC) 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.5 Top of Stack, (TOS) 4-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.6 Product High Register (PH) 4-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.7 Product Low Register (PL) 4-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.8 Accumulators (AC0–AC31) 4-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.9 Accumulator Pointers (AP0–AP3) 4-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.10 Indirect Register (R0–R7) 4-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.11 String Register (STR) 4-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.12 Status Register (STAT) 4-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3 Instruction Syntax and Addressing Modes 4-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3.1 MSP50P614/MSP50C614 Instruction Syntax 4-8. . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3.2 Addressing Modes 4-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3.3 Immediate Addressing 4-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3.4 Direct Addressing 4-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3.5 Indirect Addressing 4-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3.6 Relative Addressing 4-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3.7 Flag Addressing 4-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3.8 Tag/Flag Bits 4-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.4 Instruction Classification 4-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.4.2 Class 2 Instructions: Accumulator and Constant Reference 4-28. . . . . . . . . . . . . .

4.4.3 Class 3 Instruction: Accumulator Reference 4-30. . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.4.4 Class 4 Instructions: Address Register and Memory Reference 4-34. . . . . . . . . . .

4.4.5 Class 5 Instructions: Memory Reference 4-36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.4.6 Class 6 Instructions: Port and Memory Reference 4-38. . . . . . . . . . . . . . . . . . . . . .

4.4.7 Class 7 Instructions: Program Control 4-39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Contents

4.4.8 Class 8 Instructions: Logic and Bit 4-41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.4.9 Class 9 Instructions: Miscellaneous 4-42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.5 Bit, Byte, Word and String Addressing 4-44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.6 MSP50P614/MSP50C614 Computational Modes 4-49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.7 Hardware Loop Instructions 4-53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.8 String Instructions 4-55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.9 Lookup Instructions 4-57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.10 Input/Output Instructions 4-59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.11 Special Filter Instructions 4-59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.12 Conditionals 4-69. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.13 Legend 4-70. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.14 Individual Instruction Descriptions 4-74. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.15 Instruction Set Encoding 4-187. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.16 Instruction Set Summary 4-196. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5 Code Development Tools 5-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.1 Introduction 5-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2 MSP50C6xx Software Development Tool 5-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3 Requirements 5-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.4 Hardware Installation 5-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.5 Software Installation 5-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.6 Software Emulator 5-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.6.1 The Open Screen 5-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.6.2 Projects 5-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.6.3 Description of Windows 5-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.6.4 Debugging a Program 5-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.6.5 Initializing Chip 5-27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.6.6 Emulator Options 5-28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.6.7 Emulator Online Help System 5-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.6.8 Known Differences, Incompatibilities, Restrictions 5-32. . . . . . . . . . . . . . . . . . . . . . .

5.7 Assembler 5-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.7.1 Assembler DLL 5-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.7.2 Assembler Directives 5-34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.8 Linker 5-38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.9 C–– Compiler 5-39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.9.1 Foreword 5-40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.9.2 Variable Types 5-41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.9.3 External References 5-41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.9.4 C– – Directives 5-42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.9.5 Include Files 5-44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.9.6 Function Prototypes and Declarations 5-45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.9.7 Initializations 5-45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.9.8 RAM Usage 5-45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.9.9 Variable Types 5-45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents

ix

Contents

5.9.10 String Functions 5-45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.9.11 Constant Functions 5-47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.10 Implementation Details 5-48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.10.1 Comparisons 5-48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.10.2 Division 5-50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.10.3 Function Calls 5-50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.10.4 Programming Example 5-51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.10.5 Programming Example, C – With Assembly Routines 5-53. . . . . . . . . . . . . . . . . . .

5.11 Beware of Stack Corruption 5-67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.12 Reported Bugs With Code Development Tool 5-67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6 Applications 6-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.1 Application Circuits 6-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2 MSP50C614/MSP50P614 Initialization Codes 6-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2.1 File init.asm 6-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.3 Texas Instruments C614 Synthesis Code 6-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.3.1 Memory Overlay 6-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.4 ROM Usage With Respect to Various Synthesis Algorithms 6-14. . . . . . . . . . . . . . . . . . . . .

7 Customer Information 7-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.1 Mechanical Information 7-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.1.1 Die Bond-Out Coordinates 7-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.1.2 Package Information 7-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2 Customer Information Fields in the ROM 7-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.3 Speech Development Cycle 7-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.4 Device Production Sequence 7-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.5 Ordering Information 7-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.6 New Product Release Forms 7-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A MSP50C605 Preliminary Data A-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A.1 Introduction A-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A.2 Features A-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A.3 Architecture A-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A.3.1 RAM A-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A.3.2 ROM A-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A.3.3 I/O Pins A-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B MSP50C604 Preliminary Data B-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B.1 Introduction B-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B.2 Features B-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B.3 Architecture B-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B.3.1 RAM B-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B.3.2 ROM B-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B.3.3 I/O Pins B-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B.3.4 Slave Mode Operation B-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

x

Contents

B.3.5 Host Write Sequence B-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B.3.6 Host Read Sequence B-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B.3.7 Interrupts B-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B.4 Packaging B-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C MSP50C605 Data Sheet C-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C.1 MSP50C605 Data Sheet C-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents

xi

Figures

Figures

1–1 Functional Block Diagram for the C614 1-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1–2 Oscillator and PLL Connection 1-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1–3 RESET Circuit 1-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1–4 MSP50C614 100 Pin PJM PLastic Package Pinout 1-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1–5 120 Pin Grid Array Package for the Development Device, P614 1-13. . . . . . . . . . . . . . . . . . . .

2–1 MSP50C614 Core Processor Block Diagram 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–2 Computational Unit Block Diagram 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–3 Overview of the Multiplier Unit Operation 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–4 Overview of the Arithmetic Logic Unit 2-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–5 Overview of the Arithmetic Logic Unit 2-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–6 Data Memory Address Unit 2-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–7 C614 Memory Map (not drawn to scale) 2-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–8 Interrupt Initialization Sequence 2-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–9 PLL Performance 2-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–10 Instruction Execution and Timing 2-34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–1 PDM Clock Divider 3-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–2 Relationship Between Comparator/Interrupt Activity and the TIMER1 Control 3-15. . . . . . . .

4–1 Top of Stack (TOS) Register Operation 4-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–2 Relative Flag Addressing 4-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–3 Data Memory Organization and Addressing 4-45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–4 Data Memory Example 4-47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–5 FIR Filter Structure 4-59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–6 Setup and Execution of MSP50P614/MSP50C614 Filter Instructions, N+1 Taps 4-67. . . . . .

4–7 Filter Instruction and Circular Buffering for N+1 Tap Filter 4-68. . . . . . . . . . . . . . . . . . . . . . . . . .

4–8 Valid Moves/Transfer in MSP50P614/MSP50C614 Instruction Set 4-131. . . . . . . . . . . . . . . . .

5–1 Level Translator Circuit 5-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–2 Hardware Installation 5-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–3 10-Pin IDC Connector 5-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–4 InstallShield Window 5-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–5 Setup Window 5-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–6 Exit Setup Dialog 5-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–7 User Information Dialog 5-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–8 Choose Destination Location Dialog 5-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xii

Figures

5–9 Select Program Folder Dialog 5-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–10 Copying Files 5-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–11 Setup Complete Dialog 5-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–12 Open Screen 5-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–13 Project Menu 5-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–14 Project Open Dialog 5-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–15 File Menu Options 5-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–16 MSP50P614/MSP50C614 Code Development Windows 5-16. . . . . . . . . . . . . . . . . . . . . . . . . .

5–17 RAM Window 5-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–18 CPU Window 5-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–19 Program Window 5-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–20 Hardware Breakpoint Dialog 5-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–21 Inspect Dialog 5-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–22 Inspect Window 5-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–23 I/O Ports Window 5-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–24 Debug Menu 5-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–25 EPROM Programming Dialog 5-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–26 Trace Mode 5-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–27 Init Menu Option 5-27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–28 Options Menu 5-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–29 Miscellaneous Dialog 5-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–30 Windows Menu Options 5-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–31 Context Sensitive Help System 5-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–1 100-Pin PJM Mechanical Information 7-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–2 120-Pin Grid Array Package for the Development Device, P614 7-5. . . . . . . . . . . . . . . . . . . . .

7–3 120 Pin Grid Array (PGA) Package Leads, P614 7-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–4 Speech Development Cycle 7-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A–1 MSP50C605 Architecture A-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A–2 MSP50C605 Memory Organization A-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A–3 MSP50C605 100-Pin PJM Package A-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B–1 MSP50C604 Block Diagram B-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B–2 MSP50C604 Memory Organization and I/O ports B-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B–3 MSP50C604 Slave Mode Signals B-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B–4 MSP50C604 64-Pin PJM Package B-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents

xiii

Tables

Tables

1–1 Signal and Pad Descriptions for the C614 1-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1–2 MSP50C614 100-Pin PJM Plastic Package Pinout Description 1-11. . . . . . . . . . . . . . . . . . . . .

2–1 Signed and Unsigned Integer Representation 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–2 Summary of C614’s Peripheral Communications Ports 2-17. . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–3 Programmable Bits Needed to Control Reduced Power Modes 2-37. . . . . . . . . . . . . . . . . . . . .

2–4 Status of Circuitry When in Reduced Power Modes 2-38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–5 How to Wake-Up from Reduced Power Modes 2-39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–6 Destination of Program Counter on Wake-Up Under Various Conditions 2-40. . . . . . . . . . . . .

3–1 Interrupts 3-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–2 State of the Status Register (17 bit) after RESET Low-to-High 3-21. . . . . . . . . . . . . . . . . . . . .

4–1 Status Register (STAT) 4-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–2 Addressing Mode Encoding 4-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–3 Rx Bit Description 4-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–4 Addressing Mode Bits and {adrs} Field Description 4-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–5 MSP50P614/MSP50C614 Addressing Modes Summary 4-11. . . . . . . . . . . . . . . . . . . . . . . . . .

4–6 Auto Increment and Auto Decrement Modes 4-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–7 Flag Addressing Field {flagadrs} for Certain Flag Instructions (Class 8a) 4-12. . . . . . . . . . . . .

4–8 Initial Processor State for the Examples Before Execution of Instruction 4-13. . . . . . . . . . . . .

4–9 Indirect Addressing Syntax 4-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–10 Symbols and Explanation 4-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–1 1 Instruction Classification 4-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–12 Classes and Opcode Definition 4-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–13 Class 1 Instruction Encoding 4-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–14 Class 1a Instruction Description 4-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–15 Class 1b Instruction Description 4-27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–16 Class 2 Instruction Encoding 4-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–17 Class 2a Instruction Descritpion 4-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–18 Class 2b Insstruction Description 4-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–19 Class 3 Instruction Encoding 4-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–20 Class 3 Instsruction Description 4-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–21 Class 4a Instruction Encoding 4-34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–22 Class 4a Instruction Description 4-35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–23 Class 4b Instruction Description 4-35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–24 Class 4c Instruction Description 4-35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xiv

4–25 Class 4d Instruction Description 4-35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–26 Class 5 Instruction Encoding 4-36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–27 Class 5 Instruction Description 4-36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–28 Class 6a Instruction Encoding 4-38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–29 Class 6a Instruction Description 4-38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–30 Class 6b Instruction Description 4-39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–31 Class 7 Instruction Encoding and Description 4-40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–32 Class 8a Instruction Encoding 4-41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–33 Class 8a Instruction Description 4-42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–34 Class 8b Instruction Description 4-42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–35 Class 9a Instruction Encoding 4-43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–36 Class 9a Instruction Description 4-43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–37 Class 9b Instruction Description 4-43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–38 Class 9c Instruction Description 4-44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–39 Class 9d Instruction Description 4-44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–40 Data Memory Address and Data Relationship 4-46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–41 MSP50P614/MSP50C614 Computational Modes 4-50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–42 Hardware Loops in MSP50P614/MSP50C614 4-54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–43 Initial Processor State for String Instructions 4-55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–44 Lookup Instructions 4-57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–45 Auto Increment and Decrement 4-73. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–46 Addressing Mode Bits and adrs Field Description 4-73. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–47 Flag Addressing Syntax and BIts 4-73. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–48 Names for cc 4-87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Tables

5–1 String Functions 5-46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–1 MSP50C614 100-Pin PJM Plastic Package Pinout Description 7-3. . . . . . . . . . . . . . . . . . . . . .

A–1 MSP50C605 100-Pin PJM Plastic Package Pinout Description A-7. . . . . . . . . . . . . . . . . . . . . .

B–1 MSP50C604 64-Pin PJM Plastic Package Pinout Description B-8. . . . . . . . . . . . . . . . . . . . . . .

Contents

xv

Notes, Cautions, and Warnings

Notes, Cautions, and W arnings

MSP50C605 and MSP50C604 1-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PGA Package 1-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ROM Locations that Hold Interrupt Vectors 2-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Instructions with References 2-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Block Protection Mode 2-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Block Protections Word 2-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Setting a Bit in the IFR Using the OUT Instruction 2-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Interrupt Service Branch 2-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Writing to the TIM Register 2-27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ClkSpdCtrl Bits 8 and 9 2-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference Oscillator Stopped by Programmed Disable 2-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Register Trim Value 2-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Idle State Clock Control Bit 2-36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reading the Data Register 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PDM Enable Bit 3-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IntGenCtrl Register Bit 15 3-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Internal RAM State after Reset 3-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Stack Pointer Initialization 3-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Data Memory Access 4-45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Scan Port Bond Out 7-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MSP50C605 A-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MSP50C604 B-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xvi

Chapter 1

Introduction to the MSP50C614

The MSP50C614 (C614) is a low cost, mixed signal controller, that combines
a speech synthesizer, general-purpose I/O, onboard ROM, and direct
speaker-drive in a single package. The computational unit utilizes a powerful
new DSP which gives the C614 unprecedented speed and computational
flexibility compared with previous devices of its type. The C614 supports a
variety of speech and audio coding algorithms, providing a range of options
with respect to speech duration and sound quality.

Topic Page

1.1 Features of the C614 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 Applications 1–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 Development Version: P614 1–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4 Functional Description 1–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.5 C605 and C604 1–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.6 T erminal Assignments and Signal Descriptions 1–10. . . . . . . . . . . . . . .

1-1

Features of the C614

1.1 Features of the C614

-

Advanced, integrated speech synthesizer for high quality sound

-

Operates up to 8 MHz (performs up to 8 MIPS)

-

Very low-power operation, ideal for hand-held devices

-

Low voltage operation, sustainable by three batteries

-

Reduced power stand-by modes, less than 10 µA in deep-sleep mode

-

Supports high-quality synthesis algorithms such as MELP, CELP, LPC,
and ADPCM

-

Contains 32K words onboard ROM (2K words reserved)

-

640 words RAM

-

40 general purpose, bit configurable I/O

-

8 inputs with programmable pullup resistors and a dedicated interrupt
(key-scan)

-

16 dedicated output pins

-

Direct speaker driver, 32 Ω (PDM)

-

One-bit comparator with edge-detection interrupt service (IMPORTANT:
Not currently supported)

-

Resistor-trimmed oscillator or 32-kHz crystal reference oscillator

-

Serial scan port for in-circuit emulation and diagnostics

-

The MSP50C614 is sold in die form; an emulator device for the
MSP50C614 is sold in a ceramic package for development.

1-2

1.2 Applications

Applications

Due to its low cost, low-power needs, and high programmability, the C614 is
suitable for a wide variety of applications incorporating I/O control and high­quality speech:

-

Talking Toys

-

Electronic Learning Aids

-

Games

-

Talking Clocks

-

Talking Books

-

Talking Dictionaries

-

Warning Systems

-

Equipment for the Handicapped

Introduction to the MSP50C614

1-3

Development Device: MSP50P614

1.3 Development Device: MSP50P614

The MSP50P614 is an EPROM based version of the MSP50C614, and is
available in 120 pin windowed ceramic pin grid array. This EPROM based
version of the device is only available in limited quantities to support software
development. Since the MSP50P614 program memory is EPROM, each
person doing software development should have several of these PGA
packaged devices.

The MSP software development tool supports non-real-time debugging by
scanning the code sequence through the MSP50C614/MSP50P614 scanport
without programming the EPROM. However, the rate of code execution is lim­ited by the speed of the PC parallel port. Any MSP50C614/MSP50P614 can
be used in this debugging mode.

The MSP50P614 EPROM must be programmed to debug the code in real
time. The MSP software development tool is used to program the EPROM, set
a breakpoint, and evaluate the internal registers after the breakpoint is
reached. If a change is made to the code, the code will need to be updated and
programmed into another device while erasing previous devices. This cycle
of programming, debugging, and erasing typically requires 10–15 devices to
be in the eraser at any one time, so 15–20 devices may be required to operate
efficiently . The windowed PGA version of the MSP50P614 is required for this
debugging mode.

1-4

1.4 Functional Description

The device consists of a micro-DSP core, embedded program and data
memory , and a self-contained clock generation system. General-purpose pe­riphery is comprised of 64 bits of partially configurable I/O.

The core processor is a general-purpose 16 bit micro-controller with DSP
capability. The basic core block includes a computational unit (CU), data
address unit, program address unit, two timers, eight level interrupt processor,
and several system and control registers. The core processor gives the P614
and C614 break-point capability in emulation.

The processor is a Harvard type for efficient DSP algorithm execution. It re­quires separate program and data memory blocks to permit simultaneous ac­cess. The ROM has a protection scheme to prevent third-party pirating. It is
configured in 32K 17-bit words.

The total ROM space is divided into two areas: 1) The lower 2K words are re­served by T exas Instruments for a built-in self-test, 2) the upper 30K is for user
program/data.

The data memory is internal static RAM. The RAM is configured in 640 17-bit
words. Both memories are designed to consume minimum power at a given
system clock and algorithm acquisition frequency.

Functional Description

A flexible clock generation system is included that enables the software to
control the clock over a wide frequency range. The implementation uses a
phase-locked loop (PLL) circuit that drives the processor clock at a selectable
frequency between the minimum and maximum achievable. Selectable
frequencies for the processor clock are spaced apart in 65.536-kHz steps. The
PLL clock-reference is also selectable; either a resistor-trimmed oscillator or
a crystal-referenced oscillator may be used. Internal and peripheral clock
sources are controlled separately to provide different levels of power
management (see Figure 1–2).

The peripheral consists of five 8-bit wide general-purpose I/O ports, one 8-bit
wide dedicated input port, and one 16-bit wide dedicated output port. The
bidirectional I/O can be configured under software control as either
high-impedance inputs or as totem-pole outputs. They are controlled via
addressable I/O registers. The input-only port has a programmable pullup
option (100-kΩ minimum resistance) and a dedicated service interrupt. These
features make the input port especially useful as a key-scan interface.

A simple one-bit comparator is also included in the periphery . The comparator
is enabled by a control register, and its pin access is shared with two pins in
one of the general-purpose I/O ports. Rounding out the C614 periphery is a

Introduction to the MSP50C614

1-5

C605 and C604 (Preliminary Information)

built in pulse-density-modulated DAC (digital-to-analog converter) with direct
speaker-drive capability . The block diagram appearing in Figure 1–1 gives an
overview of the C614 functionality. IMPORTANT: a one bit comparator is not
currently supported.

Typical connections to implement reset functionality are shown in Figure 1–3.

1.5 C605 and C604 (Preliminary Information)

Two related products, the MSP50C605 (C605) and MSP50C604(C604) use
the C614 core. The C605 has a 224K byte data ROM built into the chip and
32 I/O port pins. The C605 can provide up to 30 minutes of uninterrupted
speech. The C604 is designed to support slave operation with an external host
microcontroller. In this mode the C604 can be programmed with a code that
communicates with the host via a command set. This command set can be de­signed to support LPC, CELP , MELP, and ADPCM coders by selecting the ap­propriate command. The C604 can also be used stand-alone in master mode.
The C604 and the C605 use the P614 as the development version device. De­tails on C605 and C604 processors are found in Appendix A and B.

Note: MSP50C605 and MSP50C604

MSP50C605 and MSP50C604 are in the Product Preview stage of develop­ment. For more information contact your local TI sales office. See Appen­dices A and B for more information.

1-6

Figure 1–1. Functional Block Diagram for the C614

C605 and C604 (Preliminary Information)

V

SCAN
SCAN

PGM

SCAN

PULSE

RESET

OSC

OSC

OUT
CLK

SYNC

TEST

DAC

DAC

OUT

PLL

V

Power (P614 only)

(EP)ROM 32k x (16 + 1) bit

Test-Area
(reserved)

User ROM 0x0800 to

INT vectors 0x7FF0 to

Core

Instr. Decoder
PCU Prog. Counter Unit
CU Computational Unit

TIMER1 PRD1

TIMER2

Clock Control
Gen. Control

Interrupt Processor

or

DMAU

RAM 640 x 17 bit
(data)

P

M

Scan Interface

Break Point

Emulation
OTP Program
Serial Comm.

(C614 only)
(P614 only)

DAC 0x30
32 Ohm PDM

Initialization
Logic

OSC Reference

Resistor
Trimmed
32 kHz nominal

or

Crystal
Referenced

32.768 kHz
PLL Filter

IN

IN

DDVPP

SS

55

0x0000 to

0x3A

PRD2

0x3E

FLAG

0x39

Data Mem. Addr.

0x07FF

0x7FEF

0x7FFF

TIM1
0x3B

TIM2
0x3F

0x3D

0x38

MASK

0x38

0x000 to

0x027F

A port I/O

Data 0x00
Control 0x04

B port I/O

Data 0x08
Control 0x0C

C port I/O

Data 0x10
Control 0x14

Comparator
1 bit: PD5 vs PD

D port I/O

Data 0x18
Control 0x1C

E port I/O

Data 0x20
Control 0x24

F port INPUT

Data 0x28

G port OUTPUT

Data 0x2C

4

+–

PA

PB

PC

PD

PE

PF

PG

0–7

8

0–7
8

0–7

8

0–7

8

0–7
8

0–7
8

0–15

16

Introduction to the MSP50C614

1-7

C605 and C604 (Preliminary Information)

Figure 1–2. Oscillator and PLL Connection

a) Crystal Oscillator Operation Connections

MSP50P614
MSP50C614

OSC

IN

32.768 kHz†

10 Mن

†

Keep these components as close as possible to the OSCIN, OSC

22 pF†

OSCOUT PLL

10 Mن

b) Resistor Trim Operation Connections

MSP50C614
MSP50P614

OSC

R

(RTO)

IN

OSCOUT PLL

470 kΩ 1%†

=

22 pF†

, and PLL pins.

OUT

C

(PLL)

C

= 3300 pF†

(PLL)

= 3300 pF†

†

Keep these components as close as possible to the OSCIN, OSC

1-8

, and PLL pins.

OUT

Figure 1–3. RESET Circuit

V

PP

(MSP50P614 only)

IN914

C605 and C604 (Preliminary Information)

To Pin 1 of Optional (Scanport)
Connector

‡

V

DD

100 kΩ

†

Inside the
MSP50P614
MSP50C614

†

If it is necessary to use the software development tools to control the MSP50P614 in application board, the 1 kΩ resistor is need­ed to allow the development tool to over drive the RESET circuit on the application board.

‡

This Diode can be omitted (shorted) if the application does not require use of the scanport interface. See Section 7.1.1 regarding
scan port bond out.

RESET

V

SS

1 kΩ

1 µF

(20%)

To Pin 2 of optional (scan port) connector

5 V

IN914

Reset

Switch

†

Introduction to the MSP50C614

1-9

Terminal Assignments and Signal Descriptions

1.6 Terminal Assignments and Signal Descriptions

Table 1–1. Signal and Pad Descriptions for the C614

SIGNAL PAD NUMBER I/O DESCRIPTION

Input/Output Ports

PA0 – PA
PB0 – PB
PC0 – PC
PD0 – PD
PE0 – PE
PF0 – PF
PG0 – PG
PG8 – PG
Pins PD4 and PD5 may be dedicated to the comparator function, if the comparator enable bit is set.

Refer to Section 3.3,

SCANIN 54 I Scan port data input
SCANOUT 50 O Scan port data output
SCANCLK 53 I Scan port clock
SYNC 52 I Scan port synchronization
TEST

PGMPULSE
The scan port pins must be bonded out on any C614 production board.

Consult the “Important Note regarding Scan Port Bond Out”, Section 7.1.1,

OSC
OSC
PLL 67 O Phase-lock-loop filter

DAC
DAC

RESET 55 I Initialization

V
V

†

Pads VSS (19) and VDD (21) service the DAC circuitry. Their pins tend to sustain a higher current draw . A dedicated decoupling
capacitor across these pins is therefore required. Refer to Section 6.1,

7

7
7
7
7

7

7
15

Comparator

IN
OUT

P
M

SS
DD

75 → 68 I/O Port A general-purpose I/O (1 Byte)
85 → 78 I/O Port B general-purpose I/O (1 Byte)

8 → 1 I/O Port C general-purpose I/O (1 Byte)
18 → 11 I/O Port D general-purpose I/O (1 Byte)
63 → 56 I/O Port E general-purpose I/O (1 Byte)
31 → 24 I Port F key-scan input (1 Byte)
49 → 42
39 → 32

, for details. (Currently not supported)

Scan Port Control Signals

51 I C614 : test modes

Oscillator Reference Signals

65 I Resistor/crystal reference in
66 O Resistor/crystal reference out

DAC Sound Output

22 O Digital-to-analog output 1 (+)
20 O Digital-to-analog output 2 (–)

Power Signals

9, 19†, 40, 64, 76 Ground

10, 21†, 23, 41, 77 Processor power (+)

O Port G dedicated output (2 Bytes)

P614 : programming pulse

Scan Port Bond Out

Initialization

Application Circuits

.

, for details.

1-10

Terminal Assignments and Signal Descriptions

The C614 is sold in die form for its volume production. Contact you local TI
sales office for mount and bond information.

MSP50C614 is also available in 100 pin plastic QFP package. The pinout is
shown in Figure 1–4 and Table 1–2.

Table 1–2. MSP50C614 100-Pin PJM Plastic Package Pinout Description

Description Pin # Description Pin # Description Pin # Description Pin #

GND3/DA 1 GND4 26 PE

0

NC 2 VCC4 27 GND 52 NC 77
NC 3 NC 28 NC 53 NC 78
NC 4 NC 29 NC 54 NC 79

DAC

M

VCC3/DA 6 PF

DAC

P

V

CC

PF

7

PF

6

PF

5

PF

4

PF

3

PF

2

PF

1

PF

0

5 PG

7 PF
8 PF

9 PF
10 PF
11 PF
12 PF

7
6
5
4
3
2
1
0

30 NC 55 NC 80
31 X2 56 NC 81
32 X1 57 NC 82
33 PLL 58 PC
34 PA
35 PA
36 PA

37 PA
13 SCANOUT 38 PA
14 TEST 39 PA
15 SYNC 40 PA
16 SCANCLK 41 PA

7
6
5
4
3
2
1
0

NC 17 SCANIN 42 GND1 67 VCC2 92
PG
PG
PG
PG
PG
PG

PG
PG

15
14
13
12
11
10

9
8

18 RESET 43 VCC1 68 PD
19 PE
20 PE
21 PE
22 PE
23 PE
24 PE
25 PE

7
6
5
4
3
2
1

44 PB
45 PB
46 PB
47 PB
48 PB
49 PB
50 PB

7
6
5
4
3
2
1

51 PB

59 PC
60 PC
61 PC
62 PC
63 PC
64 PC
65 PC

0

7
6
5
4
3
2
1
0

66 GND2 91

7

69 PD
70 PD
71 PD
72 PD
73 PD
74 PD
75 PD

6
5
7

73

2
1
0

76

83
84
85
86
87
88
89
90

93
94
95
96
97
98
99

100

Introduction to the MSP50C614

1-11

Terminal Assignments and Signal Descriptions

Figure 1–4. MSP50C614 100 Pin PJM PLastic Package Pinout (Preliminary Information)

PJM PACKAGE

(TOP VIEW)

2

PD6

94

37

PD7

93

38

CC

V

92

39

GND2

PC0

90

91

41

40

PC1

89

42

PC2

88

43

PC3

87

44

PC4

86

45

PC5

85

46

PC6

PC7NCNC

83

84

48

47

82

49

81

50

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

NC
NC
NC
NC
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7

V

CC

GND1
PA0

PA1
PA2

PA3
PA4
PA5
PA6
PA7
PLL
X1
X2
NC
NC
NC

GND
PE0

1

GND3/DA

NC
NC
NC

DACM

3/DAV

CC

DACP

V

CC

PF7
PF6

PF5
PF4
PF3
PF2
PF1
PF0

NC
PG15
PG14
PG13

PG12
PG11
PG10

PG9
PG8

GND4

CC

NC

NC

PG7

PD1

PD2

PD4

PD5

99

32

98

33

PD3

97

34

96

35

95

36

PD0

100

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27

4V

28
29
30

31

1-12

PG6

PG5

PG4

PG3

PG2

PG1

PG0

TEST

SCANOUT

SYNC

SCANIN

SCANCLK

PE7

PE6

RESET

PE5

PE4

PE3

PE2

PE1

Terminal Assignments and Signal Descriptions

For software development and prototyping, a windowed ceramic 120-pin grid
array packaged P614 is available. The P614’s PGA package is shown in
Figure 1–5 and Table 1–3:

Figure 1–5. 120 Pin Grid Array Package for the Development Device, P614

MSP50P614

N
M
L
K
J
H
G
F
E
D
C
B
A

214365871012 1113 9

N
M
L
K
J
H
G
F
E
D
C
B
A

1

42 3

extra pin

5

(bottom view)(top view)

12 1310 118967

Note: PGA Package

The PGA package is only available in limited quantities for development pur­poses.

Introduction to the MSP50C614

1-13

Terminal Assignments and Signal Descriptions

The pin assignments for the 120-pin PGA package (P614 device only) are out­lined in the following table. Refer to Section 1.6 for more information on the
signal functions.

nc nc V

N

nc nc DACMDACPPF

M

PD0nc nc V

L

PD3PD

K

PD5PD4PD

J

V

H

DD

V

G

SS

PC2PC3PC

F

PC5PC

E

PC7nc nc extra nc V

D

nc nc nc nc PB

C

nc nc nc PB

B

nc nc nc PB

A

1

PD7PD
PC1PC

6

†

DD

PF

nc PG

2
6
0
4

nc PE

SS

PF

7

†

V

PB

0

PB

2

DD

5
6

1
3
4

PF2V
PF

3

PF

4

(bottom view) RESET scanin PE

PB5V
PB

6

PB7V

PG15PG12PG

PP

PF1PG14PG11PG
PF0PG

PA

SS

PA0PA

PA

DD

13

PG

9

PA

3

7

PA

2

PA

1

5
4

PLL OSC

PA

V

10

8

nc nc PG

PG

pgmpuls SYNC scanclk

PE

nc nc nc nc

OSC

6

6
2

4
0

OUT

IN

V

DD

PG

5

PG
PG0scanout

PE
PE

SS

nc nc
nc nc

PG

3

PE

5

PE

2

PE

SS

nc nc PG

nc

7
4
1

7
6
3
1

1 2 3 4 5 6 7 8 9 10 11 12 13

†

It is important to provide a separate decoupling capacitor for the VDD, VSS pair which services the DAC. These pins are PGA
numbers N3 and L4, respectively. The relatively high current demands of the digital-to-analog circuitry make this a requirement.
Refer to Section 6.1,

TBD

, for details.

1-14

Chapter 2

MSP50C614 Architecture

A detailed description of MSP50C614 architecture is included in this chapter.
After reading this chapter, the reader will have in-depth knowledge of internal
blocks, memory organization, interrupt system, timers, clock control mecha­nism, and various low power modes.

Topic Page

2.1 Architecture Overview 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 Computation Unit 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3 Data Memory Address Unit 2–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4 Program Counter Unit 2–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5 Bit Logic Unit 2–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6 Memory Organization: RAM and ROM 2–15. . . . . . . . . . . . . . . . . . . . . . . .

2.7 Interrupt Logic 2–22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.8 Timer Registers 2–26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.9 Clock Control 2–29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.10 Execution Timing 2–33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11 Reduced Power Modes 2–34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-1

2.1 Architecture Overview

The core processor in the C614 is a medium performance mixed signal pro­cessor with enhanced microcontroller features and a limited DSP instruction
set. In addition to its basic multiply/accumulate structure for DSP routines, the
core provides for a very efficient handling of string and bit manipulation. A
unique accumulator-register file provides additional scratch pad memory and
minimizes memory thrashing for many operations. Five different addressing
modes and many short direct references provide enhanced execution and
code efficiency.

The basic elements of the C614 core are shown in Figure 2–1. In addition to
the main computational units, the core’s auxiliary functions include two timers,
an eight-level interrupt processor, a clock generation circuit, a serial scan-port
interface, and a general control register.

2-2

Figure 2–1. MSP50C614 Core Processor Block Diagram

Interrupt Inputs

Interrupt Flag Register (IFR)†

Multiplier (MR)† Shift Value (SV)†

17 x 17 Multiplier

Product High (PH)†

MUX

16 bit ALU

32 Accumulators (AC0–AC31)†

Control Register (CTRL)†

Interrupt Processor

Serial Interface Register†

Oscillator Register†
Timer Period (PRD1 and PRD2)†
Timer Register (TIM1 and TIM2)†

AP0–AP3†

Accumulator Pointer

Peripheral

Interface

Serial

Interface

VCO

Frequency

Divider

Instruction

Decoder

+1

Column Exchange

Stack (R7)

Page (R6)

Index (R5)

Loop (R4)

R3
R2
R1
R0

MUX

Arithmetic Unit

MUX

Data Memory

640 x 17 bit

†

Indicates internal programmable registers.

Incrementor

Top Of Stack (TOS)†

Program Counter (PC)†

Protection Register (PR)†

Data Pointer (DP)†

MUX

String Register†

MUX

Repeat Counter†

Status Register (STAT)†

Flag Register†

Test Code
2k x 17 bit

Program Memory

30k x 17 bit

Macro Calls

Vectors

MSP50C614 Architecture

2-3

Figure 2–2. Computational Unit Block Diagram (The shaded boxes represent internal

programmable registers.)

16

16

16

16

16

16

5

Internal Databus – 16 bit

Shift Value (SV)

Multiplier Register (MR)

17 bit x 17 bit

Multiplexer

Product High (PH)

Accumulators

AP0
AP1

AP2
AP3

16

16

(Product Low, PL)
16 LSB

16 MSB

16

0

0

16

AB

ALU

16

Read/Write

AC0
AC1
AC2

AC3
AC4

5

AC5
AC6
AC7

AC8

AC9
AC10
AC11

AC12
AC13
AC14

AC15

AC16
AC17

AC18
AC19

AC20
AC21
AC22

AC23
AC24

AC25
AC26
AC27

AC28
AC29
AC30

AC31

16

16

2-4

2.2 Computation Unit

The computational unit (CU) is comprised of a (17-bit by 17-bit) Booth’s
algorithm multiplier and a 16-bit arithmetic logic unit (ALU). The block diagram
of the CU is shown in Figure 2–2. The multiplier block is served by 4 system
registers: a 16-bit multiplier register (MR), a 16-bit write-only multiplicand
register, a 16-bit high word product register (PH), and a 4-bit shift value register
(SV). The output of the ALU is stored in one 16-bit accumulator from among
the 32 which compose the accumulator-register block. The accumulator
register block can supply either one operand to the ALU (addressed
accumulator register or its offset register) or two operands to the ALU (both the
addressed register and its offset).

2.2.1 Multiplier

The multiplier executes a 17-bit by 17-bit 2s complement multiply and
multiply-accumulate in a single instruction cycle. The sign bit within each
operand is bit 16, and its value extends from bit 0 (LSB) to bit 15 (MSB). The
sign bit for either operand (multiplier or multiplicand) can assume a positive
value (zero) or a value equal to the MSB (bit 15). In assuming zero, the extra
bit supports unsigned multiplication. In assuming the value of bit 15, the extra
bit supports signed multiplication. Table 2–1 shows the greater magnitude
achievable when using unsigned multiplication (65535 as opposed to 32767).

Computation Unit

Table 2–1. Signed and Unsigned Integer Representation

Unsigned Signed

Decimal Hex Decimal Hex

65535 0xFFFF −1 0xFFFF
32768 0x8000 −32768
32767 0x7FFF 32767
0

During multiplication, the lower word (LSB) of the resulting product, product
low, is multiplexed to the ALU. Product low is either loaded to or arithmetically
combined with an accumulator register. These steps are performed within the
same instruction cycle. Refer to Figure 2–3. At the end of the current execution
cycle, the upper word (MSB) of the product is latched into the product high
register (PH).

0x0000 0 0x0000

0x8000
0x7FFF

MSP50C614 Architecture

2-5

Computation Unit

The multiplicand source can be either data memory, an accumulator, or an
accumulator offset. The multiplier source can be either the 16-bit multiplier
register (MR) or the 4-bit shift value (SV) register. For all multiply operations,
the MR register stores the multiplier operand. For barrel shift instructions, the
multiplier operand is a 4-to-16-bit value that is decoded from the 4-bit shift
value register (SV). Refer to Figure 2–4.

As an example of a barrel shift operation, a coded value of 0x7 in the SV
register results in a multiplier operand of 0000000010000000 (1 at bit 7). This
causes a left-shift 7-times on the 16 bit multiplicand. The output result is 32-bit.
On the other hand, if the status bit FM (multiplier shift mode) is SET, then the
multiplier operand (0000000010000000) is left-shifted once to form a 17
significant-bit operand (00000000100000000). This mode is included to avoid
a divide-by-2 of the product, when interpreting the input operands as signed
binary fractions. The multiplier shift mode status bit is located in the status
register (STAT).

All three multiplier registers (PH, SV, and MR) can be loaded from data
memory and stored to data memory . In addition, data can be transferred from
an accumulator register to the PH, or vice versa. Both long and short constants
can be directly loaded to the MR from program memory.

The multiplicand is latched in a write-only register from the internal data bus.
The value is not accessible by memory or other system registers.

2-6

Figure 2–3. Overview of the Multiplier Unit Operation

MULTIPLIER UNIT INPUTS

Computation Unit

Multiplicand 16-bit

- latched in a write-only register
from one of the following sources ...

Data Memory
Accumulator
Offset Accumulator

performs multiplication and barrel shifting

MSB 16-bit LSB 16-bit

(PH) Product High (PL) Product Low

- readable and writeable by Data Memory - a simulated register: PL is realized in ALU-A

- readable and writeable by ALU-A

†

Also write-able by Program Memory

X Multiplier

- writeable and readable by Data Memory
as one of the following ...

MULTIPLYING: 16-bit

SHIFTING:

MULTIPLIER UNIT

MULTIPLIER UNIT INPUTS

(MR)

(SV)

Multiplier Register†

or

Shift Value Register

2.2.2 Arithmetic Logic Unit

4-bit

The arithmetic logic unit is the focal point of the computational unit, where data
can be added, subtracted, and compared. Logical operations can also be
performed by the ALU. The basic hardware word-length of the ALU is 16 bits;
however, most ALU instructions can also operate on strings of 16-bit words
(i.e., a series or array of values). The ALU operates in conjunction with a
flexible, 16-bit accumulator register block. The accumulator register block is
composed of 32, 16-bit registers which further enhances execution and
promotes compact code.

The ALU has two distinct input paths, denoted ALU-A and ALU-B (see
Figure-2–4). The ALU-A input selects between all zeros, the internal databus,
the product high register (PH), the product low (PL), or the offset output of the
accumulator register block. The ALU-B input selects between all zeros and the
output from the accumulator register block.

MSP50C614 Architecture

2-7

Computation Unit

The all-zero values are necessary for data transfers and unitary operations.
All-zeros also serve as default values for the registers, which helps to minimize
residual power consumption. The databus path through ALU-A is used to input
memory values (RAM) and constant values (program memory) to the ALU.
The PH and PL inputs are useful for supporting multiply-accumulate
operations (refer to Section 2.2.1,

The operations supported by the ALU include arithmetic, logic, and
comparison. The arithmetic operations are addition, subtraction, and load
(add to zero). The logical operations are AND, OR, XOR, and NOT.
Comparison includes equal-to and not-equal-to. The compare operations may
be used with constant, memory, or string values without destroying any
accumulator values.

2.2.2.1 Accumulator Block

The output of the ALU is the accumulator block. The accumulator block is com­posed of 32, 16-bit registers. These registers are organized into two terminals,
denoted accumulator and OFFSET accumulator. The terminals provide refer­ences for all of the data which is to be held in the accumulator block. The accu­mulator incorporates one-half of the 32 accumulator registers: AC0..AC15.
The OFFSET accumulator incorporates the other half: AC16..AC31.

Multiplier

).

2-8

Figure 2–4. Overview of the Arithmetic Logic Unit

ALU INPUTS

ALU-A 16-bit

Computation Unit

ALU-B 16-bit

- selects between ...
all 0’s

Offset Accumulator Register
Data Memory
Program Memory

(PH)

(PL)

16, 16-bit registers ... 16, 16-bit registers ...
AC0, AC1, AC2, AC3, AC4, AC5, AC6, AC7, AC8,

AC9, AC10, AC11, AC12, AC13, AC14, AC15

†

For multiply-accumulate operations.

Product High†
Product Low†

ARITHMETIC LOGIC UNIT

performs arithmetic, comparison, and logic

ALU OUTPUTS

THE ACCUMULATOR BLOCK

Accumulator Register OFFSET Accumulator Register

AC16, AC17, AC18, AC19, AC20, AC21, AC22,
AC23, AC24, AC25, AC26, AC27, AC28, AC29,
AC30, AC31

2.2.2.2 Accumulator Pointer Block

- selects between ...
all 0’s

Accumulator Register

There are four 5-bit registers which are used to store pointers to members of
the accumulator block. The accumulator pointers (AP0, AP1, AP2, AP3) are
used in two modes: 1) as a direct reference to one of 32, or 2) as an indirect
reference. The indirect reference includes a direct reference to one of 16 and
an offset (optional) which increments the reference by 16: AC(N+16). For
example, AC0 has its offset register located at AC16. AC1 has an offset
register located at AC17, and so on. The block is circular: address 31, when
incremented, results in address 0. The offsets of AC16 through AC31,
therefore, are AC0 through AC15, respectively. See Figure 2–5 Indirect
referencing by the AP pointers is supported by most of the C614’s
accumulator-referenced instructions.

MSP50C614 Architecture

2-9

Computation Unit

When writing an accumulator-referenced instruction, therefore, the working
accumulator address is stored in one of AP0 to AP3. The C614 instruction set
provides a two-bit field for all accumulator referenced instructions. The two-bit
field serves as a reference to the accumulator pointer which, in turn, stores the
address of the actual 16-bit accumulator. Some MOV instructions store the
contents of the APn directly to memory or load from memory to the APn
register. Other instructions can add or load 5-bit constants to the current APn
register contents. A full description of the C614 instruction set is given in
Chapter 4,

Instructions

.

Figure 2–5. Overview of the Arithmetic Logic Unit

Accumulator Block: 32, 16-bit registers AC(0) . . . AC(31)
Accumulator Block Pointers: 4, 5-bit registers AP(0) . . . AP(3)

The accumulator block pointers may assume values in one of two forms:

1) DIRECT REFERENCE:

2) INDIRECT REFERENCE: 0 . . . 15 points to: 0 . . . 15

– AP registers are served by a 5-bit processor for sequencing addresses or repetitive operations.
– Selection between the 4 AP’s is made in the 2-bit An field in all accumulator-referenced

instructions

2.2.2.3 String Operations

The AP registers are served by a 5-bit processor that provides efficient
sequencing of accumulator addresses. The design automates repetitive
operations like long data strings or repeated operations on a list of data.

When operating on a multiword data string, the address is copied from the AP
register to fetch the least significant word of the string. This copy is then
consecutively incremented to fetch the next n words of the string. At the
completion of the consecutive operations, the actual address stored in the AP
register is left unchanged; its value still points to the least significant location.
The AP register, therefore, is loaded and ready for the next repeatable
operation.

0 . . . 31

AC Register #

0 . . . 15 OFFSET points to: 16 . . . 31
15 . . . 31 OFFSET points to: 0 . . . 15

2-10

Data Memory Address Unit

For some instructions, the 5-bit string processor can also preincrement or
predecrement the AP pointer-value by +1 or –1, before being used by the
accumulator register block. This utility can be effectively used to minimize
software overhead in manipulating the accumulator address. The
premodification of the address avoids the software pipelining effect that
post-modification would cause.

Some C614 instructions reference only the accumulator register and cannot
use or modify the offset register that is fetched at the same time. Other instruc­tions provide a selection field in the instruction word (A~ or ~A op-code bit).
This has the effect of exchanging the column addressing sense and thus the
source or order of the two registers. Also, some instructions can direct the ALU
output to be written either to the accumulator register or to the offset accumula­tor register. Refer to Chapter 4,

Instructions

, for more details.

The ALU’s accumulator block functions as a small workspace, which elimi­nates the need for many intermediate transfers to and from memory . This al­leviates the memory thrashing which frequently occurs with single accumula­tor designs.

2.3 Data Memory Address Unit

The data memory address unit (DMAU) provides addressing for data memory
(internal RAM). The block diagram of the DMAU is shown in Figure 2–6. The
unit consists of a dedicated arithmetic block and eight read/write registers (R0
through R7). Each read/write register is 16-bits in size. The arithmetic block
is used to add, subtract, and compare memory-address operands. The
register set includes four general-purpose registers (R0 to R3) and four
special-purpose registers. The special-purpose registers are: the LOOP
control register (R4), the INDEX register (R5), the P AGE register (R6), and the
STACK register (R7). The DMAU generates a RAM address as output. The
DMAU functions completely in parallel with the computational unit, which
helps the C614 maintain a high computational throughput.

MSP50C614 Architecture

2-11

Data Memory Address Unit

Figure 2–6. Data Memory Address Unit

Arithmetic Block

Internal
Databus

2.3.1 RAM Configuration

The data memory block (RAM) is physically organized into 17-bit parallel
words. Within each word, the extra bit (bit 16) is used as a flag bit or tag for
op-codes in the instruction set. Specifically , the flag bit directs complex branch
conditions associated with certain instructions. The flag bit is also used by the
computational unit for signed or unsigned arithmetic operations (see
Section 2.2.1,

R0
R1
R2

R3
R4

R5
R6
R7

LOOP
INDEX

PAGE

STACK

Register Addressing Mode

Internal Program Bus

Multiplier

).

RAM Address

2-12

The size of the C614 RAM block is 640 17-bit locations. Each address provided
by the DMAU causes 17 bits of data to be addressed. These 17 bits are
operated on in different ways, depending on the instructions being executed.
For most instructions, the data is interpreted as 16-bit word format. This means
that bits 0 through 15 are used, and bit 16 is either ignored or designated as
a flag or status bit.

Data Memory Address Unit

There are two-byte instructions, for example MOVB, which cause the proces­sor to read or write data in a byte (8-bit) format. (The B appearing at the end
of MOVB designates it as an instruction, which uses byte-addressable argu­ments.) The byte-addressable mode causes the hardware to read/write either
the upper or lower 8 bits of the 16-bit word based on the LSB of the address.
In this case, the address is a byte address, rather than a word address. Bits
0 through 7 within the word are used, so that a single byte is automatically right­justified within the databus. Bits 8 through 15 may also be accessed as the up­per byte at that same address.

A third data-addressing mode is the flag data mode, whereby , the instruction
operates on only the single flag bit (bit 16) at a given address. All flag mode
instructions execute in one instruction cycle. The flags can be referenced in
one of two addressing modes: 1) global address, whereby 64 global flags are
located at fixed locations in the first 64 RAM addresses, and 2) flag relative
address, whereby a reference is made relative to the current P AGE (R6). The
relative address supports 64 different flags whose PAGE-offset values are
stored in the PAGE register. The flag mode instructions cannot address
memory in the INDEX-relative modes. See Chapter 4,

Instructions

, for more

details.

2.3.2 Data Memory Addressing Modes

The DMAU provides a powerful set of addressing modes to enhance the per­formance and flexibility of the C614 core processor. The addressing modes for
RAM fall into three categories:

-

Direct addressing

-

Indirect addressing with post-modification

-

Relative addressing

The relative addressing modes appear in three varieties:

-

Immediate Short, relative to the PAGE (R6) register.
The effective RAM address is: [*R6 + (a 7 bit direct offset)].

-

Relative to the INDEX (R5) register.
The effective RAM address is: [*R5 + (an indexed offset)].

-

Long Immediate, relative to the register base.
The effective RAM address is: [*Rx + (a 16 bit direct offset)].

Refer to Chapter 4,
used in conjunction with various instructions.

Instructions

, for a full description of how these modes are

MSP50C614 Architecture

2-13

Program Counter Unit

2.4 Program Counter Unit

The program counter unit provides addressing for program memory (onboard
ROM). It includes a 16-bit arithmetic block for incrementing and loading
addresses. It also consists of the program counter (PC), the data pointer (DP),
a buffer register, a code protection write-only register, and a hardware loop
counter (for strings and repeated-instruction loops). The program counter unit
generates a ROM address as output.

The program counter value, PC, is automatically saved to the stack on various
CALL instructions and interrupt service branches. The stack consists of one
hardware-level register (TOS) which points to the top-of-stack. The TOS is
followed by a software stack. The software stack resides in RAM and is
addressed using the STACK register (R7) in indirect mode (see Section 2.3,

Data Memory Address Unit

The hardware loop counter controls the execution of repeated instructions
using one of two modes: 1) consecutive iterations of a single instruction
following the repeat (RPT) instruction, or 2) a single instruction which operates
on a string of data values (string loops). For all types of repeated execution,
interrupt service branches are automatically disabled (temporarily).

).

2.5 Bit Logic Unit

The data pointer (DP) register is loaded at two instances: 1) from the
accumulator during lookup-table instructions, and 2) from the databus during
the fetch of long string constants. To simplify algorithms which require
sequential indices to lookup tables, the DP register may be stored in RAM.

The bit logic unit is a 1-bit unit which operates on flag bit data. It is controllable
by eleven different instructions, which generate the decision flags for
conditional program control. The results of operations performed by the bit
logic unit are sent either to the flag bit of RAM memory or to the TF1 and TF2
bits of the status register (STAT).

2-14

2.6 Memory Organization: RAM and ROM

Data memory (RAM) and program memory (ROM) are each restricted to
internal blocks on the C614. The program memory is read-only and limited to
32K, 17-bit words. The lower 2048 of these words is reserved for an internal
test code and is not available to the user. The data memory is static RAM and
is limited to 640, 17-bit words. 16 bits of the 17-bit RAM are used for the data
value, while the extra bit is used as a status flag.

The C614 does not have the capability to execute instructions directly from
external memory. However, additional program memory (external ROM) can
be accessed using the general-purpose I/O. The interface for external ROM
must be configured in the software.

2.6.1 Memory Map

The memory map for the C614 is shown in Figure 2–7. Refer to Section 2.6.3,

Interrupt Vectors

and to Section 2.7.2,
on the I/O communications ports.

, for more detailed information regarding the interrupt vectors,

Peripheral Communications (Ports)

Memory Organization: RAM and ROM

, for more information

MSP50C614 Architecture

2-15

Memory Organization: RAM and ROM

Figure 2–7. C614 Memory Map (not drawn to scale)

Program Memory

0x0000

0x07FF

0x0800

0x7F00

0x7FF0

0x7FF7
0x7FF8

0x7FFE
0x7FFF

Internal Test Code

2048 x 17 bit

30704 x 17 bit

(C614 : read-only)

(P614 : EPROM)

Macro Call Vectors

255 x 17 bit

(overlaps interrupt

vector locations)

Usable Interrupt

Unusable Interrupt

RESET vector

(reserved)

User ROM

Vectors†
8 x 17 bit

Vectors

(reserved)

Data Memory

0x0000

0x027F

RAM

640 x 17 bit

Peripheral Ports

0x00
0x04
0x08 PB
0x0C
0x10
0x14
0x18
0x1C
0x20
0x24
0x28
0x2C

0x2F
0x30
0x34
0x38 IntGenCtrl
0x39
0x3A

PA

0–7

PA

0–7

0–7

PB

0–7

PC

0–7

PC

0–7

PD

0–7

PD

0–7

PE

0–7

PE

0–7

PF

0–7

PG

0–15

RTRIM
DAC data
DAC ctrl

IFR
PRD1

data
ctrl
data
ctrl
data
ctrl
data
ctrl
data
ctrl

data

data

Shaded boxes highlight dedicated ROM and control registers.

2.6.2 Peripheral Communications (Ports)

Peripheral functions in the C614 are controlled using one or more of the I/O
address-mapped communications ports. Table 2–2 describes the ports.

The width of each mapped location, shown in width of location, is independent
of the address spacing. In other words, some registers are smaller in width
than the spacing between neighboring addresses. The few unused bits appear
to the right of the LSB values within the DAC Data register, address 0x30 (refer

2-16

to Section 3.2.2,

DAC Control and Data Registers

0x3B
0x3D
0x3E
0x3F

TIM1
ClkSpdCtrl
PRD2
TIM2

).

Memory Organization: RAM and ROM

When writing to any of the locations in the I/O address map, therefore, the
bit-masking need only extend as far as width of location. Within a 16-bit
accumulator, the desired bits (width of location) should be right-justified. The
write operation is accomplished using the OUT instruction, with the address
of the I/O port as an argument.

A read from these locations is accomplished using the IN instruction, with the
address of the I/O port as an argument. When reading from the I/O port to a
16-bit accumulator, the IN instruction automatically clears any extra bits in
excess of width of location. The desired bits in the result will be right-justified
within the accumulator.

Allowable access indicates whether the port is bidirectional, read-only, or
write-only. The last column of the table points to the section in this manual
where the functions of each bit have been defined in more detail.

Table 2–2. Summary of C614’s Peripheral Communications Ports

I/O Map

Address

0x00 8 bits read & write I/O port A data PA
0x04 8 bits read & write I/O port A control PA
0x08 8 bits read & write I/O port B data PB

0x0C 8 bits read & write I/O port B control PB

0x10 8 bits read & write I/O port C data PC
0x14 8 bits read & write I/O port C control PC
0x18 8 bits read & write I/O port D data PD

0x1C 8 bits read & write I/O port D control PD

0x20 8 bits read & write I/O port E data PE
0x24 8 bits read & write I/O port E control PE
0x28 8 bits READ only Input port F data PF

0x2C 16 bits read & write Output port G data PG

0x30 16 bits WRITE only DAC data DAC Data 0x0000 3.2.2
0x34 4 bits read & write DAC control DAC Ctrl 0x0 3.2.2
0x38 16 bits read & write Interrupt/general Ctrl IntGenCtrl 0x0000 3.4

Width of
Location

Allowable

Access

Control Register

Name

Abbreviation

Data unknown†

0..7
Ctrl 0x00 ‡

0..7
Data unknown

0..7
Ctrl 0x00

0..7
Data unknown

0..7
Ctrl 0x00

0..7
Data unknown

0..7
Ctrl 0x00

0..7
Data unknown

0..7
Ctrl 0x00

0..7
Data unknown 3.1.2

0..7
Data 0x0000 3.1.3

0..15

State after

RESET LOW

Section for

Reference

3.1.1

0x39 8 bits read & write Interrupt flag IFR

†

Input states are provided by the external hardware.

‡

A control register value of 0x00 yields a port configuration of all inputs.

Same state as
before RESET

MSP50C614 Architecture

2.7

2-17

Memory Organization: RAM and ROM

2.8

2.8

Table 2–2. Summary of C614’s Peripheral Communications Ports (Continued)

I/O Map

Address

0x3A 16 bits read & write TIMER1 period PRD1 0x0000
0x3B 16 bits read & write TIMER1 count-down TIM1 0x0000
0x3D 16 bits WRITE only Clock speed control ClkSpdCtrl 0x0000 2.9.3
0x3E 16 bits read & write TIMER2 period PRD2 0x0000

0x3F 16 bits read & write TIMER2 count-down TIM2 0x0000

Width of
Location

Allowable

Access

Control Register Name Abbreviation

State after

RESET LOW

2.6.3 Interrupt Vectors

When its event has triggered and its service has been enabled, an interrupt
causes the program counter to branch to a specific location. The destination
location is stored (programmed) in the interrupt vector, which resides in an up­per address of ROM. The following table lists the ROM address associated
with each interrupt vector:

Interrupt Name

INT0 0x7FF0 DAC Timer Highest
INT1 0x7FF1 TIMER1 2nd
INT2 0x7FF2 TIMER2 3rd
INT3 0x7FF3 port D
INT4 0x7FF4 port D
INT5 0x7FF5 all port F 6th
INT6 0x7FF6 port D
INT7 0x7FF7 port D

RESET

ROM address of

Vector

Event Source Interrupt Priority

2
3

4
5

0x7FFE storage for ROM Protection Word
0x7FFF storage for initialization vector

Section for

Reference

4th
5th

7th

Lowest

2-18

Note: ROM Locations that Hold Interrupt Vectors

ROM locations that hold interrupt vectors are reserved specifically for this
purpose. Additional ROM locations 0x7FF8 - 0x7FFD are reserved for future
expansion. Like the interrupt vectors, they should not be used for general
program storage.

The branch to the program location that is specified in the interrupt vector is,
of course, contingent on the occurrence of the trigger event. Refer to Section

3.1.5,
specific conditions for each interrupt-trigger event. The branch operation,
however, is also contingent on whether the interrupt service has been enabled.
This is done individually for each interrupt, using the interrupt mask bits within
the interrupt/general control register. Refer to Section 2.7,
more details.

The ROM location 0x7FFF holds the program destination associated with the
hardware RESET event (branch happens after RESET LOW-to-HIGH). The
location 0x7FFE holds the read/write block-protection word. Refer to Sec­tion 2.6.4,
scheme.

2.6.4 ROM Code Security

The C614 provides a mechanism for protecting its internal ROM code from
third-party pirating. The protection scheme is composed of two levels, both of
which prevent the ROM contents from being read. Protection may be applied
to the entire program memory, or it can be applied to a block of memory
beginning at address 0x0000 and ending at an arbitrary address. The two
levels of ROM protection are designated as follows:

Internal and External Interrupts

ROM Code Security

, for an explanation of the ROM security

Memory Organization: RAM and ROM

, for more information regarding the

Interrupt Logic

, for

-

Direct read and write protection, via the ROM scan circuit.

-

Indirect read protection, which prohibits the execution of memory-lookup
instructions.

For the purposes of direct security , the ROM is divided into two blocks. The first
block begins at location 0x0000, and ends, inclusively, at location
(m × 512 – 1), where m is some integer. Each address specifies a 17-bit word
location. The second block begins at location (m × 512), and ends, inclusively ,
at 0x7FFF (the end of the ROM). The first block is protected from reads and
writes by programming a block protection bit, and the second block is
protected from reads and writes by programming a global protection bit.

The two-block system is designed in such a way that a secondary developer
is prevented from changing the partition address between blocks. Once the
block protection has been engaged, then the only security option available to
the secondary developer is engaging the global protection.

Note: Instructions with References

Care must be taken when employing instructions that have either long string
constant references or look-up table references. These instructions will
execute properly only if the address of the instruction and the address of the
data reference are within the same block.

MSP50C614 Architecture

2-19

Memory Organization: RAM and ROM

The protection modes are implemented on the C614 as follows. Within the
ROM is a dedicated storage for the block protection word (address 0x7FFE).
The block protection word is divided into two 6-bit fields and two single-bit
fields. The remainder of the 17-bit word is broken into three single-bit fields
which are reserved for future use.

ROM
Block Protection Word

address 0x7FFE (17-bit wide location)
WRITE only 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

R R TM TM TM TM TM TM GP BP R FM FM FM FM FM FM

05 04 03 02 01 00 05 04 03 02 01 00
TM : True Protection Marker (NTM) GP : Global Protection (0 value protects)
FM : False Protection Marker (NFM) BP : Block Protection (0 value protects)

R : Reserved for future use (must be 1) 1 : Default value of cells on erasure

The two 6-bit fields are designated as the true protection marker, (TM5 through
TM0) and the false protection marker, (FM5 through FM0). When setting up
a partition for partial ROM protection, the address of the partition must be spe­cified as:

2-20

Memory Organization: RAM and ROM

[(NTM + 1) * 512 – 1] = highest ROM address within the block to be

protected
(NTM + 1) * 512 = lowest ROM address which is left unprotected
N

TM

= the value programmed at TM5…TM0 (true

protection marker)
N
N

FM
FM

≡ the binary complement of N

TM

= the value programmed at FM5…FM0 (false

protection marker)

The purpose of the true and false protection markers is to provide parity. An
erased P614 EPROM cell defaults to the value 1. Once programmed from 1
to 0, it cannot be programmed back to 1, unless the cell (and all other cells
along with it) are subject to erasure. A multi-pass programming, therefore, can
only lower the value stored at an EPROM address and never raise it. Once a
valid block-partition address has been properly specified in both TM and FM,
it is impossible to change TM to another address and still maintain parity with
FM.

Note: Block Protection Mode

When applying the block protection mode, bits FM5 through FM0 must be
programmed as the logical inverse of bits TM5 through TM0, respectively.

Across the span of the 32k word ROM space, there are 64 possible values for
NTM (including zero). Hence, the 6-bit-wide locations for TM and FM.

The two single-bit fields found within the block protection word are the block
protection bit (BP) and the global protection bit (GP). If BP and GP are both
SET (erased), then no protection is applied to the ROM.

If BP is CLEAR and GP is SET, then the block protection mode is engaged.
This means that read and write access is prevented at locations 0x0000
through [(N

+ 1) × 512 – 1]. Read and write access is permitted at locations

TM

[(NTM + 1) × 512] through 0x7FFF.
If GP is CLEAR, then the global protection mode is engaged. This prevents

read and write access to all addresses of the ROM, regardless of the value of
BP.

Note: Block Protection Word

The remaining bits in the block protection word are reserved for future use,
but must remain set in order to ensure future compatibility. These bits are
numbers 6, 15, and 16.

MSP50C614 Architecture

2-21

Interrupt Logic

When the device is powered up, the hardware initialization circuit reads the
value stored in the block protection word. The value is then loaded to an inter­nal register and the security state of the ROM is identified. Until this occurs,
execution of any instructions is suspended.

The same initialization sequence is executed before entry into the special
test-modes available on the P614 and C614 (EPROM mode, emulation mode,
and trace mode). This insures that the protection scheme is always in force
when running the processor in one of these modes. A dedicated circuit
ensures that a switch between emulation mode and trace mode cannot occur
without going through the initialization (security check). This forces all look-up
tables and long constant references to originate from an external program
source, when in emulation mode. It is possible to switch from trace mode to
emulation mode by lowering V
jeopardize code security.

2.6.5 Macro Call Vectors

Macro call vectors are similar to CALL instructions except they take an 8-bit
address. The upper 8 bits is always 7Fh. See Section 4.14.83,
more information on the VCALL instruction.

, but this transition, by design, does not

PP

VCALL

, for

2.7 Interrupt Logic

2-22

An eight-level interrupt system is included as part of the C614’s core
processor. The initialization and control of these interrupts is governed by the
following components: the global interrupt enable, the interrupt flag register,
the interrupt mask register, and the interrupt service branch. Each of these is
described below.

Interrupts must be globally enabled using the INTE instruction, and they are
globally disabled using the INTD instruction. INTE sets the global interrupt
enable bit, and INTD clears the global interrupt enable bit. The state of this bit
specifically determines whether any interrupt service branches will be taken.
The global interrupt enable appears as bit 4 within the status register (ST AT).

Each interrupt level waits for the conditions of its trigger event (refer to
Figure 2–8). At the time that a trigger event occurs, the respective bit is
automatically SET in the interrupt flag register (IFR). The IFR is an 8-bit wide
port-addressed register; wherein, each interrupt level is represented. A set bit
in the IFR indicates that the interrupt is pending and waiting to be serviced. A
clear bit indicates that the interrupt is not currently pending. The address of the
IFR is 0x39. After a RESET low, the IFR is left in the same state it was before

Interrupt Logic

the RESET low, assuming there is no interruption in power. For a full
description of the interrupt-trigger events, refer to Section 3.1.5,

External Interrupts

IFR

Interrupt Flag register
address 0x39

D5 : port D5 falling-edge
D4 : port D4 rising-edge
D3 : port D3 falling-edge T1 : TIMER1 underflow
D2 : port D2 rising-edge DA : DAC timer underflow
1 : A bit value 1 indicates pending interrupt waiting to be serviced.
RESET: The IFR is left in the same state it was before RESET low, assuming no interruption in power .

†

INT6 and INT7 may be associated instead with the Comparator function, if the Comparator Enable bit has been set. Refer to
Section 3.3,

Comparator

†

†

, for details.

.

(8-bit wide location)

07 06 05 04 03 02 01 00 ← INT number

D5

D4 PF D3 D2 T2 T1 DA
low high
priority priority

PF : any port F falling-edge
T2 : TIMER2 underflow

Internal and

Individual interrupts are enabled or disabled for service by setting or clearing
the respective bit in the interrupt mask register (IMR, 8 bits). If an interrupt level
has its bit cleared in the IMR, then the interrupt service associated with that
interrupt is disabled. Setting the bit in the IMR allows service to occur (pending
the trigger-event which is registered in the IFR).

The IMR is accessible as part of another (larger) register, namely, the
interrupt/general control register (peripheral port 0x38). After a RESET LOW,
the default value of each bit in the IMR is zero: no interrupt service enabled.
A full description of the bit locations in the interrupt/general control register can
be found in Section 3.4,

Interrupt/General Control Register

.

The IMR functions independently of the IFR, in the sense that interrupt-trigger
events can be registered in the IFR, even if the respective IMR bit is clear. Both
the IFR and IMR are readable and writeable as port addressed registers. To
read the register, use the IN instruction in conjunction with the port address
(0x38 or 0x39). Use the OUT instruction to write. (Refer to Section 2.6.2,

Peripheral Communications (Ports)

, for more information.)

MSP50C614 Architecture

2-23

Interrupt Logic

Note: Setting a Bit in the IFR Using the OUT Instruction

Setting a bit within the IFR using the OUT instruction is a valid way of obtain­ing a software interrupt. An IFR bit may also be cleared, using OUT, at any
time.

Assuming the global interrupt enable is set and the specific bit within the IMR
is set, then, at the time of the interrupt-trigger event, an interrupt service
branch is initiated. (The trigger event is marked by a 0-to-1 transition in the IFR
bit). At that time, the core processor searches all interrupt levels which have
both: 1) pending interrupt flag, and 2) interrupt service enabled. The highest
priority interrupt among these is selected. The program then branches to the
location which is stored in the associated Interrupt Vector (Section 2.6.3,

rupt Vectors

). This location constitutes the start of the interrupt service routine.

Inter-

Instructions in the interrupt service routine are executed until the IRET (return)
instruction is encountered. Afterwards, any other pending interrupts will be
similarly serviced, in the order of their priority . Eventually , the program returns
to whatever point it was before the first interrupt service branch.

When an interrupt service branch is taken, the global interrupt enable is
automatically cleared by the core processor. This disables all further interrupt
service branches while still in the pending service routine. As a result, the
programmer must re-enable the interrupts globally using the INTE instruction.
If performed as the second-to-last instruction in the service routine, then no
nesting of multiple interrupts will occur. If, on the other hand, a nesting of
certain interrupts is desired, then the INTE instruction may be included as the
first instruction (or anywhere else) within the service routine.

2-24

When an interrupt service branch is taken, the processor core also clears
another status, namely , the respective bit in the IFR. This action automatically
communicates to the IFR that the current pending interrupt is now being
serviced. Once cleared, the IFR bit is ready to receive another SET whenever
the next trigger event occurs for that interrupt.

Note: Interrupt Service Branch

If the interrupt service branch is not enabled by the respective bit in the mask
register, then neither the global interrupt enable nor the respective flag bit is
cleared. No program vectoring occurs.

Figure 2–8 provides an overview of the interrupt control sequence. INT0 is the
highest priority interrupt, and INT7 is the lowest priority interrupt.

Figure 2–8. Interrupt Initialization Sequence

Interrupt Logic

INTD

instruction

INTE

instruction

CLEAR

SET

Global Interrupt Enable

CLEAR

CLEAR BIT

Associated With the Interrupt-Trigger Event

INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0

Interrupt / General Control Register (0x38)†

INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0

Interrupt-Trigger Event

• Internal Timer Underflow

• External Input Falling-Edge

• External Input Rising-Edge

• Software Write Instruction

INT Flag bits (IFR)

Interrupt Flag Register (0x39)

INT Mask bits (IMR)

Specific Enable for Interrupt Service

†

SET BIT

Interrupt

Service

Routine

(1 of 8)

INTE
IRET

†

The port-addressed write instruction (OUT) can be used to SET or CLEAR bits in the IFR and IMR.

Interrupt Service Branch

Highest Priority INT is Selected From

Among Those Flagged and Enabled.

Program Branches to Location

Stored in Interrupt Vector.

Interrupt Vector Storage

0x7FF0 0x7FF2 0x7FF4 0x7FF6
0x7FF1 0x7FF3 0x7FF5 0x7FF7

MSP50C614 Architecture

2-25

Timer Registers

In addition to being individually enabled, all interrupts must be GLOBALLY
enabled before any one can be serviced. Whenever interrupts are globally
disabled, the interrupt flag register may still receive updates on pending trigger
events. Those trigger events, however, are not serviced until the next INTE
instruction is encountered.

After an interrupt service branch, it is the responsibility of the programmer to
re-SET the global interrupt enable, using the INTE instruction.

2.8 Timer Registers

The C614 contains two identical timers, TIMER1 and TIMER2. Each includes
a period register and a count-down register. The period register (PRD1 or
PRD2) defines the initial value for the counter, and the count-down register
(TIM1 or TIM2) does the counting. When the count-down register decrements
to the value 0x0000, then the value currently stored in the period register is
loaded to the count-down register. The count-down register then resumes
counting again from that value.

For each TIMER, there is an interrupt-trigger event associated with the
TIMER’s underflow condition (the point of reaching 0x0000 and then re-setting
again). When enabled, the interrupt INT1 is triggered by the underflow of
TIMER1, and the interrupt INT2 is triggered by the underflow of TIMER2. INT1
and INT2 are the second and third-highest priority interrupts in the C614. Refer
to Section 2.7,
Section 2.6.3,

Interrupt Logic

Interrupt Vectors

, for a summary of the interrupt logic, and to

, for a listing of the interrupt vectors.

Both the period and the count-down registers are readable and writeable as
port-addressed registers:

2-26

PRD1 register
address 0x3A

TIM1 register
address 0x3B

Timer Registers

(16-bit wide location)

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

†

†

PPPPPPPPPPPPPPPP
TIMER1 Period

TTTTTTTTTTTTTTTT
TIMER1 Count-Down Triggers INT1 on underflow

PRD2 register
address 0x3E

TIM2 register
address 0x3F

†

TIMER1 may be associated with the comparator function, if the comparator enable bit is set. Refer to Section 3.3,
for details.

PPPPPPPPPPPPPPPP
TIMER2 Period

TTTTTTTTTTTTTTTT
TIMER2 Count-Down Triggers INT2 on underflow

P : period register (initial counter value)
T : count-down register (counts from the value in P)

0x0000 : default state of both registers after RESET LOW

Reading from either the PRD or the TIM returns the current state of the register.
This can be used to monitor the progress of the TIM register at any time.

Writing to the PRD register does not change the TIM register until the TIM
register has finished decrementing to 0x0000. The new value in the PRD
register is then loaded to the TIM register, and counting resumes from the new
value.

Note: Writing to the TIM Register

Writing to the TIM register causes the same value to be written to the PRD
register. In this case, the TIM register is immediately updated, and counting
continues immediately from the new value.

Comparator

,

Each TIMER decrements its count-down register at a fixed clock rate. The rate
is selectable between two existing clock sources: the reference oscillator or
1/2 Master Clock. The rate of the master clock (MC) is programmable. It is
determined by the value loaded to the PLL multiplier (Section 2.9.3,

Speed Control Register

). The source to the TIMER is therefore one-half the

Clock

frequency of the programmed master clock (1/2 MC). If, instead, the reference
oscillator is selected as the source to the TIMER, then the source is either a
resistor-trimmed oscillator (RTO) or a crystal oscillator (CRO). Both reference
oscillators are designed to run at a nominal 32 kHz. Refer to Section 2.9,

Clock Control

, for more information regarding the oscillator configuration and

clock programmability.

MSP50C614 Architecture

2-27

Timer Registers

Selection between the timer-source options is made using two control bits in
the interrupt/general control register (IntGenCtrl). The IntGenCtrl is a 16-bit
port-addressed register at 0x38. Clearing bit 8 selects 1/2 MC as the source
for TIMER1. Setting bit 8 selects the reference oscillator as the source for TIM­ER1. Similarly , clearing bit 9 of the IntGenCtrl selects 1/2 MC as the source for
TIMER2. Setting bit 9 selects the reference oscillator as the source for TIM­ER2. The default value after a RESET LOW is zero: select 1/2 MC as the
source.

Each of the TIMERs counts from the value stored in its period register to
0x0000. These maximum and minimum counts each receive a full clock cycle
from the TIMER source. This means that the true period of the TIMER, from
one underflow event to the next, is the value stored in the period register plus
one:

Time duration btwn. underflows = (value in PRD + 1) ÷ (frequency of T imer
Source)

TIMER1 and TIMER2 must be enabled for use. This is done at the IntGenCtrl
register. Bit 10 of the IntGenCtrl is the enable bit for TIMER1, and bit 11 is the
enable bit for TIMER2. Setting the enable bit enables the TIMER, i.e., starts
count-down running. Clearing the enable bit disables the TIMER, i.e., stops
the count-down. The default setting after a RESET LOW is zero: both TIMERs
disabled. Refer to Section 3.4,

Interrupt/General Control Register

, for sum-

mary information regarding the IntGenCtrl.

2-28

The TIMER enable bits may be used to start and stop the TIMERs repeatedly
in software. Switching the enable bit from 1 to 0 stops the TIMER, but the
current value in the count-down register is retained. When the enable bit is
subsequently switched from 0 to 1, count-down then resumes from the held
value. The following procedure outlines one (of many) possible ways to start
the TIMERs. TIMER2 is given as an example:

1) Select the TIMER2 clock source: 1/2 MC or RTO/CRO (bit 9 of the Int­GenCtrl, address 0x38).

2) Clear the TIMER2 enable (bit 11 in the IntGenCtrl).

3) Load the count-down register (TIM2) with the desired period value ahead­of-time. This prepares TIM2 for counting, and also loads the period regis­ter (PRD2) with its value.

4) Be sure the TIMER2 interrupt (INT2) has been enabled for service (set bit
2 of IntGenCtrl).

5) Flip the TIMER2 enable bit from 0 to 1, at the precise time you want count­ing to begin.

2.9 Clock Control

2.9.1 Oscillator Options

The C614 has two oscillator options available. Either option may be enabled
using the appropriate control bits in the clock speed control register
(ClkSpdCtrl). The ClkSpdCtrl is described in Section 2.9.3,

trol Register

The first oscillator option, called the resistor-trimmed oscillator (RTO), is useful
in low-cost applications where accuracy is less critical. This option utilizes a
single external resistor to reference and stabilize the frequency of an internal
oscillator. The oscillator is designed to run nominally at 32 kHz. It has a low V
coefficient and a low temperature coefficient (refer to Appendix C). The
reference resistor is mounted externally across pins OSCIN and OSC
RTO oscillator is insensitive to variations in the lead capacitance at these pins.
The required value of the reference resistor is 470 kΩ (1%).

The second oscillator option, CRO for crystal referenced, is a real time clock
utilizing a 32.768 kHz crystal. The crystal is mounted externally across pins
OSC

and OSC

IN

Clock Control

Clock Speed Con-

.

DD

. The

OUT

.

OUT

2.9.2 PLL Performance

A software controlled PLL multiplies the reference frequency (generated from
either RTO or CRO) by integer multiples. This higher frequency drives the
master clock which, in turn, drives the CPU clock. The master clock (MC)
drives the circuitry in the periphery sections of the C614. The CPU Clock drives
the core processor; its rate determines the overall processor speed. The multi­plier in the PLL circuit, therefore, allows the master clock and the CPU clock
to be adjusted between their minimum and maximum values.

For either oscillator option, the reference frequency (32.768 kHz) is multiplied
by four before it is accessed by the PLL circuit. The base frequency for the PLL,
therefore, is 131.07 kHz, and the multiplier operates in increments of this base
frequency. The minimum multiplication of the base frequency is 1, and the
maximum multiplication is 256. The resulting master clock frequency, there­fore, can be varied from a minimum of 131.07 kHz to a maximum of 33.554
MHz, in 131.07 kHz steps.

From the master clock to the CPU clock, there is a divide-by-two in frequency .
The CPU clock, therefore, can be set to run between 65.536 kHz and the maxi­mum achievable (see Appendix C), in 65.536 kHz steps.

MSP50C614 Architecture

2-29

Clock Control

The maximum required CPU clock frequency for the C614 is 8 MHz over the
entire VDD range. This rate applies to the speed of the core processor. Higher
CPU clock frequencies may be achieved, but these are not qualified over the
complete range of supply voltages in the guaranteed specification.

Figure 2–9. PLL Performance

Oscillator Reference

32 kHz

Resistor

Trimmed

RTO CRO

Selection Made in ClkSpdCtrl

Phase-Locked-Loop circuit

Multiplier Adjusted in ClkSpdCtrl

or

x4

PLL

x 1 ... x 256

crystal
referenced

Timer Source Option

Selected in IntGenCtrl

1
0

1
0

÷2

CPU Clock

(F

MAX

MC

÷2

= 8 MHz)

Master Clock : Runs Periphery

131.07 kHz ... 33.554 MHz

Core-Processor Speed

65.536 kHz ... F

TIMER2

MAX

TIMER2

2.9.3 Clock Speed Control Register

The ClkSpdCtrl is a 16-bit memory mapped register located at address 0x3D.
The reference oscillator (RTO or CRO) is selected by setting one of the two
control bits located at bits 8 and 9. Setting bit 8 configures the C614 for the RTO
reference option and simultaneously starts that oscillator. Setting bit 9
configures the C614 for the CRO reference option and simultaneously pulses
the crystal, which starts that oscillator.

2-30

Clock Control

Note: ClkSpdCtrl Bits 8 and 9

When bit 8 is set in the ClkSpdCtrl register, the crystal oscillator bit (bit 9) be­comes the least significant bit of the 6-bit resistor trim value. Thus, bits 15–1 1
and 9 make up the 6-bit resistor trim value. For example, if the ClkSpdCtrl
register is 00010X11XXXXXXXX (X means don’t care, bold numbers are re-
sistor trim bits), then the resistor trim value is equal to five.

The default value of the ClkSpdCtrl is 0x0000, which means that neither option
is enabled by default. Immediately after a RESET LOW-to-HIGH, and
regardless of whether a resistor or a crystal is installed across OSCIN/
OSC

, the C614 does not have a reference oscillator running. In the

OUT

absence of a reference, however, the PLL still oscillates; it bottoms-out at a
minimum frequency . The master clock, in turn, runs at a very slow frequency
(less than 100 kHz) in the absence of a reference oscillator. Under this
condition, program execution is supported at a slow rate until one of the two
references (RTO or CRO) is enabled in software. (Refer to Chapter 8,

MSP50C614 Electrical Specifications

, for a more precise characterization of

the master clock rate under these conditions.)
Once a reference oscillator has been enabled, the speed of the master clock

(MC) can be set and adjusted, as desired. Bits 7 through 0 in the ClkSpdCtrl
constitute the PLL multiplier (PLLM). The value written to the PLLM controls
the effective scaling of the MC, relative to the 131.07 kHz base frequency. A
0 value in PLLM yields the minimum multiplication of 1, and a 255 value in
PLLM yields the maximum multiplication of 256. The resulting MC frequency ,
therefore, is controlled as follows:

MC Master clock frequency kHz = (PLLM register value + 1) × 131.07 kHz
CPU Clock frequency kHz = (PLLM register value + 1) × 65.536 kHz

The configuration of bits in the clock speed control register appears below:

ClkSpdCtrl register
address 0x3D (16-bit wide location)
WRITE only 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

T5 T4 T3 T2 T1 I C or T0 R MMMMMMMM
T : RTO oscillator-Trim adjust R : enable Resistor-trimmed oscillator
I : Idle State clock Control M : PLLM multiplier bits for MC
C : enable Crystal oscillator

(or T0 if R is set

0x0000 : default state after RESET LOW

MSP50C614 Architecture

2-31

Clock Control

Bit 10 in the ClkSpdCtrl is idle state clock control. The level of deep-sleep
generated by the IDLE instruction is partially controlled by this bit. When this
bit is cleared (default setting), the CPU Clock is stopped during the sleep, but
the MC remains running. When the idle state clock control bit is set, both the
CPU clock and the MC are stopped during sleep. Refer to section 2.12 for more
information regarding the C614’s reduced-power modes.

Note: Reference Oscillator Stopped by Programmed Disable

If the reference oscillator is stopped by a programmed disable, then, on re­enable, the oscillator requires some time to restart and resume its correct fre­quency. This time imposes a delay on the core processor resuming full­speed operation. The time-delay required for the CRO to start is GREA TER
than the time-delay required for the RTO to start.

2.9.4 RTO Oscillator Trim Adjustment

Bits 15 through 11 and bit 9 (6 bits total) in the ClkSpdCtrl effect a software
control for the RTO oscillator frequency. The purpose of this control is to trim
the RTO to its rated (32 kHz) specification. The correct trim value varies from
device to device. The user must program bits 15 through 1 1 and 9, in order to
achieve the 32-kHz specification within the rated tolerances. Texas
Instruments provides the trim value to the programmer of the P614 part with
a sticker on the body of the chip. For the C614 part, the correct trim value is
located at I/O location 0x2Fh.

RTRIM Register (Read Only) (Applies to MSP50C614 Device Only)

I/O Address 0x2Fh (17-bit wide location)

16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

RRRRRRRRRRRT5T4T3T2T1T0

T: RTO oscillator-trim storage (device specific)
R: reserved for Texas Instruments use

ClkSpdCtrl Value Copied (Shaded)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

T5 T4 T3 T2 T1 I T0 1 M7 M6 M5 M4 M3 M2 M1 M0

When selecting and enabling the RTO oscillator ,therefore, the bits at positions
05 through 01 should be read from I/O location 0x2F (MSP50C614 device
only), then copied to the ClkSpdCtrl trim adjust (bits 15 through 11 of control
register 0x3D), and bit 0 of 0x2F I/O port should be copied to bit 9 of ClkSpdCtrl
register. The bit ordering is the same; bit 04 of I/O 0x2F copies to bit 15 of
register 0x3D. Likewise, bit 00 of I/O 0x2F copies to bit 11 of register 0x3D.

2-32

Execution Timing

However, the general specification of the adjustment can be useful in certain
circumstances. For example, the adjustment can be used to obtain a program­matic increase or decrease in the speed of the RTO reference. The default val­ue for the adjustment, after RESET low, is all zeros. The zero value generates
the slowest programmable rate for the RTO reference. The maximum value,
0x3F , generates the fastest programmable rate for the RTO reference. The full
range from 0x00 to 0x3F , ef fects an approximate +62% change (based on the
RTO resistor value specification). The change is nonlinear and nonlinear it
changes from one device to another.

On the P614 part, the above method does not cause in the correct trim value
to be loaded in ClkSpdCtrl. MSP50P614 is an EPROM device. Any
preprogrammed value is erased when the chip goes through a UV erase
procedure. The RTO trim value must, therefore, be computed separately for
each chip. RTO trim values differ from one chip to another, is identical for the
same chip.

Note: Register Trim Value

A resistor trim value is only needed when the resistor trimmed oscillator
(RTO) is used. The MSP50P614 device must determine the trim value sepa­rately and use this value in the ClkSpdCtrl register bits 15–1 1 and 9, but C614
device needs to copy bit 0 of I/O location 0x2F to bit 9 of the ClkSpdCtrl regis­ter and bits 5 through 1 to bits 15 through 11 of ClkSpdCtrl register.

This software-controlled trim for the RTO is not a replacement for the external
reference-resistor mounted at pins OSCIN and OSC
adjustment has no effect on the rate of the CRO reference oscillator.

2.10 Execution Timing

For executing program code, the C614’s core processor has a three-level
pipeline. The pipeline consists of instruction fetch, instruction decode, and
instruction execution. A single instruction cycle is limited to one program Fetch
plus one data memory read or write. The master clock consists of two phases
with non-overlap protection. A fully static implementation eliminates pre­charge time on busses or in memory blocks. This design also results in a very
low power dissipation. Figure 2–9 illustrates the basic timing relationship
between the master clock and the execution pipeline.

. Also, note that this

OUT

MSP50C614 Architecture

2-33

Reduced Power Modes

Figure 2–10. Instruction Execution and Timing

CLOCK

FETCH

DECODE

EXEC

DATA ADD

PC ADD

N

N–1

N–2

N

N+1 N+2

N N+1

N–1 N

N–1

N+1 N+2

2.11 Reduced Power Modes

The power consumption of the C614 is greatest when the DAC circuitry is
called into operation, i.e., when the synthesizer speaks. There are, however,
a number of reduced power modes (sleep states) on the C614 which may be
engaged during quiet intervals.

The performance and flexibility of the reduced power modes make the C614
ideal for battery powered operation. Refer to Chapter 8,

Electrical Specifications

including the acceptable power-supply ranges.

N N+1

N+3

N+2

N+1

N+3

N+4

N+3

N+2

N+2

N+4

N+3

N+5 N+6

N+4 N+5

N+3 N+4

N+4 N+5

N+5 N+6

N+7

N+5

N+7

MSP50C614

, for a full description of the electrical characteristics,

2-34

The reduced power state on the C614 is achieved by a call to the IDLE
instruction. The idle state is released by some interrupt event. Different modes
(or levels) of reduced-power are brought about by controlling a number of
different core and periphery components on the device. These components
are independently enabled/disabled before engaging the IDLE instruction.
The number of subsystems left running during sleep directly impacts the
overall power consumption during that state. The various subsystems that
determine (or are affected by) the depth of sleep include the:

-

Processor core, which is driven by the CPU clock

-

PLL clock circuitry

-

PLL reference oscillator

-

C614 periphery, which is driven by the master clock

-

TIMER1 and TIMER2

-

PDM pulsing

Reduced Power Modes

The deepest sleep achievable on the C614, for example, is a mode where all
of the previously listed subsytems are stopped. In this state, the device draws
less than 10 µA of current and obtains the greatest power savings. It may be
awakened from this state using an external interrupt (input port).

A number of control parameters determine which of the internal components
are left running after the IDLE instruction. In most cases, the states of these
controls may be mixed in any combination. There are three combinations,
however, which are primarily useful. The three modes (light, mid, and deep
sleep) are executed through the independent control of two bits: 1) the idle
state clock control, and 2) the reference oscillator enable. The other pertinent
controls simply enhance the performance of the modes dictated by these two.
Table 2–3 gives a listing of all of the controls which should be maintained by
the programmer before engaging the IDLE instruction. In some cases, it will
be impossible to wake from sleep unless certain controls are set appropriately
before going to sleep. (In those cases, only the hardware RESET low-to-high
will bring the device back into its normal operating state.)

The top row in Table 2–3 lists the first of the two primary controls, namely, the
idle state clock control. The idle state clock control determines the status of the
master clock (MC) during sleep. Setting the idle state control causes the CPU
clock, the PLL clock circuitry, and the MC to stop after the next IDLE
instruction. Clearing the idle state control causes only the CPU clock to stop
after IDLE. The PLL clock circuitry governs the MC and determines its rate.
Whenever the PLL circuitry is suspended, therefore, the MC stops. The idle
state clock control is accessed at bit 10 in the ClkSpdCtrl register. (Refer to
Section 2.9.3,

Clock Speed Control Register

, for more information.)

The reference oscillator enable is the other control which selects between the
three reduced power modes listed in T able 2–3. This control may be one of two
bits, depending on which oscillator reference is implemented in circuitry . Refer
to Section 2.9.3,

Clock Speed Control Register

. When using the
resistor-trimmed oscillator (RTO), the reference oscillator enable appears as
bit 8 in the ClkSpdCtrl register. When using the crystal-referenced oscillator
(CRO), the reference oscillator enable appears as bit 9 in the ClkSpdCtrl
register. If both bits 8 and 9 are clear, then no reference oscillator is enabled.
If either of bits 8 or 9 are set, then the reference oscillator enable is considered
set. This enables the PLL circuitry to regulate to the reference frequency, 32
kHz (assuming the idle state clock control is clear). Whichever state the
reference oscillator is in before idle, it remains in that state (running or stopped)
after idle. If the reference oscillator is left running during sleep, however, it
comes at a cost to power consumption. (This may be a necessary cost if, in
your application, elapsed time needs to be monitored during sleep.)

MSP50C614 Architecture

2-35

Reduced Power Modes

The power consumed during sleep when the RTO oscillator is left running is

greater

than the power consumed during sleep when the CRO oscillator is left

running.
If the idle state clock control is clear, then the PLL circuitry , active during sleep,

will attempt to regulate the MC to whatever frequency is programmed in the
PLL multiplier (see Section 2.9.3,

Clock Speed Control Register

). The MC con­tinues to run at this frequency , even during sleep, provided that the reference
oscillator is enabled.

If the idle state clock control is set, then neither the MC, CPU clock, nor the
TIMER clocks run during sleep, unless the TIMER source is linked to the
reference oscillator (Section 2.8, Time Registers). These relationships are
shown explicitly, as a function of the reduced power mode, in Table 2–4.

Because the DAC circuitry is the single most source of power consumed on
the C614, it is important to disable the DAC entirely before engaging any IDLE
instruction. This is accomplished at the DAC control register, address 0x34.
Refer to Section 3.2.2,

DAC Control and Data Registers

.

The ARM bit is another important control to consider before engaging the
reduced power mode. It is recommended that the ARM bit be cleared
whenever the idle state clock control is clear, and set whenever the idle state
clock control is set Table 2–3. The set ARM bit causes an asynchronous
response to all programmable interrupts when in the sleep state. (The cleared
ARM bit yields the standard synchronous response at all times.) Affected
interrupts include those tied to TIMER1 and TIMER2, as well as those tied to
the inputs at Ports F, D

, D3, D4, and D5. The advantage to having the ARM

2

bit set is that the device may be awakened by one of these interrupts, even
when the PLL clock circuitry is stopped in sleep (by virtue of the idle state
control). The disadvantage of the asynchronous response, however, is that it
can render irregularities in the timing of response to these same inputs.

2-36

Note: Idle State Clock Control Bit

If the idle state clock control bit is set and the ARM bit is clear, the only event
that can wake the C614 after an IDLE instruction is a hardware RESET low­to-high. When at sleep, the device will not respond to the input ports, nor to
the internal timers.

Reduced Power Modes

Table 2–3. Programmable Bits Needed to Control Reduced Power Modes

→ deeper sleep … relatively less power →

Control Bit

Idle state clock control
bit 10
ClkSpdCtrl register (0x3D)

Enable reference oscillator
bit 09 : CRO or
bit 08 : RTO
ClkSpdCtrl register (0x3D)

ARM
bit 14
IntGenCtrl register (0x38)

Enable PDM pulsing
bit 02
DAC Control register (0x34)

IDLE instruction
(executes the mode)

PLL multiplier
bits 07 through 00
ClkSpdCtrl register (0x3D)

Label for
Control Bit

A 0 1 1

B 1 1 0

C 0 1 1

D Should be cleared before any IDLE instruction.

E Same instruction is used to engage any of the modes.

F Programmed value is 0 … 255 .

LIGHT MID DEEP

MSP50C614 Architecture

2-37

Reduced Power Modes

Table 2–4. Status of Circuitry When in Reduced Power Modes (Refer to Table 2–3)

→ deeper sleep … relatively less power →

Component

CPU clock
(processor core)

PLL clock circuitry A, E running stopped stopped
Master clock (MC) status

(C614 periphery)
MC rate B, F 131 kHz … 34 MHz — —
Synchrony of external interrupts C, E Synchronous Asynchronous Asynchronous
PDM pulsing D stopped stopped stopped
TIMER1 or TIMER2 status

• Assuming TIMER is enabled

1) TIMER source = 1/2 MC

2) TIMER source = RTO or CRO

Determined
by Controls

E stopped stopped stopped

A, E running stopped stopped

A, B, E

LIGHT MID DEEP

1) running

2) running

1) stopped

2) running

1) stopped

2) stopped

If the reference oscillator is stopped by a programmed disable or by an IDLE
instruction, then, on re-enable or wake-up, the oscillator requires some time
to restart and resume its correct frequency . This time imposes a delay on the
core processor resuming full-speed operation. The time-delay required for the
CRO to start is

greater

than the time-delay required for the RTO to start.

2-38

There are a number of ways to wake the C614 from the IDLE-induced sleep
state. The various options are summarized, as a function of the reduced power
mode, in T able 2–5. Naturally , the RESET event (happens after the RESET pin
has gone low-to-high) causes an immediate escape from sleep; whereby , the
program counter assumes the location stored in the RESET interrupt vector.
The RESET escape from sleep is always enabled, regardless of the depth of
sleep or the state of programmable controls.

The more functional methods available for waking the device are: 1) the
Internal TIMER interrupt, and 2) the external input-port interrupt. For either of
these options to work, the respective bit in the interrupt mask register (address
0x38) must be set to enable the associated interrupt service. If the appropriate
IMR bit is not set before the IDLE instruction, then the interrupt-trigger event
will not be capable of waking the device from sleep. Note also the state of the
idle state clock control bit and the ARM bit, if you expect to wake-up using
either type of interrupt (internal or external). In most cases, the state of these
bits should coincide Table 2–3.

Reduced Power Modes

The interrupt-trigger event associated with each of the two internal TIMERs is
the underflow condition of the TIMER. In order for a TIMER underflow to occur
during sleep, the TIMER must be left running before going to sleep. In certain
cases, however, the act of going to sleep can bring a TIMER to stop, thereby
preventing a TIMER-induced wake-up. The bottom row of T able 2–4 illustrates
the various conditions under which the TIMER will continue to run after the
IDLE instruction. Not that the reduced power mode DEEP leaves both TIMERs
stopped after IDLE. This mode cannot, therefore, be used for a timed wake-up
sequence.

Table 2–5. How to Wake-Up from Reduced Power Modes (Refer to Table 2–3 and

Table 2–4)

→ deeper sleep … relatively less power →

C

C

D

Determined
by Controls

A, B, C

C

D

Event

Timer interrupts
TIMER1 and TIMER2

• Assuming respective IMR bit is set

• Assuming ARM bit is set as in

External interrupts
Port F and D

• Assuming respective IMR bit is set

• Assuming ARM bit is set as in

RESET none

DAC Timer

• Assuming PDM bit is clear as in

2,3,4,5

(if input)

The external interrupt is the other programmable option for waking the C614
from sleep. The associated interrupt-trigger event is, in some cases, a rising­edge at the input port; in some cases it is a falling-edge. Refer to Section 3.1.5,

Internal and External Interrupts

also the comparator driven interrupts described in Section 3.3,
The input ports which are supported by external interrupt include the entire F
Port, and, when programmed as inputs, Ports D2, D3, D4, and D5. Refer to Sec­tion 3.1,

I/O

, for a description of the various I/O configurations.

LIGHT MID DEEP

If TIMER is running,

then Underflow wakes device.

Rising-Edge, or Falling-Edge,

as appropriate, wakes device.

RESET LOW-to-HIGH always wakes device.

No wake-up from DAC Timer.

No wake-up

from TIMER.

, for a full description of these events. Consider

Comparator

.

Under normal operation the DAC timer, when IMR enabled, triggers an
interrupt on underflow. Before any IDLE instruction, however, the entire DAC
circuitry should be disabled. This ensures the effectiveness of the reduced
power mode and prevents any wake-up from the DAC timer.

MSP50C614 Architecture

2-39

Reduced Power Modes

In order to wake the device using a programmable interrupt, the interrupt mask
register must have the respective bit set to enable interrupt service (see Sec­tion 2.7,

Interrupt Logic

). In some cases, the ARM bit must also be set, in order

for the interrupts to be visible during sleep Table 2–3.
After the C614 wakes from sleep, the program counter assumes a specific

location, resuming normal operation of the device. Normally, the destination
of the program on wake-up is the interrupt service routine associated with the
interrupt which initiated the wake-up. The start of the interrupt service routine
is defined by the program location stored in the respective interrupt vector (see
Section 2.6.3,

Interrupt Vectors

). This wake-up response requires that the

global interrupt enable is set before going to sleep (use the INTE instruction).
If the global interrupt enable is CLEAR before going to sleep, then the

programmed interrupt can still wake the device, provided that the respective
IMR and ARM bits are set as in Table 2–5 Instead of waking to the interrupt
service routine, however, the program counter assumes the location
immediately following the IDLE instruction which initiated the sleep. This type
of wake-up response may be useful for putting the C614 into a hold sleep;
whereby, any number of programmable interrupts can wake the device, yet
they all return the program to the very same location. In order to accomplish
this, each of the necessary interrupts should be enabled in the IMR. The global
interrupt enable, however, is cleared using the INTD instruction. T able 2–6 lists
the various possible destinations of the program counter on wake-up, provided
that the wake-up is bound to occur under the given conditions.

Table 2–6. Destination of Program Counter on Wake-Up Under Various Conditions

State of Interrupt Controls
before IDLE Instruction

• Global interrupt enable is SET

• Respective IMR bit is SET

• Global interrupt enable is CLEAR

• Respective IMR bit is SET

• Global interrupt enable is SET

• Respective IMR bit is CLEAR

2-40

Assuming Wake-Up can occur…
Destination of Program Counter after Wake-Up

Program counter goes to the location stored in the interrupt vector
associated with the waking Interrupt.

Program counter goes to the next instruction immediately following
the IDLE which initiated sleep.

Wake-up cannot occur from the programmed Interrupt under these
conditions.

If RESET low-to-high occurs, then program goes to the location
stored in the RESET interrupt vector.

Chapter 3

Peripheral Functions

This chapter describes in detail the MSP50C614 peripheral function, i.e., I/O
control ports, general purpose I/O ports, interrupt control registers, compara­tor and digital-to-analog (DAC) control mechanisms.

Topic Page

3.1 I/O . . . 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2 Digital-to-Analog Converter (DAC) 3–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3 Comparator 3–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4 Interrupt/General Control Register 3–17. . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5 Hardware Initialization States 3–19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-1

I/O

3.1 I/O

The C614 has 64 input-output pins. Forty of these are software configurable as
either inputs or outputs. Eight are dedicated inputs, and the remaining sixteen
are dedicated outputs.

3.1.1 General-Purpose I/O Ports

The forty configurable input/output pins are organized in 5 ports, A,B,C,D, and
E. Each port is one byte wide. The pins within these ports can be individually
programmed as input or output, in any combination. The selection is made by
clearing or setting the appropriate bit in the associated control register (Control
A, B, C, D, or E). Clearing the bit in the control register renders the pin as a
high-impedance input. Setting the control bit renders the pin as a totem-pole­output.

When configured as an input, the data presented to the input pin can be read
by referring to the appropriate bit in the associated data register (Data A, B,
C, D, or E). This is done using the IN instruction, with the address of the data
register as an argument.

When configured as an output, the data driven by the output pin can be
controlled by setting or clearing the appropriate bit in the associated data
register. This is done using the OUT instruction, with the address of the data
register as an argument.

3-2

Port A Port B Port C Port D Port E

Control register address
Possible control values 0 = High-Z INPUT 1 = TOTEM-POLE OUTPUT
V alue after RESET low 0 = High-Z INPUT
Data register address 0x00h 0x08h 0x10h 0x18h 0x20h
Possible input data values Low = 0 High = 1 (don’t care on write)
Possible output data values 0 = Low 1 = High

†

Each of these I/O ports is only 8 bits wide. The reason for the 4-byte address spacing is so that
instructions

these registers.

with limited addressability (such as memory transfers) can still access

0x04h†0x0Ch 0x14h 0x1Ch 0x24h

Note: Reading the Data Register

Whether configured as input or as output, reading the data register reads the
actual state of the pin.

The programmable I/O are initialized to a known state by cycling the RESET
pin low-to-high. The state of the control registers during and after RESET low

I/O

is 0x00 (all inputs). The state of the data registers after RESET low is unknown
(input state provided by external hardware).

The 8-bit width is the true size of the mapped location. This is independent of
the address spacing, which is greater than 8-bits. When writing to any of the
locations in the I/O address map, therefore, the bit-masking need only extend
across 8 bits. Within a 16-bit accumulator, the desired bits should be
right-justified. When reading from these locations to a 16-bit accumulator, the
IN instruction automatically clears the extra bits in excess of 8. The desired bits
in the result will be right-justified within the accumulator.

The following table shows the bit locations of the I/O port mapping:

(8-bit wide location)

07 06 05 04 03 02 01 00

A port data register address 0x00. . . . . A7 A6 A5 A4 A3 A2 A1 A0

A port control register address 0x04. . . C C C C C C C C

B port data register address 0x08. . . . . B7 B6 B5 B4 B3 B2 B1 B0

B port control register address 0x0C. . . C C C C C C C C

C port data register address 0x10. . . . . C7 C6 C5 C4 C3 C2 C1 C0

C port control register address 0x14. . . C C C C C C C C

D port data register address 0x18. . . . . D7 D6 D5 D4 D3 D2 D1 D0

D port control register

E port data register address 0x20. . . . . E7 E6 E5 E4 E3 E2 E1 E0

E port control register address 0x24. . . C C C C C C C C

A7, B7, C7, D7, E7 : data register

†

Ports D4 and D5 may be dedicated to the Comparator function, if the Comparator Enable bit is
set. If so, then bits 4 and 5 of the D port Control register

3.3,

Comparator

†

address 0x1C. . C C C C C C C C

C : control register (0 = IN, 1 = OUT)

0x00 : state of control register after RESET low

must

, for details.

be CLEAR. Please refer to Section

Port D0 is connected to the branch condition COND1. Port D1 is connected to
the branch condition COND2, assuming the comparator is disabled. Please
refer to Section 3.1.4,

Branch on D Port

, (and to Section 3.3,

Comparator

) for
more information. External interrupts can be caused by transitions on ports D2,
D3, D4, and D5. The interrupts associated with the D port are supported
whether those pins are programmed as inputs or as outputs.

Peripheral Functions

3-3

I/O

3.1.2 Dedicated Input Port F

Port F is an 8-bit wide input-only port. The data presented to the input pin can
be read by referring to the appropriate bit in the F port data register, address
0x28. This is done using the IN instruction, with the 0x28 address as an
argument. The state of the F port data registers after RESET low is unknown
(input state provided by external hardware)

Each of the pins at port F has a programmable pull-up resistor. The resistance
of these pullups is at least 100 kΩ. All eight pullup resistors can be enabled by
setting the enable pullup (EP) in the interrupt/general control register (Int­GenCtrl). The address of the IntGenCtrl is 0x38, and the location of the EP bit
is 12. Clearing the EP bit disables the eight pullups, and setting the EP bit en­ables the eight pullups. After RESET low, the default setting for the EP bit is
0 (F-port pullups disabled).

Input Port F

Data register address

Possible input data values Low = 0 High = 1

Possible output data values N/A

V alue after RESET low Pullup resistors DISABLED

0x28h

When reading from the 8-bit F-port data register to a 16-bit accumulator, the
IN instruction automatically clears the extra bits in excess of 8. The desired bits
in the result will be right-justified within the accumulator.

The following table shows the bit locations of the port F address mapping:

F port Input Data register
address 0x28h
READ only

(8-bit wide location)
07

06 05 04 03 02 01 00

F7 F6 F5 F4 F3 F2 F1 F0

The external interrupt INT5 is triggered by a falling-edge event on any of the
eight port-F input pins (see Section 3.1.5,

Internal and External Interrupts

Specifically , INT5 is triggered if all eight port-F pins are held high, and then one
or more of these pins is taken low. Port F, therefore, is especially useful as a
key-scan interface.

).

3-4

3.1.3 Dedicated Output Port G

Port G is a 16-bit wide output-only port. The output drivers have a T otem-Pole
configuration. The data driven by the output pin can be controlled by setting
or clearing the appropriate bit in the G port Data register, address 0x2C. This
is done using the OUT instruction, with the 0x2C address as an argument. Af­ter RESET low, the default settings for the G port outputs are 0 (logical low).

I/O

Totem-Pole Output Port G

The following table shows the bit locations of the port G address mapping:

G port Data
address 0x2C
read and write

Data register address

Possible input data values N/A

Possible output data values 0 = Low 1 = High

V alue after RESET low 0 = Low

(16-bit wide location)
15

14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
G15 G14 G13 G12 G11 G10 G9 G8 G7 G6 G5 G4 G3 G2 G1 G0
0x0000 : default state of data register after RESET low

0x2Ch

Peripheral Functions

3-5

I/O

3.1.4 Branch on D Port

Instructions exist to branch conditionally depending upon the state of ports D
and D1. These conditionals are COND1 and COND2, respectively . The condi­tionals are supported whether the D

and D1 ports are configured as inputs or

0

as outputs. The following table lists the four possible logical states for D0 and
D1, along with the software instructions affected by them.

D0 = 1 COND1 = TRUE. . . CIN1

CNIN1

JNIN1

D0 = 0 COND1 = FALSE. . . CIN1

CNIN1

JNIN1

† D1 = 1 COND2 = TRUE. . . CIN2

CNIN2

JNIN2

† D1 = 0 COND2 = FALSE. . . CIN2

CNIN2

JNIN2

†

COND2 may be associated instead with the comparator function, if the comparator Enable bit
is set. Please refer to Section 3.3,

Comparator

has its conditional call taken.
has its conditional call ignored.

JIN1

has its conditional jump taken.
has its conditional jump ignored.

has its conditional call ignored.
has its conditional call taken.

JIN1

has its conditional jump ignored.
has its conditional jump taken.

has its conditional call taken.
has its conditional call ignored.

JIN2

has its conditional jump taken.
has its conditional jump ignored.

has its conditional call ignored.
has its conditional call taken.

JIN2

has its conditional jump ignored.
has its conditional jump taken.

, for details.

0

3.1.5 Internal and External Interrupts

INT3, INT4, INT6, and INT7 are external interrupts which may be triggered by
events on the PD2, PD3, PD4, and PD5 pins. These interrupts are supported
whether the D-port pins are programmed as inputs or outputs. (When
programmed as an output, the pin effectively triggers a software interrupt.)

INT5 is an external interrupt triggered by a falling-edge event on any of the
F-port inputs. It is triggered if all eight port-F pins are held high, and then one
or more of these pins is taken low.

Only the transition from 0xFFh (all high) to (one or more pins) low will trigger
the INT5 event. If any F-port pin is continuously held low and another is toggled
high-to-low, no interrupt is detected at the toggling pin. After all F-port pins
have been brought high again, then it is possible for a new INT5 trigger to
occur.

INT0 is an internal interrupt (highest priority) which is triggered by an underflow
condition on the DAC Timer (see Section 3.2.2,

3-6

DAC Control and Data

I/O

Registers

). INT1 and INT2 are high-priority , internal interrupts triggered by the
underflow conditions on TIMER1 and TIMER2, respectively. Please refer to
Section 2.8,

Timer Registers

, for a full description of the TIMER controls and

their underflow conditions.
When properly enabled, any of these interrupts may be used to wake the de-

vice up from a reduced-power state. In a deep-sleep state, they can also be
used to wake the device when used in conjunction with the ARM bit. Please
refer to Section 2.11,

Reduced Power Modes

, for information regarding the

C614’s reduced power modes.
A summary of the interrupts is given in Table 3–1.

Table 3–1. Interrupts

Interrupt Vector Source Trigger Event Priority Comment

INT0 0x7FF0 DAC Timer Timer underflow Highest Used to synch. speech data
INT1 0x7FF1 TIMER1 T imer underflow 2

INT2 0x7FF2 TIMER2 T imer underflow 3
INT3 0x7FF3 PD
INT4 0x7FF4 PD
INT5 0x7FF5 All port F Any falling edge 6

2
3

Rising edge 4

Falling edge 5

nd

rd
th

Port D2 goes high

th

Port D3 goes low

th

Any F port pin goes from all-high to low

†

INT6
INT7

†

INT6 and INT7 may be associated instead with the Comparator function, if the Comparator Enable bit has been set.

0x7FF6 PD

†

0x7FF7 PD

4
5

Rising edge 7

Falling edge Lowest Port D5 goes low

th

Port D4 goes high

Note: Interrupts in Reduced Power Mode

An interrupt may be lost if its event occurs during power-up or wake-up from
a reduced power mode. Also, note that interrupts are generated as a divided
signal from the master clock. The frequency of the various timer interrupts
will therefore vary, depending upon the operating master clock frequency.

Peripheral Functions

3-7

Digital-to-Analog Converter (DAC)

3.2 Digital-to-Analog Converter (DAC)

The C614 incorporates a two-pin pulse-density-modulated DAC which is
capable of driving a 32 Ω loudspeaker directly. To drive loud speakers other
than 32 Ω, an external impedance-matching circuit is required.

3.2.1 Pulse-Density Modulation Rate

The rate of the master clock (MC) determines the pulse-density-modulation
(PDM) rate, and this governs the output sampling-rate and the achievable
DAC resolution. In particular, the sampling rate is determined by dividing the
PDM rate by the required resolution:

Output sampling rate = PDM Rate ÷ 2

PDM Rate #DAC resolution bits
Set in ClkSpdCtrl register Set in DAC control register
Address 0x3D Address 0x34

For example, a 9 bit PDM DAC at 8 kHz sampling rate requires a PDM rate of

4.096 MHz.

(# DAC resolution bits)

There are four sampling rates which may be used effectively within the
constraints of the C614 and the various software vocoders provided by T exas
Instruments. These are: 7.2 kHz, 8 kHz, 10 kHz, and 11.025 kHz. Other
sampling rates, however, may also be possible.

From the MC to the PDM clock, there is an
This option is controlled by the PDM clock divider in the interrupt/general
control register. This means that the PDM rate can be set to run between

131.07 kHz and 33.554 MHz in 131.07 kHz steps (the same as the MC). Or,
the PDM rate can be set to run between 65.536 kHz and the maximum
achievable CPU frequency (see Chapter 8,

Specifications

of these two ranges apply . Within these ranges, it is the PLLM which sets the
rate: ClkSpdCtrl, 0x3D. Refer to Section 3.2.3,
information regarding the PDM clock divider and the available combinations
of CPU clock rates vs sampling rates. (Section 2.9.3,

Register

) in 65.536 kHz steps. The PDM clock divider determines which

, has more details regarding the PLLM.)

3.2.2 DAC Control and Data Registers

The resolution of the PDM-DAC is selected using the control bits in the DAC
control register (address 0x34). The available options are 8, 9, or 10 bits of res­olution. Bits 0 and 1 in the DAC control register control this option:

optional

divide-by-two in frequency .

MSP50C614 Electrical

PDM Clock Divider

, for more

Clock Speed Control

3-8

Digital-to-Analog Converter (DAC)

DAC Control register
Address 0x34 (4-bit wide location)

02 01 00

03

Set DAC resolution to 8 bits:
Set DAC resolution to 9 bits:
Set DAC resolution to 10 bits:

DM : Drive Mode selection (0 = C3x style : 1 = C5x style)
E : pulse-density-modulation Enable (overall DAC enable)
0x0 : default state of register after RESET low

DM E 0 0
DM E 0 1
DM E 1 0

Bit 2 in the DAC control register is used to enable/disable the pulse-density
modulation. This bit must be set in order to enable the overall functionality of
the DAC. After RESET is held low, the default state of bit 2 is clear . In this state,
the output at the DAC pins is guaranteed to be zero (no PDM pulsing). During
DAC activity, the PDM enable bit may also be toggled at any time to achieve
the zero state. In other words, toggling the PDM enable bit from high-to-low-to­high brings the DAC output to the known state of zero.

Note: PDM Enable Bit

By default, the PDM enable bit is cleared: DAC function is off.

Data values are output to the DAC by writing to the DAC data register, address
0x30. The highest-priority interrupt, INT0, is generated at the sampling rate
governed by the ClkSpdCtrl and the DAC control register. The program in
software is responsible for writing a correctly-scaled DAC value to the DAC
data register, in response to each INT0 interrupt. The register at 0x30 is 16-bits
wide. The data is written in sign-magnitude format. Bit 15 of the register is the
sign bit. Bits 14 and 13 are the overflow bits. Bits 12 through 3 are the
data-value bits: The MSB is bit 12, and the LSB is bit 5, 4, or 3, depending on
the resolution.

DAC Data register
Address 0x30 (16-bit wide location)
Write Only 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
10 bit DAC resolution:

9 bit DAC resolution:
8 bit DAC resolution:

S : Sign bit M : Most-significant data value D ; Data (magnitude)
O : Overflow bits L : Least-significant data value X : ignored bits

S OOMDDDDDDDDLXX X
S OOMDDDDDDDL XXXX
S OOMDDDDDDLXXXXX

The overflow bits function in different ways, depending on the drive mode
selected. The two DAC drive modes are informally named

Peripheral Functions

C3x style

and

C5x

3-9

Digital-to-Analog Converter (DAC)

style

. Their selection is made at bit 3 of the DAC control register (0x34). The

C3x style

bit 3. The default value of the selection is zero which yields the
The overflow bits appear in the DAC data register (14 and 13) to the left of the

MSB data bit (12). In the
buffer to handle overflow in the value field (bits 12…3). Any magnitude written
to the value field which is greater than 1023 (up to the limit 4095) lands a 1 in
the overflow. The overflow state (when a 1 appears in either bit 13 or 14) yields
the maximum PDM saturation and delivers the maximum possible current
drive to the loudspeaker. The overflow bits thus help to ensure that the audible
artifacts of

3.2.3 PDM Clock Divider

The pulse-density-modulation rate is determined by the master clock. The
PDM rate may be set equal to the rate of the MC, or it may be set at one-half
the rate of the MC. This option is controlled by the PDM clock divider (PDMCD)
in the interrupt/general control register (IntGenCtrl). The PDMCD is located at
bit 13 in IntGenCtrl (address 0x38).

is selected by clearing bit 3, and the

wrap-around

C3x style

do not occur.

mode, the overflow bits serve as a 2-bit

C5x style

is selected by setting

C3x style

.

Clearing the PDMCD bit results in a PDM rate equal to 1/2 MC (i.e., the CPU
Clock rate). Setting the PDMCD bit results in a PDM rate equal to the MC. After
RESET is held low, the default setting for the PDMCD bit is zero (PDM
rate = 1/2 MC).

Figure 3–1. PDM Clock Divider

Master Clock : 131.07 kHz ... 33.554 MHz

(rate adjusted in ClkSpdCtrl)

Core-Processor Speed

(8 MHz is max assured : see Chapter 9)

MC

÷2

CPU Clock

65.536 kHz ... F

MAX

PDMCD
PDM Clock Divider
Bit 13 in IntGenCtrl

0

1

÷2

x1

(frequency)

Pulse-Density-Modulation Rate

PDM Rate

Governs DAC Capacity

65.536 kHz ... F

131.07 ... 33.554 MHz

MAX

or

3-10

Digital-to-Analog Converter (DAC)

For a given sampling rate and DAC resolution, the CPU clock rate may be
increased, if necessary, through the use of over-sampling. In the previous
example, an original sampling rate of 8 kHz and a PDM rate of 4 MHz was
used. A 2-times over-sampling, therefore, would require the PDM rate to be
8 MHz. This can be accomplished in two ways:

PDM rate = 8 MHz : Set the master clock to 8 MHz also (ClkSpdCtrl).

Set the PDMCD bit to 1: 1x master clock (IntGenCtrl).
CPU clock rate will be 4 MHz.

PDM rate = 8 MHz : Set the master clock to 16 MHz.

Set the PDMCD bit to 0: 1/2 master clock.
CPU clock rate will be 8 MHz.

In the case of over-sampling, the same number of instructions are achievable
between each INT0 interrupt. Not every INT0, however, requires an
independently computed synthesis value, hence, the advantage in increased
instruction capacity. A 2-times over-sampling means that every 2nd INT0
requires a computed update from the synthesis algorithm. The other INT0 may
be satisfied with an interpolating filter computation, then a return to the main
program.

As stated previously , the maximum ensured CPU clock frequency for the C614
operates over the entire V

range. This rate applies to the speed of the core

DD

processor. Operating the processor higher than the listed specification is not
recommended by Texas Instruments.

The following tables illustrate a number of possible combinations with respect
to sampling rate, PDM rate, DAC resolution, master clock rate, and CPU clock
rate. The first table applies to the 8 kHz sampling rate and N-times-8 kHz
over-sampling. The second applies to the 10 kHz sampling rate and
N-times-10 kHz over-sampling.

Note:

The value programmed to the PLLM register is not exactly the multiplicative
factor between the 32-kHz reference and the master clock. Refer to
Section 2.9.3,

Clock Speed Control Register

, for more information on the

relationship between the PLLM and the resulting MC rate.

The column in these tables output sampling rate reports the true audio
sampling rate achievable by the C614, using the 32.768-kHz CRO. The values
reported are not always exact multiples of the 8-kHz and 10-kHz options;
however, they are the closest obtainable (using the PLLM multiplier) under the
given set of constraints.

Peripheral Functions

3-11

Digital-to-Analog Converter (DAC)

8 kHz Nominal Synthesis Rate

32.768 kHz Oscillator Reference

ClkSpdCtrl

PLLM

IntGenCtrl

DAC

Precision

8 bits 1 1x 0x 0F 2.10 2.10 1.05 8.19 128 128

9 bits

10 bits

PDMCD

Bit

0

1 1x 0x 1E 4.06 4.06 2.03 7.94 256 256

0

1 1x 0x 3E 8.26 8.26 4.13 8.06 512 512

0 1x 0x 7C 16.38 8.19 8.19 8.00 1024 1024

Over-

Sampling

Factor

2x 0x 1E 4.06 4.06 2.03 15.87 128 256
4x 0x 3E 8.26 8.26 4.13 32.26 128 512
8x 0x 7C 16.38 16.38 8.19 64.00 128 1024
1x 0x 1E 4.06 2.03 2.03 7.94 256 256
2x 0x 3E 8.26 4.13 4.13 16.13 256 512
4x 0x 7C 16.38 8.19 8.19 32.00 256 1024

2x 0x 3E 8.26 8.26 4.13 16.13 256 512
4x 0x 7C 16.38 16.38 8.19 32.00 256 1024
1x 0x 3E 8.26 4.13 4.13 8.06 512 512
2x 0x 7C 16.38 8.19 8.19 16.00 512 1024

2x 0x 7C 16.38 16.38 8.19 16.00 512 1024

Register

Value

(hex)

Master

Clock

Rate

(MHz)

PDM

Rate

(MHz)

CPU

Clock

Rate

(MHz)

Output

Sampling

Rate
(kHz)

Number of

Instructs
Between

DAC

Interrupts

Number of

Instructs

Between

8 kHz

Interrupts

3-12

Digital-to-Analog Converter (DAC)

10 kHz Nominal Synthesis Rate

32.768 kHz Oscillator Reference

ClkSpdCtrl

PLLM

IntGenCtrl

DAC

Precision

8 bits 1 1x 0x 13 2.62 2.62 1.31 10.24 128 128

9 bits

10 bits

PDMCD

Bit

0

1 1x 0x 26 5.11 5.11 2.56 9.98 256 256

0

“1” 1x 0x 4D 10.22 10.22 5.11 9.98 512 512

“0” 1x 0x 9B 20.45 10.22 10.22 9.98 1024 1024

Over-

Sampling

Factor

2x 0x 26 5.11 5.11 2.56 19.97 128 256
4x 0x 4D 10.22 10.22 5.11 39.94 128 512
8x 0x 9B 20.45 20.45 10.22 79.87 128 1024
1x 0x 26 5.11 2.56 2.56 9.98 256 256
2x 0x 4D 10.22 5.11 5.11 19.97 256 512
4x 0x 9B 20.45 10.22 10.22 39.94 256 1024

2x 0x 4D 10.22 10.22 5.11 19.97 256 512
4x 0x 9B 20.45 20.45 10.22 39.94 256 1024
1x 0x 4D 10.22 5.11 5.11 9.98 512 512
2x 0x 9B 20.45 10.22 10.22 19.97 512 1024

2x 0x 9B 20.45 20.45 10.22 19.97 512 1024

Register

Value

(hex)

Master

Clock

Rate

(MHz)

PDM
RATE
(MHZ)

CPU

Clock

Rate

(MHz)

Output

Sampling

Rate

(kHz)

Number of

Instructs
Between

DAC

Interrupts

Number of

Interrupts

Instructs
Between

10 kHz

Peripheral Functions

3-13

Comparator

3.3 Comparator

The C614 provides a simple comparator that is enabled by a control register
option. The inputs of the comparator are shared with pins PD

and PD5. PD

4

is the noninverting input to the comparator, and PD4 is the inverting input.
When the comparator is enabled, the conditional operation COND2 (normally

associated with PD1) becomes associated with the comparator result. In addi­tion, the interrupts associated with PD4 and PD5 (namely , INT6 and INT7), be­come interrupts based on a

transition

in the comparator result. Finally, the
start/stop function of TIMER1 may be controlled, indirectly, by a comparator
transition. When enabled, therefore, the comparator controls the following four
events:

5

(1) Steady-State Comparator TRUE V

CIN2
CNIN2

has its conditional call taken.
has its conditional call ignored.

(2) Steady-State Comparator FALSE V

CIN2
CNIN2

has its conditional call ignored.
has its conditional call taken.

(3) Comparator transition FALSE-to-TRUE V

PD5

PD5

> V

< V

PD4

PD4

JIN2
JNIN2

JIN2
JNIN2

rises above V

PD5

COND2 = TRUE . . .

has its conditional jump taken.
has its conditional jump ignored.

COND2 = FALSE . . .

has its conditional jump ignored.
has its conditional jump taken.

. . .

PD4

INT6 trigger event
IF: [(INT6 Flag is SET) OR (INT7 Flag is CLEAR)] AND (TIMER1 Enable is CLEAR)

THEN: TIMER1 stops counting

(4) Comparator transition TRUE-to-FALSE V

falls below V

PD5

PD4

. . .
INT7 trigger event
IF: [(INT6 Flag is CLEAR) AND (INT7 Flag is SET)] OR (TIMER1 Enable is SET)]

THEN: TIMER1 starts counting

With regards to the transition events, the rising-edge in the comparator is a
trigger for INT6. This happens independently of any activity associated with
TIMER1. TIMER1, on the other hand, comes to a stop anytime the following
conditional is true:

IF: [(INT6 Flag is SET) OR (INT7 Flag is CLEAR)] AND (TIMER1 Enable is CLEAR)]
THEN: TIMER1 stops counting

INT6 flag refers to bit 6 within the interrupt flag register (IFR, peripheral port
0x39). This bit is automatically SET anytime that an INT6 event occurs. The

3-14

Comparator

bit is automatically CLEARed again if an INT6 event occurs at the same time
that the associated mask bit is SET (IntGenCtrl, address 0x38, bit 6). The latter
indicates that the program vectoring associated with INT6 is enabled. (The flag
bit is SET when the INT event occurs. Only if the mask bit is set, does the
interrupt service occur: vectoring takes place and the flag bit is once again
cleared. Refer to Section 2.7,

Interrupt Logic

, for more details)

The INT6 Flag may also be SET or CLEARed deliberately, at any time, in
software. Use the OUT instruction with the associated I/O port address (IFR,
address 0x39).

INT7 flag refers to bit 7 within the interrupt flag register. This bit is automatically
SET anytime that an INT7 event occurs. The bit is automatically CLEARed
again if an INT7 event occurs at the same time that the associated mask bit
is SET (IntGenCtrl, address 0x38, bit 7). The latter indicates that the service
for INT7 is enabled.

The INT7 Flag may also be SET or CLEARed at any time, in software. Use the
OUT instruction with the associated I/O port address (IFR, address 0x39).

The TIMER1 enable bit is set or cleared in software: bit 10 of the IntGenCtrl.

falling

Similarly, the

-edge event in the comparator is a trigger for INT7. This

happens independently of any activity associated with TIMER1. TIMER1

starts

counting anytime the following conditional is true:

IF: [(INT6 Flag is CLEAR) AND (INT7 Flag is SET)] OR (TIMER1 Enable is SET)]
THEN: TIMER1 starts counting

Figure 3–2. Relationship Between Comparator/Interrupt Activity and the TIMER1 Control

INT-Trigger

Event

Associated With the Interrupt-Trigger Event

0 1 2 3 4 5 INT6 INT7

INT Service

Branch

INT Flag bits (IFR)

Interrupt Flag Register (0x39)

Comparator ENABLE

Bit 15, IntGenCtrl (0x38)

port-addressed

write instruction

TIMER1 ENABLE

Bit 10, IntGenCtrl (0x38)

TIMER1 Control

0 = TIM1 stopped

1 = TIM1 running

Peripheral Functions

3-15

Comparator

The comparator, along with all of its associated functions, is enabled by setting
bit 15 of the interrupt/general control register (IntGenCtrl, address 0x38). The
default value of the register is zero: comparator disabled.

Note: IntGenCtrl Register Bit 15

At the time that bit 15 in the IntGenCtrl is set, PD
comparator inputs. At any time during which bit 15 is set, PD

and PD5 become the

4

and PD5 MUST

4

be set to INPUT (I/O Port D Control, address 0x1C, bits 4 and 5 CLEARed).
Failure to do so may result in a bus contention.

The function of pins PD4 and PD5, and the behavior of events COND2, INT6,
INT7, and TIMER1 are very different, depending on whether the comparator
has been enabled or disabled. A summary of the various states appears in the
following table:

Comparator ENABLED

PD4 functions as comparator negative input
PD

functions as comparator positive input

5

SET bit 15 in the IntGenCtrl, address 0x38 . . .

(port D Control, 0x1C, bit 4 MUST be 0)

(port D Control, 0x1C, bit 5 MUST be 0)
COND2 maps to the state of the comparator (PD5 relative to PD4)
INT6 is triggered by a rising edge at PD

INT7 is triggered by a falling edge at PD
TIMER1 may be started by a falling edge at PD

TIMER1 will be stopped by a rising edge at PD

5

5

5

5

(relative to PD4)

(assuming TIMER1 Enable is 0)

Comparator DISABLED CLEAR bit 15 in the IntGenCtrl, address 0x38 . . .

PD4 functions as a general I/O pin
PD5 functions as a general I/O pin

COND2 maps to the state of the I/O pin PD
INT6 is triggered by a rising edge at PD

INT7 is triggered by a falling edge at PD

4

5

1

(port D Control 0x1C, bit 4 = 0 or 1)

(port D Control 0x1C, bit 5 = 0 or 1)

(0 or 1 logical)

(0 to 1 logical)

(1 to 0 logical)
TIMER1 is started/stopped in software by setting/clearing TIMER1 enable (IntGenCtrl)

3-16

3.4 Interrupt/General Control Register

The interrupt/general control (IntGenCtrl) is a 16-bit wide port-mapped register
located at address 0x38. The primary component in the IntGenCtrl is the 8-bit
interrupt mask register (IMR). The service branch enable status for each of the
eight interrupts is registered in the IMR. A SET bit in the IMR enables that
interrupt to assume the service branch (at the time that the associated trigger
event occurs). A CLEAR bit disables the service branch for that interrupt. The
IMR is located at bits 0 through 7 in the IntGenCtrl. Bit 0 is associated with
INT0, which is the highest priority interrupt. Bit 7 is associated with INT7. Refer
to Section 2.7,
interrupt-system logic and initialization sequence.

IntGenCtrl register
address 0x38 (16-bit wide location)

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

CE AR PD EP E2 E1 S2 S1 D5 D4 PF D3 D2 T2 T1 DA

Interrupt Logic

Interrupt/General Control Register

, for more information regarding the

0x0000 : State after RESET low

CE : Comparator enable
AR : ARM bit
PD : Pulse-density clock: PDMCD
EP : Enable pullup resistors on port F

E2 : Enable TIMER2 (1 value starts timer)
E1 : Enable TIMER 1 (1 value starts timer)
S2 : Clock source for TIMER2 (0 chooses 1/2 MC)
S1 : Clock source for TIMER1 (0 chooses 1/2 MC)

The remaining bits in the IntGenCtrl have various control functions which are
not directly related to the interrupt system. Four of these are related to the timer
functions. Bits 8 and 9 are used to select the clock sources which govern the
rates of TIMER1 and TIMER2. Clearing bit 8 chooses 1/2 MC as the source
for TIMER1 (i.e., the TIMER runs at one-half the frequency of the Master
Clock). Setting bit 8 chooses the oscillator reference (RTO or CRO) as the
source for TIMER1. (The same applies for bit 9 and TIMER2.) Bits 10 and 1 1
in the IntGenCtrl are used to enable TIMER1 and TIMER2, respectively.
Setting bit 10

starts

TIMER1, and clearing bit 10

applies for bit 11 and TIMER2).

low
priority

Interrupt mask register

D5 : port D5 falling-edge
D4 : port D4 rising-edge
D3 : port D
D2 : port D

PF : any port F falling-edge
T2 : TIMER2 underflow
T1 : TIMER1 underflow
DA : DAC timer underflow

(1 value enables interrupt service)

falling-edge

3

rising-edge

2

stops

TIMER1. (The same

high

priority

Peripheral Functions

3-17

Interrupt/General Control Register

The upper four bits in the IntGenCtrl have independent functions. Bit 12 is the
enable bit for the pull-up resistors on input port F. Setting this bit engages all
8 F-port pins with at least 100-kΩ pull-ups (see Section 3.1.2,

Port F

Bit 13 is the PDMCD bit for the pulse-density modulation clock. Clearing this
bit yields a PDM clock rate equal to one-half the frequency of the master clock
(i.e., the CPU clock rate). Setting bit 13 yields a PDM rate equal to the rate of
the master clock (see Section 3.2.3,

Bit 14 is the ARM bit. The set ARM bit causes an asynchronous response to
the internal and external interrupts during the sleep state. If the master clock
has been suspended during sleep, then the ARM bit must be set (before the
IDLE instruction), in order to allow a programmable interrupt to wake the C614.
Refer to Section 2.11,

Finally , the top-most bit in the IntGenCtrl is the comparator enable bit. Setting
bit 15 enables the comparator and all of its associated functions. Some of the
C614’s conditions, interrupts, and timers behave differently, depending on
whether the comparator is enabled or disabled by this bit. Refer to Section 3.3,

Comparator

)

, for a full description.

PDM Clock Divider

Reduced Power Modes

Dedicated Input

)

, for more information.

3-18

3.5 Hardware Initialization States

The RESET pin is configured at all times as an external interrupt. It provides
for a hardware initialization of the C614. When the RESET pin is held low, the
device assumes a deep sleep state and various control registers are
initialized. After the RESET pin is taken high once again, the Program Counter
is loaded with the value stored in the RESET Interrupt Vector.

Note: Internal Power Reset Function

There is no power-on reset function internal to the C614. After the initial pow­er-up or after an interruption in power, the RESET pin must be cycled low-to­high. The application circuitry must therefore provide a mechanism for ac­complishing this during a power-up transition or after a power fluctuation.

Hardware Initialization States

The application circuits shown in Section 6.1,

Application Circuits

, illustrate
one implementation of a reset-on-power-up circuit. The circuit consists of an
RC network (100 kΩ, 1 µF). When powering V

from 0 V to 4.5 V, the circuit

DD

provides some delay on the RESET pin’s low-to-high transition. This delay
helps to ensure that the C614 initialization occurs

after

the power supply has
had time to stabilize between VDD MIN and VDD MAX. VDD MIN and VDD MAX
are the minimum and maximum supply voltages as rated for the device. The

every

circuit shown, however, may not shield the RESET pin from

kind of rapid
fluctuation in the power supply . At any time that the power supply falls below
VDD MIN, even momentarily , then the RESET pin must be held low and then
high once again, either by the user of the device or by some other external cir­cuitry . Refer to Chapter 8,
terization of the values V

MSP50C614 Electrical Specifications

MIN, VDD MAX, VIL, and VOL. (VIL and VOL are the

DD

, for a charac-

low-level and high-level input voltages, respectively , which dictate the precise
levels of transition for RESET.)

When the RESET pin is held low, the C614 is considered reset and has the
following internal states:

RESET low . . .

-

I/O ports are be placed in a high impedance Input condition: Ports A, B,
C, D, and E.

-

All outputs on Port G is are set to low (0x0000).

-

Device is placed in a deep sleep state (refer to reduced power mode IV
in Table 2–7).

-

PLL circuitry, master clock, CPU clock, and TIMERs are stopped.

-

Current draw from the VDD is less than 10 µA in this condition.

-

Interrupt flag register (IFR at address 0x39) is

-

Internal RAM is

not

automatically cleared.

not

automatically cleared.

Peripheral Functions

3-19

Hardware Initialization States

When RESET is brought back high again, many of the programmable controls
and registers are left in their default states:

RESET high, just after low . . .

-

-

-

-

-

-

-

-

-

-

-

Note: Internal RAM State after Reset

The RESET low will not change the state of the internal RAM, assuming there
is no interruption in power. This applies also to the interrupt flag register . The
same applies to the states of the accumulators in the computational unit.

No reference oscillator is enabled. PLL runs at its minimum achievable
rate.
Master clock runs at a very slow frequency (less than 100 kHz).
PLL multiplier is set to 0x00 (renders slowest speed for MC, once
reference is enabled).
RTO oscillator trim bits are set to zero (renders slowest speed for RTO,
once enabled).
Interrupt mask register is 0x00. Global interrupt enable is clear. All
Interrupts are disabled.
I/O Ports A through E and output Port G have the same state as in RESET
low.
All pull-up resistors on input Port F are disabled.
DAC circuitry is disabled (no PDM pulsing).
Both TIMER1 and TIMER2 are disabled. Count-down and period registers
are 0x0000.
The status register is

partially

initialized, as specified in Table 3–1.

Idle state clock control and ARM bit are both set to zero.

3-20

When in this state, the processor runs, albeit slowly . It executes the following
initialization routine, then resumes execution of the program:

1) ROM block protection word is read from address 0x7FFE.

2) ROM block protection word is loaded to an internal register.

3) RESET interrupt vector is read from address 0x7FFF.

4) Program counter is loaded with the value read from (3); execution re­sumes there.

Hardware Initialization States

Note: Stack Pointer Initialization

The software stack pointer (R7) must be initialized by the programmer, so
that it points to some legitimate address in data memory (RAM). This must
be done prior to any CALL or CCC instruction. If this is not done, then the first
push/pop operation performed on the STACK will render the Program Count­er to an unknown state.

Table 3–2. State of the Status Register (17 bit) after RESET Low-to-High

(Bits 5 through 16 are left uninitialized)

Bit Bit Name Initialized Value Description

0 XM 0 Extended sign mode disabled
1 UM 0 Unsigned multiplier mode disabled (allows signed multiplier mode)
2 OM 0 Overflow mode disabled (allows ALU normal mode)

3 FM 0

4 IM 0 Global interrupt enable bit
5 (reserved) Reserved for future use
6 XZF Transfer equal-to-zero status bit
7 XSF Transfer sign status bit
8 RCF Auxiliary register carry-out status bit
9 RZF Auxiliary register equal-to-zero status bit

10 OF

11 SF
12 ZF Accumulator equal-to-zero status bit (16 bits)
13 CF Accumulator carry-out status bit (16th ALU bit)
14 TF1 Test flag 1
15 TF2 Test flag 2
16 TAG Memory tag

Same state as
before RESET

Shift mode for fractional multiplication disabled (allows unsigned
fractional/integer arithmetic)

Accumulator overflow status bit
Accumulator sign status bit (extended 17th bit)

Peripheral Functions

3-21

3-22

Chapter 4

Assembly Language Instructions

This chapter describes in detail about MSP50P614/MSP50C614 assembly
language. Instruction classes, addressing modes, instruction encoding and
explanation of each instruction is described.

Topic Page

4.1 Introduction 4–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2 System Registers 4–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3 Instruction Syntax and Addressing Modes 4–8. . . . . . . . . . . . . . . . . . . . . .

4.4 Instruction Classification 4–22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.5 Bit, Byte, Word and String Addressing 4–44. . . . . . . . . . . . . . . . . . . . . . . .

4.6 MSP50P614/MSP50C614 Computational Modes 4–49. . . . . . . . . . . . . . . .

4.7 Hardware Loop Instructions 4–53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.8 String Instructions 4–55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.9 Lookup Instructions 4–57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.10 Input/Output Instructions 4–59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.11 Special Filter Instructions 4–59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.12 Conditionals 4–69. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.13 Legend 4–70. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.14 Individual Instruction Descriptions 4–74. . . . . . . . . . . . . . . . . . . . . . . . . . .

4.15 Instruction Set Encoding 4–187. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.16 Instruction Set Summary 4–196. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-1

Introduction

4.1 Introduction

In this chapter each MSP50P614/MSP50C614 class of instructions is
explained in detail with examples and restrictions. Most instructions can
individually address bits, bytes, words or strings of words or bytes. Usable
program memory is 30K by 17-bit wide and the entire 17-bits are used for
instruction set encoding. The execution of programs can only be executed
from internal program memory . Usable program memory starts from location
800h. The data memory is 640 by 17-bits of static RAM, 16 bits of which are
an arithmetic value. The 17th bit is used for flags or tags.

4.2 System Registers

A functional description of each system register is described below.

4.2.1 Multiplier Register (MR)

The multiplier uses this 16-bit register to multiply with the multiplicand. MOV
instructions are used to load the MR register. The multiplicand is usually the
operand of the multiply instructions. All multiply, multiply-accumulate
instructions, and filter instructions (FIR, FIRK, COR and CORK) use the MR
register (see Section 4.11 for detail).

4.2.2 Shift Value Register (SV)

The shift value register is 4-bits wide. For barrel shift instructions, the multiplier
operand decodes a 4 bit value in the shift value register (SV) to a 16 bit value.
For example, a value of 7H in the SV register is decoded to a multiplier operand
of 0000000010000000 binary . In effect, this causes a left shift of 7 bits to in the
final 32 bit product. In other words, a nonzero value, say
SV register means padding k number of zeros to the right of the final result.

4.2.3 Data Pointer Register (DP)

The data pointer register (DP) is a 16-bit register that is used to point to a
program memory location for various look up table instructions. DP is not
directly loaded by the user, It is loaded during the execution of lookup
instructions overwriting the previous content of the DP register. Lookup
instructions are described in detail in section 4.9. The DP register auto­increments the next logical program memory location after the execution of a
lookup instruction. In addition to lookup instructions, the filter instructions FIRK
and CORK (see Section 4.11 for detail) use the DP pointer to look up filter
coefficients. It may be required to context save and restore the DP in interrupt
service routines.

4.2.4 Program Counter (PC)

The program counter (PC) holds the program memory location to be used for
the next instruction’s execution. It increments (by 1 for single word instructions

k

(0 ≤ k ≤ 15), in the

4-2

or by 2 for double word instructions) each execution cycle and points to the
next program memory location to fetch. During a maskable interrupt, the next
PC address is stored in the TOS register and is reloaded from TOS after the
interrupt encounters an IRET instruction. Call and jump instructions also store
the next instruction address by adding PC+2 and then storing the result in the
TOS register . Upon encountering a RET instruction, the TOS value is reloaded
to the PC. Call instructions may not precede RET instructions. Similarly , a RET
instruction may not immediately follow another RET instruction. In these
conditions, pipeline operations breaks down and the PC never recovers its re­turn address from the TOS register . The processor stalls, and the only solution
is to reset the device. On the other hand, RET can be safely replaced by IRET
eliminating processor stalls in all conditions. However, IRET takes one more
cycle than RET.

4.2.5 Top of Stack, (TOS)

The top of stack (TOS) register holds the value of the stack pointed by the stack
register (R7). The MSP50P614/MSP50C614 hardware uses TOS register for
very efficient returns from CALL instructions. Figure 4-1 shows the operation
of the TOS register . When call instructions are executed, the old TOS register
value is pushed into the stack by pre-incrementing R7. The current PC value
is incremented by 2 to compute the final return address and is then stored in
the TOS register . Thus, the TOS register holds the next PC value pointing to
the next instruction. When the subroutine reaches the RET instruction, the
program counter (PC) is loaded with the TOS register . Next, the TOS is loaded
with the value pointed to by R7. Finally , the stack register (R7) is decremented.

System Registers

Figure 4–1. Top of Stack (TOS) Register Operation

Program counter (PC)

+2

Top of stack register (TOS)

Read before
incrementing R7

Data memory stack area

The MSP50P614/MSP50C614 development tools use the TOS register for
parameter passing. The TOS register must be used with caution inside user
programs. If the TOS register and stack register (R7) are not restored to their
previous values after using the TOS register in an application, the program can
hang the processor or cause the program to behave in an unpredictable way .

Increment R7 then
store TOS value

Stack register (R7)

Preincrement
during write (+2)

Postdecrement
during read (+2)

Assembly Language Instructions

4-3

System Registers

It is recommended to avoid using the TOS register altogether in applications
and leave its operation to development tools only.

4.2.6 Product High Register (PH)

This register holds the upper 16 bits of the 32 bit result of a multiplication,
multiply-accumulate, or shift operation. The lower 16 bits of the result are
stored in the PL register. The PH register can be loaded directly by MOV
instructions. Special move accumulate instructions MOVAPH, MOVAPHS,
MOVSPH, MOVSPHS also use the PH register .

4.2.7 Product Low Register (PL)

This register holds the lower 16 bits of the 32 bit result of a multiplication,
multiply-accumulate, or shift operation. The upper 16 bits of the result are
stored in the PH register. There are no instructions that load or save the PL
register directly , but multiply-accumulate instructions allow the contents of the
PL register to be added, subtracted or transferred to the accumulator.

4.2.8 Accumulators (AC0–AC31)

There are 32 accumulators on the MSP50P614/MSP50C614. Each is 16 bits
wide. The first sixteen accumulators, AC0–AC15, have offset accumulators,
AC16–AC31, and vice versa. At any one time, four accumulators can be
selected through accumulator pointer registers, AP0–AP3 (see section 4.2.9).
Some instructions can specify offset accumulators which are the
accumulators pointed to by AP
to 31). The offset accumulators are indicated by an offset bit (A~) in some
instructions. When this bit is 0, A
then A

n~

points to the offset (for some instructions this scheme changes). The
selected accumulator pointer register should contain the index to the
corresponding accumulator. For example, if AP0 has a value of 25, then it is
pointing to accumulator AC25. If the offset bit is 1, A0~, then it is pointing to
accumulator AC9 (25–16=9). Because, accumulators can only be addressed
through accumulator pointers, special symbols are used in MSP50P614/
MSP50C614 instructions. Accumulators are indicated by the symbol A
where n ranges from 0 to 3. The symbol indicates that the accumulator pointed

n

to by AP
accumulator ACk. Similarly, An~ points to the offset accumulator pointed by
APn. For example, if AP3 = 22, then A3 is accumulator AC22 and A3~ is
accumulator AC6.

is the referring accumulator. If APn has a value of k, it is pointing to

n

+16 or APn –16 (whichever is in the range 0

n

points to the accumulator directly . If it is 1,

n

,

4-4

During accumulator read operations, both An and offset An~ are fetched.
Depending on the instruction, either or both registers may be used. In addition,
some write operations allow either register to be selected.

The accumulator block can also be used in string operations. The selected

n

accumulator (A

or An~) is the least significant word (LSW) of the string and
is restored at the end of the operation. String instructions are described in
detail in section 4.8.

4.2.9 Accumulator Pointers (AP0–AP3)

The accumulator pointer (AP) registers are 5 bit registers which point to one
of the 32 available accumulators. The APs contain the index of accumulators.
Many instructions allow preincrement or predecrement accumulator pointers.
Such instructions have a suffix of ++A for preincrement or ––A for
predecrement. Accumulator pointers can be stored or loaded from memory
using various addressing modes. Limited arithmetic operations can be
performed on accumulator pointers.

Bit Bits 16 – 5 4 3 2 1 0

System Registers

AP0–AP3 Not used Points to A

4.2.10 Indirect Register (R0–R7)

Indirect registers, R0–R7, are 16-bit registers that are used in various
addressing modes or as general-purpose registers. R0, R1, R2 and R3 can
be usedsolely as general-purpose registers. These registers can also be used
as indirect registers with relative addressing.

The R4 or LOOP register is used with instructions BEGLOOP and ENDLOOP
to define a hardware controlled loop. If R4 is loaded with a value,

32767), the BEGLOOP and ENDLOOP block will be executed
loop stops when R4 becomes negative.

The R5 or INDEX register is used with indirect addressing and relative addres­sing modes of certain instructions.

The R6 or P AGE register is used with page relative addressing and relative flag
addressing.

The R7 or ST ACK register holds the pointer to the stack. It can be used as a
general-purpose register as long as no CALL/RET instructions are used
before restoring it with its old value. However, this register can only be used
as a general-purpose register when maskable interrupts are disabled. The old

n

n = val (b0–b4)

n

(0 ≤ n ≤

n+2

times. The

Assembly Language Instructions

4-5

System Registers

value of the STACK register should be stored before use and restored after
use. This register must point to the beginning of the stack in the RESET
initialization routine before any CALL instruction or maskable interrupts can be
used. CALL instructions increment R7 by 2., RET instructions decrement R7
by 2. The stack in MSP50P614/MSP50C614 is positively incremented.

4.2.11 String Register (STR)

The string register (STR) holds the length of the string used by all string instruc­tions. MOV instructions are used to load this register to define the length of a
string. The value in this register is not altered after the execution of a string
instruction. A value of zero in this register defines a string length of 2. Thus,
a numerical value, n
maximum string length is 32. Therefore, 0 ≤ nS ≤ 30 corresponds to actual
string lengths from 2 to 32.

4.2.12 Status Register (STAT)

The status register (STAT) provides the storage of various single bit mode
conditions and condition bits. As shown in Table 4–1, mode bits reside in the
first 5 LSBs of the status register and can be independently set or reset with
specific instructions. See section 4.6 for detail about these computational
modes. Condition bits and flags are used for conditional branches, calls, and
flag instructions. Flags and status condition bits are stored in the upper 10 bits
of the 17 bit status register. MOV instructions provide the means for context
saves and restores of the status register. The STAT should be initialized to
0000h after the processor resets.

, in the STR register, defines a string length of ns+2. The

s

4-6

The XSF and XZF flags are related to data flow to or from the internal data bus.
If the destination of the transfer is an accumulator, then the SF, ZF , CF and OF

x

flags are affected. If the destination of the transfer is R

, the RCF and RZF
flags are affected. If the destination of the transfer is through the internal
databus, the XSF and XZF flags are affected. The SF flag is the sign flag and
it is equal to the most significant bit of an accumulator when an accumulator
instruction is executed. ZF is the zero flag and is set when the instruction
causes the accumulator value to become zero. CF is the carry flag and is set
when the instruction causes a carry. A carry is generated by addition,
subtraction, multiplication, multiply-accumulate, compare, shifting and some
MOV instructions (that have accumulation features). CF is reset if no carry
occurs after execution of an instruction. OF is set when a computation causes
overflow in the result. It is reset if no overflow occurs during an accumulator
based instruction. Overflow saturation mode is set by the OM bit as explained
in section 4.6.

System Registers

Table 4–1. Status Register (STAT)

Bit Name Function

0 XM Sign extended mode bit. This bit is one, if sign extension mode is enabled. See

MSP50P614/MSP50C614 Computational Modes, Section 4.6.

1 UM Unsigned multiplier mode. This bit is one if unsigned multiplier mode is enabled. See

MSP50P614/MSP50C614 Computational Modes, Section 4.6.

2 OM Overflow mode. This bit is one if overflow (saturation) mode is enabled. See

MSP50P614/MSP50C614 Computational Modes, Section 4.6.

3 FM Fractional multiplication shift mode. This bit is set if fractional mode is enabled. See

MSP50P614/MSP50C614 Computational Modes, Section 4.6.
4 IM Maskable interrupt enable mode. If this bit is zero, all maskable interrupts are disabled.
5 Reserved Reserved for future use.
6 XZF Transfer(x) equal to zero status (flag) bit. In transfer instructions, this bit is set if the operation

cause the destination result to become zero (excluding accumulator and Rx registers).
7 XSF Transfer(x) sign status (flag) bit. In transfer instructions, the sign bit of the value is copied to

this bit if the destination is not accumulator or R

x

registers.

8 RCF Indirect register carry out status (flag) bit. This bit is set if an addition to the value of Rx register

caused a carry.
9 RZF Indirect register equal to zero status (flag) bit. This bit is set if the Rx register content used by

the instruction is zero.

10 OF Accumulator overflow status (flag) bit. This bit is set if an overflow occurs during computation

in ALU.

11 SF Accumulator sign status (flag) bit (extended 17th bit). This bit is set if the 16th bit (the sign bit)

of the destination accumulator is 1.

12 ZF Accumulator equal to zero status (flag) bit (16 bits). This bit is set to 1 if the result of previous

instruction cause the destination accumulator to become zero.

13 CF Accumulator carry out status (flag) bit ( 16th ALU bit).
14 TF1 Test Flag 1. T est flags are related with Class 8 instructions discussed later.
15 TF2 Test Flag 2. T est flags are related with Class 8 instructions discussed later.
16 TAG Memory tag. Holds the 17th bit whenever a memory value is read.

Assembly Language Instructions

4-7

Instruction Syntax and Addressing Modes

4.3 Instruction Syntax and Addressing Modes

MSP50P614/MSP50C614 instructions can perform multiple operations per
instruction. Many instructions may have multiple source arguments. They can
premodify register values and can have only one destination. The addressing
mode is part of the source and destination arguments. In the following subsec­tion, a detail of the MSP50P614/MSP50C614 instruction syntax is explained
followed by the subsection which describes addressing modes.

4.3.1 MSP50P614/MSP50C614 Instruction Syntax

All MSP50P614/MSP50C614 instructions with multiple arguments have the
following syntax:

name [

dest

] [,

src

] [,

src1

] [,

mod

]

where the symbols are described as follows:

name

dest dest

src sourc

src1 sourc

mod

name

of the instruction. Instruction names are shown in bold letters. If the

instruction

name

types. If

tional or not used for some instructions. Destination is also used as both a
source and a destination for some instructions. If a destination is specified,
it must always be the first argument. Destinations can be system registers
or data memory locations referred by addressing modes. This is instruc­tion specific.

be a system register, a data memory location referred by addressing
modes, or a program memory location. This is instruction specific.

tional or not used for some instructions. Source 1 can be a system register,
a data memory location referred by addressing modes, or a program
memory location. This is instruction specific.

pre or post modification of a register. The meaning of
specific.

name

is followed by a B, the arguments are all byte types. If

is followed by an S, all arguments are word string (strings of words)

name

is followed by BS, all arguments are byte string types.

ination of data to be stored after the execution of an instruction. Op-

e of first data. Optional or not used for some instruction. Source can

e of second data. Some instructions use a second data source. Op-

mod

is instruction

4-8

[ ] Square brackets represent optional arguments. Some instructions have

many combinations of source and destination registers and addressing
modes. The combination is instruction class specific.

The possible combinations of sources, destinations and modifications are de­pendent on the instruction class. Instruction classes are discussed in detail in
section 4.4.