Texas Instruments MSP430x11x1 User Manual

Low Supply Voltage Range 1.8 V – 3.6 V

Ultralow-Power Consumption Low Operation Current,

1.3 µA at 4 kHz, 2.2 V 160 µA at 1 MHz, 2.2 V

Five Power Saving Modes: (Standby Mode: 0.8 µA, RAM Retention Off Mode: 0.1 µA)

Wake-Up From Standby Mode in 6 µs

16-Bit RISC Architecture, 125 ns Instruction Cycle Time

Basic Clock Module Configurations: – Various Internal Resistors – Single External Resistor – 32 kHz Crystal – High Frequency Crystal – Resonator – External Clock Source

16-Bit Timer With Three Capture/Compare Registers

Slope A/D Converter With External Components

On-Chip Comparator for Analog Signal Compare Function or Slope A/D Conversion

description

Serial Onboard Programming

Programmable Code Protection by Security Fuse (C11x1 Only)

Family Members Include: MSP430C1 111: 2KB ROM,128B RAM MSP430C1 121: 4KB ROM, 256B RAM MSP430F1101: 1KB + 128B Flash Memory

MSP430F1121: 4KB + 256B Flash Memory

Available in a 20-Pin Plastic Small-Outline Wide Body (SOWB) Package and 20-Pin Plastic Thin Shrink Small-Outline Package (TSSOP)

TEST

VCC

P2.5/R

osc

XOUT

XIN

/NMI

RST

P2.0/ACLK

P2.1/INCLK

P2.2/CAOUT/TA0

MSP430x11x1

MIXED SIGNAL MICROCONTROLLER

SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000

(MTP{), 128B RAM

(MTP{), 256B RAM

DW OR PW PACKAGE

(TOP VIEW)

1 2 3 4 5 6 7 8 9 10

20 19 18 17 16 15 14 13 12 11

P1.7/TA2/TDO/TDI P1.6/TA1/TDI P1.5/TA0/TMS P1.4/SMCLK/TCK P1.3/TA2 P1.2/TA1 P1.1/TA0 P1.0/TACLK P2.4/CA1/TA2 P2.3/CA0/TA1

The T exas Instruments MSP430 series is an ultralow-power microcontroller family consisting of several devices featuring different sets of modules targeted to various applications. The microcontroller is designed to be battery operated for an extended-application lifetime. With 16-bit RISC architecture, 16 bit integrated registers on the CPU, and a constant generator, the MSP430 achieves maximum code efficiency. The digitally-controlled oscillator provides fast wake-up from all low-power modes to active mode in less than 6 ms.

Typical applications include sensor systems that capture analog signals, convert them to digital values, and then process the data and display them or transmit them to a host system. Stand alone RF sensor front end is another area of application. The I/O port inputs provide single slope A/D conversion capability on resistive sensors. The MSP430x11x series is an ultralow-power mixed signal microcontroller with a built in 16-bit timer and fourteen I/O pins. The MSP430x11x1 family adds a versatile analog comparator.

The flash memory provides added flexibility of in-system programming and data storage without significantly increasing the current consumption of the device. The programming voltage is generated on-chip, thereby alleviating the need for an additional supply , and even allowing for reprogramming of battery-operated systems.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

{

MTP = Multiple Time Programmable

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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MSP430x11x1

40°C to 85°C

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–

functional block diagram

AVAILABLE OPTIONS

PACKAGED DEVICES

PLASTIC

20-PIN SOWB

(DW)

MSP430C1111IDW MSP430C1121IDW MSP430F1101IDW MSP430F1121IDW

PLASTIC

20-PIN TSSOP

(PW)

MSP430F1101IPW MSP430F1121IPW

TEST

Rosc

†

XIN XOUT

Oscillator

System Clock

MCLK

CPU

Incl. 16 Reg.

Test

JTAG

ACLK SMCLK

MAB, 16 Bit

MDB, 16 Bit

ACLK

SMCLK

1/2/4 KB ROM/

Flash+126/256B

Flash INFO

’C’: ROM ’F’: Flash

Watchdog

Timer

15/16 Bit

128/256B

RAM

Timer_A

3 CC

CCR0/1/2 x = 0, 1, 2

RST/NMI P1.0–7

Power-on-

Reset

Bus

Conv.

TACLK or

INCLK CCI1

Outx CCIx CCIx

Comparator-A

Input Multiplexer

RC Filtered O/P

Internal Vref

Analog Switch

Outx

CCIxA

TACLK

SMCLK

MAB, 4 Bit

MCB

MDB, 8 Bit

INCLK

Out0 CCI0

8 I/O’s, All With

CCI1

I/O Port P1

Interrupt

Capabililty

I/O Port P2

6 I/O’s All With

Interrupt

Capabililty

JTAG

ACLK DCOR

†

A pulldown resistor of 30 kΩ is needed on F11x1.

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P2.0 / ACLK

P2.1 / INCLK

P2.2 / CAOUT/TA0

P2.5 / Rosc P2.4 / CA1/TA2 P2.3 / CA0/TA1

MSP430x11x1

TERMINAL

I/O

DESCRIPTION

MIXED SIGNAL MICROCONTROLLER

SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000

Terminal Functions

NAME NO.

P1.0/TACLK 13 I/O General-purpose digital I/O pin/Timer_A, clock signal TACLK input P1.1/TA0 14 I/O General-purpose digital I/O pin/Timer_A, capture: CCI0A input, compare: Out0 output P1.2/TA1 15 I/O General-purpose digital I/O pin/Timer_A, capture: CCI1A input, compare: Out1 output P1.3/TA2 16 I/O General-purpose digital I/O pin/Timer_A, capture: CCI2A input, compare: Out2 output P1.4/SMCLK/TCK 17 I/O General-purpose digital I/O pin/SMCLK signal output/test clock, input terminal for device programming

P1.5/TA0/TMS 18 I/O General-purpose digital I/O pin/Timer_A, compare: Out0 output/test mode select, input terminal for

P1.6/TA1/TDI 19 I/O General-purpose digital I/O pin/Timer_A, compare: Out1 output/test data input terminal P1.7/TA2/TDO/TDI

P2.0/ACLK 8 I/O General-purpose digital I/O pin/ACLK output P2.1/INCLK 9 I/O General-purpose digital I/O pin/Timer_A, clock signal at INCLK P2.2/CAOUT/T A0 10 I/O General-purpose digital I/O pin/Timer_A, capture: CCI0B input/comparator_A, output P2.3/CA0/T A1 11 I/O General-purpose digital I/O pin/Timer_A, compare: Out1 output/comparator_A, input P2.4/CA1/T A2 12 I/O General-purpose digital I/O pin/Timer_A, compare: Out2 output/comparator_A, input P2.5/R

osc

RST/NMI 7 I Reset or nonmaskable interrupt input TEST 1 I Select of test mode for JTAG pins on Port1. Must be tied low with less than 30 kΩ (F11x1). VCC 2 Supply voltage V

XIN 6 I Input terminal of crystal oscillator XOUT 5 I/O Output terminal of crystal oscillator

†

TDO or TDI is selected via JTAG instruction.

†

20 I/O General-purpose digital I/O pin/Timer_A, compare: Out2 output/test data output terminal or data input

3 I/O General-purpose digital I/O pin/Input for external resistor that defines the DCO nominal frequency

4 Ground reference

and test

device programming and test

during programming

short-form description

processing unit

The processing unit is based on a consistent, and orthogonally-designed CPU and instruction set. This design structure results in a RISC-like architecture, highly transparent to the application development, and noted for its programming simplicity . All operations other than program-flow instructions are consequently performed as register operations in conjunction with seven addressing modes for source, and four modes for destination operands.

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short-form description (continued)

CPU

Program Counter

PC/R0

All sixteen registers are located inside the CPU,

Stack Pointer

SP/R1

providing reduced instruction execution time. This reduces a register-register operation execution

Status Register

SR/CG1/R2

time to one cycle of the processor.

Constant Generator

CG2/R3

Four registers are reserved for special use as a program counter, a stack pointer , a status register,

General-Purpose Register

and a constant generator. The remaining twelve registers are available as general-purpose

General-Purpose Register

registers. Peripherals are connected to the CPU using a

data address and control buses and can be

General-Purpose Register R14

handled easily with all instructions for memory manipulation.

General-Purpose Register

R15

instruction set

The instructions set for this register-register architecture provides a powerful and easy-to-use assembly language. The instruction set consists of 51 instructions with three formats and seven addressing modes. T able 1 provides a summation and example of the three types of instruction formats; the addressing modes are listed in Table 2.

Table 1. Instruction Word Formats

Dual operands, source-destination e.g. ADD R4, R5 R4 + R5 → R5 Single operands, destination only e.g. CALL R8 PC → (TOS), R8 → PC

Relative jump, un-/conditional e.g. JNE Jump-on equal bit = 0

Most instructions can operate on both word and byte data. Byte operations are identified by the suffix B. Examples: Instructions for word operation Instructions for byte operation

MOV EDE,TONI MOV.B EDE,TONI ADD #235h,&MEM ADD.B #35h,&MEM PUSH R5 PUSH.B R5 SWPB R5 —

Table 2. Address Mode Descriptions

ADDRESS MODE s d SYNTAX EXAMPLE OPERATION

Register √ √ MOV Rs, Rd MOV R10, R11 R10 → R11 Indexed √ √ MOV X(Rn), Y(Rm) MOV 2(R5), 6(R6) M(2 + R5) → M(6 + R6) Symbolic (PC relative) √ √ MOV EDE, TONI M(EDE) → M(TONI) Absolute √ √ MOV &MEM, &TCDAT M(MEM) → M(TCDAT) Indirect √ MOV @Rn, Y(Rm) MOV @R10, Tab(R6) M(R10) → M(Tab + R6) Indirect autoincrement √ MOV @Rn+, RM MOV @R10+, R11 M(R10) → R11, R10 + 2 → R10 Immediate √ MOV #X, TONI MOV #45, TONI #45 → M(TONI)

NOTE: s = source d = destination Rs/Rd = source register/destination register Rn = register number

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instruction set (continued)

Computed branches (BR) and subroutine calls (CALL) instructions use the same addressing modes as the other instructions. These addressing modes provide calls. The full use of this programming capability permits a program structure different from conventional 8- and 16-bit controllers. For example, numerous routines can easily be designed to deal with pointers and stacks instead of using flag type programs for flow control.

indirect

operation modes and interrupts

The MSP430 operating modes support various advanced requirements for ultralow-power and ultralow energy consumption. This is achieved by the intelligent management of the operations during the different module operation modes and CPU states. The advanced requirements are fully supported during interrupt event handling. An interrupt event awakens the system from each of the various operating modes and returns with the

RETI

instruction to the mode that was selected before the interrupt event. The different requirements of the CPU and modules, which are driven by system cost and current consumption objectives, necessitate the use of different clock signals:

Auxiliary clock ACLK (from LFXT1CLK/crystal’s frequency), used by the peripheral modules

Main system clock MCLK, used by the CPU and system

Subsystem clock SMCLK, used by the peripheral modules

addressing, ideally suited for computed branches and

low-power consumption capabilities

The various operating modes are controlled by the software through controlling the operation of the internal clock system. This clock system provides many combinations of hardware and software capabilities to run the application with the lowest power consumption and with optimized system costs:

Use the internal clock (DCO) generator without any external components.

Select an external crystal or ceramic resonator for lowest frequency or cost.

Select and activate the proper clock signals (LFXT1CLK and/or DCOCLK) and clock pre-divider function.

Apply an external clock source.

Four of the control bits that influence the operation of the clock system and support fast turnon from low power operating modes are located in the status register SR. The four bits that control the CPU and the system clock generator are SCG1, SCG0, OscOff, and CPUOff:

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status register R2

15 9 8 7 0

Reserved For Future

Enhancements

rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0

V SCG1 SCG0 OscOff

6543 21

CPUOff GIE N Z C

The bits CPUOff, SCG1, SCG0, and OscOff are the most important low-power control bits when the basic function of the system clock generator is established. They are pushed onto the stack whenever an interrupt is accepted and thereby saved so that the previous mode of operation can be retrieved after the interrupt request. During execution of an interrupt handler routine, the bits can be manipulated via indirect access of the data on the stack. That allows the program to resume execution in another power operating mode after the return from interrupt (RETI).

SCG1: The clock signal SMCLK, used for peripherals, is enabled when bit SCG1 is reset or disabled if

the bit is set.

SCG0: The dc-generator is active when SCG0 is reset. The dc-generator can be deactivated only if the

SCG0 bit is set and the DCOCLK signal is not used for MCLK or SMCLK. The current consumed

by the dc-generator defines the basic frequency of the DCOCLK. It is a dc current.

The clock signal DCOCLK is deactivated if it is not used for MCLK or SMCLK or if the SCG0 bit

is set. There are two situations when the SCG0 bit cannot switch off the DCOCLK signal:

1. DCOCLK frequency is used for MCLK (CPUOff=0 and SELM.1=0).

2. DCOCLK frequency is used for SMCLK (SCG1=0 and SELS=0).

NOTE:

When the current is switched off (SCG0=1) the start of the DCOCLK is delayed slightly . The delay is in the µs-range (see device parameters for details).

OscOff: The LFXT1 crystal oscillator is active when the OscOff bit is reset. The LFXT1 oscillator can only

be deactivated if the OscOff bit is set and it is not used for MCLK or SMCLK. The setup time to

start a crystal oscillation needs consideration when oscillator off option is used. Mask

programmable (ROM) devices can disable this feature so that the oscillator can never be switched

off by software.

CPUOff: The clock signal MCLK, used for the CPU, is active when the CPUOf f bit is reset or stopped if it

is set.

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interrupt vector addresses

The interrupt vectors and the power-up starting address are located in the memory with an address range of 0FFFFh-0FFE0h. The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.

INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY

Power-up, external reset, watchdog

NMI, oscillator fault, flash memory access violation

Comparator_A CAIFG maskable 0FFF6h 11 Watchdog timer WDTIFG maskable 0FFF4h 10 Timer_A CCIFG0 (Note 2) maskable 0FFF2h 9

Timer_A

I/O Port P2 (eight flags – see Note 3)

I/O Port P1 (eight flags)

NOTES: 1. Multiple source flags

2. Interrupt flags are located in the module

3. There are eight Port P2 interrupt flags, but only six Port P2 I/O pins (P2.0–5) are implemented on the 11x1 devices.

4. (non)-maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable cannot. Nonmaskable: neither the individual nor the general interrupt enable bit will disable an interrupt event.

WDTIFG (Note1) KEYV (Note 1)

NMIIFG (Notes 1 and 4) OFIFG (Notes 1 and 4) ACCVIFG (Notes 1 and 4)

CCIFG1, CCIFG2, TAIFG (Notes 1 and 2)

P2IFG.0 to P2IFG.7 (Notes 1 and 2)

P1IFG.0 to P1IFG.7 (Notes 1 and 2)

Reset 0FFFEh 15, highest

(non)-maskable, (non)-maskable,

(non)-maskable

maskable 0FFF0h 8

maskable 0FFE6h 3

maskable 0FFE4h 2

0FFFCh 14

0FFFAh 13

0FFF8h 12

0FFEEh 7 0FFECh 6 0FFEAh 5 0FFE8h 4

0FFE2h 1 0FFE0h 0, lowest

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special function registers

Most interrupt and module enable bits are collected into the lowest address space. Special function register bits that are not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement.

interrupt enable 1 and 2

Address 0h

7654 0

rw-0 rw-0 rw-0

WDTIE: Watchdog timer enable signal OFIE: Oscillator fault enable signal NMIIE: Nonmaskable interrupt enable signal ACCVIE: Access violation at flash memory

Address 01h

7654 0321

interrupt flag register 1 and 2

Address 02h NMIIFG

7654 0

WDTIFG: Set on overflow or security key violation or

Reset on V

power-on or reset condition at RST/NMI-pin

OFIFG: Flag set on oscillator fault NMIIFG: Set via RST/NMI-pin

Address 03h

7654 0321

321

NMIIEACCVIE

321

rw-0 rw-1 rw-0

OFIE WDTIE

rw-0

OFIFG WDTIFG

Legend rw:

rw-0:

Bit can be read and written. Bit can be read and written. It is reset by PUC SFR bit is not present in device.

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memory organization

MSP430x11x1

MIXED SIGNAL MICROCONTROLLER

SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000

FFFFh FFE0h

FFDFh

F800h

027Fh 0200h 01FFh 0100h

00FFh 0010h 000Fh 0000h

MSP430C111 1

Int. Vector

2 KB ROM

128B RAM

16b Per.

8b Per.

SFR

FFFFh FFE0h FFDFh

F000h

02FFh

0200h

01FFh

0100h

00FFh

0010h

000Fh

0000h

MSP430C1121

Int. Vector

4 KB ROM

256B RAM

16b Per.

8b Per.

SFR

FFFFh FFE0h

FFDFh

FC00h

10FFh

1080h

0FFFh 0C00h

027Fh

0200h

01FFh

0100h

00FFh

0010h

000Fh

0000h

MSP430F1101

Int. Vector

1 KB Flash

Segment0,1

128B Flash

SegmentA

1 KB

Boot ROM

128B RAM

16b Per.

8b Per.

SFR

FFFFh FFE0h

FFDFh

F000h

10FFh

1000h

0FFFh 0C00h

02FFh

0200h

01FFh

0100h

00FFh

0010h

000Fh

0000h

MSP430F1121

Int. Vector

4 KB

Flash

Segment0–7

2 × 128B

Flash

SegmentA,B

1 KB

Boot ROM

256B RAM

16b Per.

8b Per.

SFR

Main Memory

Information Memory

boot ROM containing bootstrap loader

The intention of the bootstrap loader is to download data into the flash memory module. V arious write, read, and erase operations are needed for a proper download environment. The bootstrap loader is only available on F devices.

functions of the bootstrap loader:

Definition of read: apply and transmit data of peripheral registers or memory to pin P1.1 (BSLTX) write: read data from pin P2.2 (BSLRX) and write them into flash memory

unprotected functions

Mass erase, erase of the main memory (Segment0 to Segment7) Access to the MSP430 via the bootstrap loader is protected. It must be enabled before any protected function can be performed. The 256 bits in 0FFE0h to 0FFFFh provide the access key.

protected functions

All protected functions can be executed only if the access is enabled.

Write/program byte into flash memory; Parameters passed are start address and number of bytes (the segment-write feature of the flash memory is not supported and not useful with the UART protocol).

Segment erase of Segment0 to Segment7 in the main memory and segment erase of SegmentA and SegmentB in the information memory.

Read all data in main memory and information memory.

Read and write to all byte peripheral modules and RAM.

Modify PC and start program execution immediately.

NOTE:

Unauthorized readout of code and data is prevented by the user’s definition of the data in the interrupt memory locations.

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boot ROM containing bootstrap loader (continued)

features of the bootstrap loader are:

UART communication protocol, fixed to 9600 baud

Port pin P1.1 for transmit, P2.2 for receive

TI standard serial protocol definition

Implemented in flash memory version only

Program execution starts with the user vector at 0FFFEh or with the bootstrap loader (start vector is at address 0C00h)

hardware resources used for serial input/output:

Pins P1.1 and P2.2 for serial data transmission

Test and RST/NMI to start program execution at the reset or bootstrap loader vector

Basic clock module: Rsel=5, DCO=4, MOD=0, DCOCLK for MCLK and SMCLK, clock divider for MCLK

and SMCLK at default: dividing by 1

Timer_A: Timer_A operates in continuous mode with MCLK source selected, input divider set to 1,

using CCR0, and polling of CCIFG0.

WDT: Watchdog timer is halted

Interrupt: GIE=0, NMIIE=0, OFIFG=0, ACCVIFG=0

Memory allocation and stack pointer:

If the stack pointer points to RAM addresses above 0220h, 6 bytes of the stack are allocated plus RAM addresses 0200h to 0219h. Otherwise the stack pointer is set to 0220h and allocates RAM from 0200h to 021Fh.

NOTE:

When writing RAM data via bootstrap loader, take care that the stack is outside the range of the data being written.

Program execution begins with the user’s reset vector at FFFEh (standard method) if TEST is held low while RST

/NMI goes from low to high:

RST/NMI PIN

TEST PIN

User Program Starts

Reset Condition

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boot ROM containing bootstrap loader (continued)

Program execution begins with the bootstrap vector at 0C00h (boot ROM) if a minimum of two positive edges have been applied to TEST while RST/NMI is low, and TEST is high when RST/NMI goes from low to high. The TEST signal is normally used internally to switch pins P1.4, P1.5, P1.6, and P1.7 between their application function and the JTAG function. If the second rising edge at TEST is applied while RST internal TEST signal is held low and the pins remain in the application mode:

RST/NMI PIN

TEST PIN

Bootstrap loader Starts

TEST

(Internal)

/NMI is held low, the

Test mode can be entered again after TEST is taken low and then back high. The bootstrap loader will not be started (via the vector in address 0C00h), if:

There were less than two positive edges at TEST while RST/NMI is low

TEST is low if RST/NMI goes from low to high

JTAG has control over the MSP430 resources

Supply voltage VCC drops and a POR is executed

WARNING: The bootstrap loader starts correctly only if the RST to the NMI function, unpredictable program execution may result. However, a bootstrap-load may be started using software and the bootstrap vector, for example the instruction BR &0C00h.

/NMI pin is in reset mode. If it is switched

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flash memory

The flash memory consists of 512-byte segments in the main memory and 128-byte segments in the information memory. See device memory maps for specific device information.

Segment0 to Segment7 can be erased individually, or altogether as a group.

SegmentA and SegmentB can be erased individually, or as a group with segments 0–7.

The memory in SegmentA and SegmentB is also called

Information Memory.

VPP is generated internally. VCC current increases during programming.

During program/erase cycles, VCC must not drop below the minimum specified for program/erase operation.

Program and erase timings are controlled by the flash timing generator—no software intervention is needed. The input frequency of the flash timing generator should be in the proper range and must be applied until the write/program or erase operation is completed.

0FFFFh 0FE00h

0FDFFh

0FC00h

0FBFFh

0FA00h 0F9FFh

0F800h

0F7FFh

0F600h

0F5FFh

0F400h

0F3FFh

0F200h

0F1FFh

0F000h 010FFh

01080h 0107Fh

01000h

NOTE: All segments not implemented on all devices.

Segment0 w/

Interrupt Vectors

Segment1

Segment2

Segment3

Segment4

Segment5

Segment6

Segment7

SegmentA

SegmentB

Flash Main Memory

Memory

Information

During program or erase, no code can be executed from flash memory and all interrupts must be disabled by setting the GIE, NMIE, ACCVIE, and OFIE bits to zero. If a user program requires execution concurrent with a flash program or erase operation, the program must be executed from memory other than the flash memory (e.g., boot ROM, RAM). In the event a flash program or erase operation is initiated while the program counter is pointing to the flash memory, the CPU will execute JMP $ instructions until the flash program or erase operation is completed. Normal execution of the previously running software then resumes.

Unprogrammed, new devices may have some bytes programmed in the information memory (needed for test during manufacturing). The user should perform an erase of the information memory prior to first use.

flash memory control register FCTL1

All control bits are reset during PUC. PUC is active after V

is applied, a reset condition is applied to the

RST/NMI pin, the watchdog timer expires, a watchdog access violation occurs, or an improper flash operation has been performed. A more detailed description of the control-bit functions is found in the flash memory module description (refer to

MSP430x1xx User’s Guide

, literature number SLAU049). Any write to control register FCTL1 during erase, mass erase, or write (programming) will end in an access violation with ACCVIFG=1. Special conditions apply for segment-write mode. Refer to

MSP430x1xx User’s Guide

, literature number

SLAU049 for details.

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flash memory control register FCTL1 (continued)

Read access is possible at any time without restrictions. The control bits of control register FCTL1 are:

FCTL1

0128h

FCTL1 read:

FCTL1 write:

096h

0A5h

MSP430x11x1

MIXED SIGNAL MICROCONTROLLER

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815

SEG WRT

rw–0

WRT

rw–0

res.r0res.r0res.

MEras Erase res.

r0rw-0rw–0

Erase 0128h, bit1,

Erase a segment 0:1:No segment erase will be started.

Erase of one segment is enabled. The segment to be erased is defined by a

dummy

write into any address within the segment. The erase bit is

automatically reset when the erase operation is completed.

MEras 0128h, bit2,

Mass Erase, main memory segments are erased together. 0:1:No segment erase will be started.

Erase of main memory segments is enabled. Erase starts when a dummy write to any address in main memory is executed. The MEras bit is automatically reset when the erase operation is completed.

WRT 0128h, bit6, Bit WRT must be set for a successful write execution.

If bit WRT is reset and write access to the flash memory is attempted, an access violation occurs and ACVIFG is set.

SEGWRT 0128h, bit7,

Bit SEGWRT may be used to reduce total programming time. Refer to

MSP430x1xx User’s Guide

, literature number SLAU049 for details.

0:1:No segment-write acceleration is selected.

Segment-write is used. This bit needs to be reset and set between segment borders.

Table 3. Allowed Combinations of Control Bits Allowed for Flash Memory Access

FUNCTION PERFORMED SEGWRT WRT MEras Erase BUSY WAIT Lock

Write word or byte 0 1 0 0 0 0 0 Write word or byte in same segment, segment write mode 1 1 0 0 0 → 1 0 → 1 0 Erase one segment by writing to any address in the target segment 0 0 0 1 0 0 0 Erase all segments (0 to 7) but not the information memory

(segments A and B) Erase all segments (0 to 7 and A and B) by writing to any address in

the flash memory module

NOTE: The table shows all valid combinations. Any other combination will result in an access violation.

0 0 1 0 0 0 0

0 0 1 1 0 0 0

flash memory, timing generator, control register FCTL2

The timing generator (Figure 1) generates all the timing signals necessary for write, erase, and mass erase from the selected clock source. One of three different clock sources may be selected by control bits SSEL0 and SSEL1 in control register FCTL2. The selected clock source should be divided to meet the frequency requirements specified in the recommended operating conditions.

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MSP430x11x1 MIXED SIGNAL MICROCONTROLLER

SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000

flash memory, timing generator, control register FCTL2 (continued)

The flash timing generator is reset with PUC. It is also reset if the emergency exit bit EMEX is set. Control register FCTL2 may not be written to if the BUSY bit is set; otherwise, an access violation will occur

(ACCVIFG=1). Read access is possible at any time without restrictions.

SSEL1

SSEL0

Write ’1’ to

Reset

Flash Timing

Generator

ACLK

MCLK

SMCLK

FN5.......... FN0

Divider,

1 .. 64

PUC EMEX

BUSY WAIT

Figure 1. Flash Memory Timing Generator Diagram

FCTL2

012Ah

FCTL2 read:

FCTL2 write:

096h

0A5h

SSEL1

rw–0

SSEL0

rw–1

FN5 FN4 FN3

rw-0rw-0rw-0

FN2 FN1 FN0

The control bits are:

FN0–FN5 012Ah, bit0–5 These six bits define the division rate of the clock signal. The division

rate is 1 to 64, according to the digital value of FN5 to FN0 plus one.

rw-0rw-1rw–0

SSEL0, SSEL1 012Ah, bit6,7 Clock source select

0: ACLK 1: MCLK 2: SMCLK 3: SMCLK

The flash timing generator is reset with PUC. It is also reset if the EMEX bit is set.

flash memory control register FCTL3

There are no restrictions to modify this control register.

res.

res.r0EMEX Lock WAIT

FCTL3

012Ch

FCTL3 read:

FCTL3 write:

096h

0A5h

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ACCV

KEYV BUSY

IFG

rw-1rw-1rw-0

r(w)-0rw-(0)rw–0

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